STS4NM20N N-CHANNEL 200V - 0.11Ω - 4A SO-8 ULTRA LOW GATE CHARGE MDmesh™ II MOSFET TARGET DATA TYPE STS4NM20N ■ ■ ■ ■ ■ ■ VDSS RDS(on) ID 200 V < 0.13 Ω 4A WORLDWIDE LOWEST GATE CHARGE TYPICAL RDS(on) = 0.11Ω HIGH dv/dt and AVALANCHE CAPABILITIES LOW INPUT CAPACITANCE LOW GATE RESISTANCE TIGHT PROCESS CONTROL AND HIGH MANUFACTURING YIELDS SO-8 DESCRIPTION This 200V MOSFET with a new advanced layout brings all unique advantages of MDmesh technology to lower voltages. The device exhibits worldwide lowest gate charge for any given on-resistance.Its use is therefore ideal as primary switch in isolated DC-DC converters for Telecom and Computer applications.Used in combination with secondary-side low-voltage STripFETTM products, it contributes to reducing losses and boosting efficiency INTERNAL SCHEMATIC DIAGRAM APPLICATIONS The MDmeshTM family is very suitable for increasing power density allowing system miniaturization and higher efficiencies ORDERING INFORMATION SALES TYPE MARKING PACKAGE PACKAGING STS4NM20N S4NM20N SO-8 TAPE & REEL March 2003 1/6 STS4NM20N ABSOLUTE MAXIMUM RATINGS Symbol VDS VDGR VGS ID Parameter Value Unit Drain-source Voltage (VGS = 0) 200 V Drain-gate Voltage (RGS = 20 kΩ) 200 V Gate- source Voltage ± 30 V Drain Current (continuous) at TC = 25°C Drain Current (continuous) at TC = 100°C 4 2.83 A A 16 A IDM (2) Drain Current (pulsed) PTOT Total Dissipation at TC = 25°C 2.5 W Derating Factor (1) 0.02 W/°C 10 V/ns 50 °C/W 150 °C -55 to 150 °C Max Value Unit dv/dt (3) Peak Diode Recovery voltage slope THERMAL DATA Rthj-pcb Tj Tstg Thermal Resistance Junction-pcb Max (1) Max. Operating Junction Temperature Storage Temperature AVALANCHE CHARACTERISTICS Symbol Parameter IAR Avalanche Current, Repetitive or Not-Repetitive (pulse width limited by Tj max) TBD A EAS Single Pulse Avalanche Energy (starting Tj = 25 °C, ID = IAR, VDD = 35 V) TBD mJ ELECTRICAL CHARACTERISTICS (TCASE = 25 °C UNLESS OTHERWISE SPECIFIED) ON/OFF Symbol Parameter V(BR)DSS Drain-source Breakdown Voltage ID = 1 mA, VGS = 0 IDSS Zero Gate Voltage Drain Current (VGS = 0) VDS = Max Rating VDS = Max Rating, TC = 125 °C 1 10 µA µA IGSS Gate-body Leakage Current (VDS = 0) VGS = ± 30 V 100 µA VGS(th) Gate Threshold Voltage VDS = VGS, ID = 250 µA 4.2 5 V RDS(on) Static Drain-source On Resistance VGS = 10 V, ID = 2 A 0.11 0.13 Ω 2/6 Test Conditions Min. Typ. Max. 200 3.5 Unit V STS4NM20N ELECTRICAL CHARACTERISTICS (CONTINUED) DYNAMIC Symbol gfs (4) Ciss Coss Crss Coss eq. (*) RG Parameter Test Conditions Min. Typ. Max. Unit Forward Transconductance VDS = 15 V , ID = 2 A 1.4 S Input Capacitance Output Capacitance Reverse Transfer Capacitance VDS = 25 V, f = 1 MHz, VGS = 0 670 180 12 pF pF pF Equivalent Output Capacitance VGS = 0V, VDS = 0V to 400V TBD pF Gate Input Resistance f = 1 MHz Gate DC Bias = 0 Test Signal Level = 20 mV Open Drain TBD Ω (*) Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS SWITCHING ON Symbol Parameter Test Conditions td(on) tr Turn-on Delay Time Rise Time VDD = 100 V, ID = 2 A RG = 4.7Ω VGS = 10 V (see test circuit, Figure 3) Qg Qgs Qgd Total Gate Charge Gate-Source Charge Gate-Drain Charge VDD = 160 V, ID = 4 A, VGS = 10 V Min. Typ. Max. Unit TBD TBD ns ns 19 3.5 11 nC nC nC SWITCHING OFF Symbol tr (Voff) tf tc Parameter Off-Voltage Rise Time Fall Time Cross-Over Time Test Conditions Min. Typ. Max. TBD TBD TBD VDD = 100 V, ID = 2 A, RG = 4.7Ω, VGS = 10 V (see test circuit, Figure 3) Unit ns ns ns SOURCE DRAIN DIODE Symbol ISD Parameter Test Conditions Min. Typ. Source-drain Current Max. Unit 4 A ISDM (2) Source-drain Current (pulsed) VSD (4) Forward On Voltage ISD = 2 A, VGS = 0 Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD = 2 A, di/dt = 100 A/µs, VDD = 100 V, Tj = 25°C (see test circuit, Figure 5) 89 300 6.5 ns nC A Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD = 2 A, di/dt = 100 A/µs, VDD = 100 V, Tj = 150°C (see test circuit, Figure 5) TBD TBD TBD ns nC A trr Qrr IRRM trr Qrr IRRM Note: 1. 2. 3. 4. 16 A 1.3 V When mounted on 1 inch2 FR4 Board, 2oz of Cu, t≤ 10 sec. Pulse width limited by safe operating area. ISD ≤ 4 A, di/dt ≤ 400 A/µs, VDD ≤ V(BR)DSS, Tj ≤ TjMAX. Pulsed: Pulse duration = 400 µs, duty cycle 1.5 %. 3/6 STS4NM20N Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform Fig. 3: Switching Times Test Circuit For Resistive Load Fig. 4: Gate Charge test Circuit Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times 4/6 STS4NM20N SO-8 MECHANICAL DATA mm DIM. MIN. TYP. A a1 MIN. TYP. 1.75 0.1 0.003 0.009 1.65 0.65 MAX. 0.068 0.25 a2 a3 inch MAX. 0.064 0.85 0.025 0.033 b 0.35 0.48 0.013 0.018 b1 0.19 0.25 0.007 0.010 C 0.25 0.5 0.010 0.019 D 4.8 5.0 0.188 0.196 E 5.8 6.2 0.228 0.244 c1 45 (typ.) e 1.27 e3 3.81 0.050 0.150 F 3.8 4.0 0.14 0.157 L 0.4 1.27 0.015 0.050 M S 0.6 0.023 8 (max.) 0016023 5/6 STS4NM20N Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. © The ST logo is a registered trademark of STMicroelectronics © 2003 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. © http://www.st.com 6/6