STW47NM50 N-CHANNEL 500V - 0.065Ω - 45A TO-247 MDmesh™Power MOSFET ADVANCED DATA TYPE VDSS RDS(on) Rds(on)*Qg ID STW47NM50 500V < 0.085Ω 5.6 Ω*nC 45 A TYPICAL RDS(on) = 0.065Ω HIGH dv/dt AND AVALANCHE CAPABILITIES 100% AVALANCHE TESTED LOW INPUT CAPACITANCE AND GATE CHARGE LOW GATE INPUT RESISTANCE TIGHT PROCESS CONTROL AND HIGH MANUFACTURING YIELDS DESCRIPTION The MDmesh™ is a new revolutionary MOSFET technology that associates the Multiple Drain process with the Company’s PowerMESH™ horizontal layout. The resulting product has an outstanding low on-resistance, impressively high dv/dt and excellent avalanche characteristics. The adoption of the Company’s proprietary strip technique yields overall dynamic performance that is significantly better than that of similar competition’s products. 3 2 1 TO-247 INTERNAL SCHEMATIC DIAGRAM APPLICATIONS The MDmesh™ family is very suitable for increasing power density of high voltage converters allowing system miniaturization and higher efficiencies. ABSOLUTE MAXIMUM RATINGS Symbol Value Unit Drain-source Voltage (VGS = 0) 500 V Drain-gate Voltage (RGS = 20 kΩ) 500 V Gate- source Voltage ±30 V ID Drain Current (continuous) at TC = 25°C 45 A ID Drain Current (continuous) at TC = 100°C 28.4 A VDS VDGR VGS IDM () PTOT dv/dt (1) Tstg Tj Parameter Drain Current (pulsed) 180 A Total Dissipation at TC = 25°C 417 W Derating Factor 2.08 W/°C Peak Diode Recovery voltage slope Storage Temperature Max. Operating Junction Temperature (•)Pulse width limited by safe operating area January 2003 15 V/ns –65 to 150 °C 150 °C (1) ISD ≤45A, di/dt ≤400A/µs, VDD ≤ V(BR)DSS, Tj ≤ TJMAX. 1/6 STW47NM50 THERMAL DATA Rthj-case Thermal Resistance Junction-case Max 0.3 °C/W Rthj-amb Thermal Resistance Junction-ambient Max 30 °C/W 300 °C Tl Maximum Lead Temperature For Soldering Purpose AVALANCHE CHARACTERISTICS Symbol Max Value Unit IAR Avalanche Current, Repetitive or Not-Repetitive (pulse width limited by Tj max) Parameter 20 A EAS Single Pulse Avalanche Energy (starting Tj = 25 °C, ID = IAR, VDD = 35 V) 810 mJ ELECTRICAL CHARACTERISTICS (TCASE = 25 °C UNLESS OTHERWISE SPECIFIED) OFF Symbol V(BR)DSS IDSS IGSS Parameter Test Conditions Min. Typ. Max. 500 Unit Drain-source Breakdown Voltage ID = 250 µA, VGS = 0 V Zero Gate Voltage Drain Current (VGS = 0) VDS = Max Rating 10 µA VDS = Max Rating, TC = 125 °C 100 µA Gate-body Leakage Current (VDS = 0) VGS = ±30 V ±100 nA ON (1) Symbol Parameter Test Conditions VGS(th) Gate Threshold Voltage VDS = VGS, ID = 250 µA RDS(on) Static Drain-source On Resistance VGS = 10 V, ID = 22.5 A Min. Typ. Max. Unit 3 4 5 V 0.065 0.085 Ω Typ. Max. Unit DYNAMIC Symbol gfs (1) Parameter Forward Transconductance Test Conditions VDS > ID(on) x RDS(on)max, ID = 22.5A VDS = 25V, f = 1 MHz, VGS = 0 Min. 20 S Ciss Input Capacitance 3700 pF Coss Output Capacitance 610 pF Crss Reverse Transfer Capacitance 50 pF Coss eq. (2) Equivalent Output Capacitance VGS = 0V, VDS = 0V to 400V 325 pF Gate Input Resistance f=1 MHz Gate DC Bias = 0 Test Signal Level = 20mV Open Drain 1.7 Ω RG 1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %. 2. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS. 2/6 STW47NM50 ELECTRICAL CHARACTERISTICS (CONTINUED) SWITCHING ON Symbol td(on) tr Parameter Turn-on Delay Time Rise Time Qg Total Gate Charge Qgs Gate-Source Charge Qgd Gate-Drain Charge Test Conditions Min. VDD = 250V, ID = 22.5 A RG = 4.7Ω VGS = 10 V (see test circuit, Figure 3) VDD = 400 V, ID = 45 A, VGS = 10 V Typ. Max. Unit 40 ns 35 ns 87 117 nC 23 nC 42 nC SWITCHING OFF Symbol tr(Voff) Parameter Off-voltage Rise Time tf Fall Time tc Cross-over Time Test Conditions Min. VDD = 400 V, ID = 45 A, RG = 4.7Ω, VGS = 10 V (see test circuit, Figure 5) Typ. Max. Unit 18 ns 23 ns 44 ns SOURCE DRAIN DIODE Symbol Max. Unit Source-drain Current 45 A ISDM (2) Source-drain Current (pulsed) 180 A VSD (1) Forward On Voltage ISD = 45 A, VGS = 0 1.5 V Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD = 40 A, di/dt = 100A/µs, VDD = 100 V, Tj = 25°C (see test circuit, Figure 5) 520 7.8 30 ns µC A Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD = 40 A, di/dt = 100A/µs, VDD = 100 V, Tj = 150°C (see test circuit, Figure 5) 680 11.2 33 ns µC A ISD trr Qrr IRRM trr Qrr IRRM Parameter Test Conditions Min. Typ. Note: 1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %. 2. Pulse width limited by safe operating area. 3/6 STW47NM50 Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform Fig. 3: Switching Times Test Circuit For Resistive Load Fig. 4: Gate Charge test Circuit Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times 4/6 STW47NM50 TO-247 MECHANICAL DATA DIM. mm. MIN. TYP inch MAX. MIN. TYP. MAX. 0.19 0.20 A 4.85 5.15 D 2.20 2.60 0.08 0.10 E 0.40 0.80 0.015 0.03 F 1 1.40 0.04 0.05 F1 3 0.11 F2 2 0.07 F3 2 2.40 0.07 0.09 F4 3 3.40 0.11 0.13 G 10.90 0.43 H 15.45 15.75 0.60 0.62 L 19.85 20.15 0.78 0.79 L1 3.70 4.30 0.14 L2 L3 18.50 14.20 0.17 0.72 14.80 0.56 0.58 L4 34.60 1.36 L5 5.50 0.21 M 2 3 0.07 0.11 V 5º 5º V2 60º 60º Dia 3.55 3.65 0.14 0.143 5/6 STW47NM50 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. 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