2
SCHS311 – JANUARY 2001
Inputs Are TTL-Voltage Compatible
Speed of Bipolar FCT, AS, and S, With
CD54ACT05 . . . F PACKAGE
CD74ACT05 . . . E OR M PACKAGE
(TOP VIEW)
Significantly Reduced Power Consumption
Balanced Propagation Delays
±24-mA Output Drive Current
1A
1Y
2A
2Y
3A
3Y
GND
– Fanout to 15 FCT Devices
– Drives 50-Ω Transmission Lines
SCR-Latchup-Resistant CMOS Process and
Circuit Design
Exceeds 2-kV ESD Protection Per
MIL-STD-883, Method 3015
1
14
2
13
3
12
4
11
5
10
6
9
7
8
VCC
6A
6Y
5A
5Y
4A
4Y
description
The ’ACT05 devices contain six independent inverters. These devices perform the Boolean function Y = A. The
open-drain outputs require pullup resistors to perform correctly, and can be connected to other open-drain
outputs to implement active-low wired-OR or active-high wired-AND functions.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
PACKAGE†
TA
PDIP – E
–40°C
40 C to 85°C
85 C
SOIC – M
Tube
CD74ACT05E
Tube
CD74ACT05M
Tape and reel
CD74ACT05M96
TOP-SIDE
MARKING
CD74ACT05E
ACT05M
–55°C to 125°C
CDIP – F
Tube
CD54ACT05F3A
CD54ACT05F3A
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
FUNCTION TABLE
(each inverter)
INPUT
A
OUTPUT
Y
H
L
L
Z
logic symbol‡
1A
2A
3A
4A
5A
6A
1
2
1
3
4
5
6
9
8
11
10
13
12
1Y
2Y
3Y
4Y
5Y
6Y
‡ This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2001, Texas Instruments Incorporated
%(")+'-%)( %, .++!(- , )" *.&%-%)( -!
+) .-, )(")+' -) ,*!%"%-%)(, *!+ -$! -!+', )" !0, (,-+.'!(-,
,-( + /++(-1 +) .-%)( *+)!,,%(# )!, ()- (!!,,+%&1 %(&. !
-!,-%(# )" && *+'!-!+,
( *+) .-, )'*&%(- -) 22 && *+'!-!+, +! -!,-!
.(&!,, )-$!+/%,! ()-! ( && )-$!+ *+) .-, *+) .-%)(
*+)!,,%(# )!, ()- (!!,,+%&1 %(&. ! -!,-%(# )" && *+'!-!+,
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1
SCHS311 – JANUARY 2001
logic diagram, each inverter (positive logic)
A
Y
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6 V
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 2): E package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W
M package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
TA = 25°C
MIN
MAX
VCC
VIH
Supply voltage
4.5
VIL
VI
Low-level input voltage
Input voltage
0
VO
IOH
Output voltage
0
IOL
∆t/∆v
Low-level output current
High-level input voltage
5.5
2
CD54ACT05
MAX
MIN
MAX
4.5
5.5
4.5
5.5
2
0.8
High-level output current
VCC
VCC
0
0
10
VCC
VCC
0
0
–24
24
0
2
0.8
–24
Input transition rise or fall rate
CD74ACT05
MIN
24
0
10
0
UNIT
V
V
0.8
V
VCC
VCC
V
–24
mA
V
24
mA
10
ns/V
TA
Operating free-air temperature
–55
125
–40
85
°C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
2
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SCHS311 – JANUARY 2001
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VOL
TEST CONDITIONS
VI = VIH or VIL
II
ICC
VI = VCC or GND
VI = VCC or GND,
∆ICC
Ci
VI = VCC –2.1 V
TA = 25°C
MIN
MAX
VCC
CD54ACT05
MIN
MAX
CD74ACT05
MIN
MAX
IOL = 50 µA
IOL = 24 mA
IOL = 50 mA†
4.5 V
0.1
0.1
0.1
4.5 V
0.36
0.5
0.44
IOL = 75 mA†
5.5 V
5.5 V
V
1.65
1.65
5.5 V
IO = 0
UNIT
5.5 V
4.5 V to 5.5 V
±0.1
±1
±1
µA
4
80
40
µA
2.4
3
2.8
mA
10
10
10
pF
† Test one output at a time, not exceeding 1-second duration. Measurement is made by forcing indicated current and measuring voltage to minimize
power dissipation. Test verifies a minimum 50-Ω transmission-line drive capability at 85°C and 75-Ω transmission-line drive capability at 125°C.
ACT INPUT LOAD TABLE
INPUT
UNIT LOAD
A
0.18
Unit load is ∆ICC limit specified in
electrical characteristics table
(e.g., 2.4 mA at 25°C).
switching characteristics over recommended operating free-air temperature range,
VCC = 5 V ± 0.5 V, CL = 50 pF (unless otherwise noted) (see Figure 1)
PARAMETER
tPZL
tPLZ
FROM
(INPUT)
TO
(OUTPUT)
A or B
Y
CD54ACT05
CD74ACT05
MIN
MAX
MIN
MAX
2.3
9.3
2.4
8.5
2.7
10.8
2.8
9.8
UNIT
ns
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER
Cpd
Power dissipation capacitance
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TYP
UNIT
105
pF
3
SCHS311 – JANUARY 2001
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
CL = 50 pF
(see Note A)
R1 = 500 Ω† S1
2 × VCC
VCC
50% VCC
Input
50% VCC
0V
R2 = 500 Ω†
tPHZ
50% VCC
Output
† When VCC = 1.5 V, R1 = R2 = 1 kΩ
LOAD CIRCUIT
tPLZ
≈VCC
20% VCC
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns.
C. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
4
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TI warrants performance of its products to the specifications applicable at the time of sale in accordance with
TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary
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those mandated by government requirements.
Customers are responsible for their applications using TI components.
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Copyright 2001, Texas Instruments Incorporated