www.fairchildsemi.com FMS72509 Phase Locked Loop Clock Driver Features Description • • • • • • • • • • FMS72509 is a zero delay clock buffer designed for high fan out applications. It contains 10 outputs. It provides precise phase and frequency alignment between incoming clock and the output clocks. This makes it ideal for high speed application in the range of 25 to 140 MHz. The Phase Locked Loop is capable of tracking incoming clock modulation of up to ±1% of the clock period. With the exception of FBOUT, the output Enable (OE) pin, when pulled low, will force the outputs to logic low. PC-133 Spread Spectrum Compliant Frequency Range of 25 to 140 MHz VDD Range of 3.0 to 3.6 Volts Up to 11 outputs Less than 100 pS of Output to Output Skew Less than 90 pS of Cycle to Cycle Jitter Output Enable pin Integrated Damping Resistor Commercial Temperature Range Available in 24 pin TSSOP Block Diagram OE1 FB O U T Q0 Q1 Q2 Q3 FBIN PLL CLKIN Control Logic Q4 Q5 Q6 Q7 Q8 Q9 OE2 REV. 1.0 8/11/00 PRODUCT SPECIFICATION FMS72509 Pin Assignments 24 TSSO P AGND 1 24 VDD 2 23 AVDD Q0 3 22 VDD Q1 4 21 Q8 Q2 5 20 Q7 GND 6 19 GND GND 7 18 GND Q3 8 17 Q6 Q4 9 16 Q5 VDD 10 15 VDD FMS72509 CL KI N O E1 11 14 OE2 FBOUT 12 13 FB I N Pin Description Pin Name Pin # Pin Type Pin Function Description GND 6, 7, 18, 19 PWR Ground Connection: Connect all ground pins to the common system ground plane. AGND 1 PWR Analog Ground Connection: Connect to common system ground plane. VDD 2, 10, 15, 22 PWR Power Connection: Power supply for all the outputs. AVDD 23 PWR Power Connection: Power supply for the PLL. In addition, it can be used to bypass the PLL. Q(0:4) 3, 4, 5, 8, 9 OUT Clock outputs: Clock outputs 0:4 are buffer clocks of input. OE1 11 IN FBOUT 12 OUT FBIN 13 IN Feedback Clock Input: PLL feedback input. The user connects it to FBOUT. OE2 14 IN Outputs Enable 2: When low, outputs 5:8 are logic low. Normal operation when asserted high. This function is only for FMS72509. Outputs Enable 1: When low, outputs, with the exception of FBOUT, Q0 to Q4 are to logic low. Normal operation when asserted high. Feedback Clock Output: Dedicated pin for FB pin. It is not effected by OE pin. VDD 15 PWR Power Connection: Power supply for PLL. Connect to 3.3V. Q(5:8) 16,17, 20, 21 OUT Clock outputs: Outputs are buffer clocks of input. CLKIN 24 IN Input Clock: Input clock to the PLL. Functionality Table AVDD OE1 OE2 PLL Q(0:4) Q(5:8) FBOUT L L L BYPASS L L X(1) L L H BYPASS L X(1) X(1) L H L BYPASS X(1) L X(1) H L L Enabled L L Note 2 H L H Enabled L Note 2 Note 2 H H H Enabled Note 2 Note 2 Note 2 NOTES: 1. Depending on the state of the CLKIN, it will be High or Low. 2. Lock in phase with CLKIN. 2 REV. 1.0 8/11/00 FMS72509 PRODUCT SPECIFICATION Absolute Maximum Rating Symbol VDD, VIN Parameter Ratings Units Voltage on any pin with respect to ground –0.5 to 7.0 V TSTG Storage Temperature –65 to 150 °C TB Ambient Temperature –55 to 125 °C TA Operating Temperature 0 to 70 °C Stresses greater than those listed in the table may cause permanent damage to the device. These represent a stress rating only. Operation of the device at these or any other conditions above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may effect reliability. DC Electrical Characteristics TA = 0 to 70°C; Supply Voltage 3.3 V ±0.3V (unless otherwise stated) Parameter Symbol Conditions Min. Typ. Max. Units Input Low Voltage VIL GND – 0.3 0.8 V Input High Voltage VIH 2.0 VDD + 0.3 V Input Low Current IIL VIN = 0 -10 10 µA Input High Current IIH VIN = VDD -10 10 µA 2.4 High Output Voltage VOH IOH = -6mA Low Output Voltage VOL IOL = 15mA Input Capacitance CIN Frequency = 10MHz Supply Current IDD Frequency = 100 MHz; CL = 12pF Frequency = 133 MHz; CL = 12pF (1) (1) Clock Stabilization TSTAB 3.1 V 0.5 0.8 V 6.0 pF 200 290 mA 230 320 mA 1 mS 2.5 From VDD = 3.3 V to 1% Target NOTE: 1. Guaranteed by design, not subject to 100% production testing. AC Electrical Characteristics TA = 0 to 70°C; Supply Voltage VDD = 3.3V ±0.3V, CL = 12 pF (unless otherwise stated) Parameter Symbol (1) Conditions Typ. Units 60 % DT_IN Input Frequency Range FIN 140 MHz Rise Time(1) TR 0.4 to 2.0V – 1.0 2.0 nS TF 2.0 to 0.4V – 1.0 2.0 nS DT VTH = 1.25V 40 60 % TJIT VTH = 1.25V; 100 & 133MHz -120 120 pS Fall Time (1) Duty Cycle (1) Jitter (Cycle-Cycle) (1) Spread Spectrum Induced Skew 40 Max. Clock Input Duty Cycle (1) AVDD = 3.3V Min. 25 TSK_SSC VTH = VDD/2 -200 200 pS Output to Output Skew(1) TSK1 VTH = VDD/2 -120 120 pS (1,2) TSK2 CLFB = 4 pF;100 & 133MHz -100 100 pS Input to Output Delay NOTE: 1. Guaranteed by design, not subject to 100% production testing. 2. Feedback trace length of 0.7”. REV. 1.0 8/11/00 3 PRODUCT SPECIFICATION FMS72509 Parameter Measurement Information Duty Cycle Timing (DT) t1 t2 DT = 1.5V 1.5V 1.5V t2 t1 x 100 Rise/Fall Time (TR/TF) 2.0V 2.0V 3.3V 0.4V 0.4V 0V OUTPUT TR TF Output to Output Skew (TSK1) 1.5V Q0 1.5V Any Output TSK1 Input to Output Delay (TSK2) 1.5V CLKIN 1.5V FBIN TSK2 4 REV. 1.0 8/11/00 FMS72509 PRODUCT SPECIFICATION Application Diagram CLKIN Q0 IN PLL QN FBIN FBOUT C Note: Feedback capacitor value 'C' is to be determined based on the phase characteristics of the PLL. REV. 1.0 8/11/00 5 PRODUCT SPECIFICATION FMS72509 Mechanical Dimensions 24-Lead TSSOP Package Inches Symbol Millimeters Min. Max. Min. Max. A A1 B C D — .002 .007 .004 .308 .047 .006 — 0.05 0.19 0.09 7.70 1.20 0.15 E e H .172 .180 .026 BSC .256 BSC .018 .030 4.30 4.50 0.65 BSC 6.40 BSC 0.45 0.75 24 24 L N α ccc .012 .008 .316 0.30 0.20 7.90 0° 8° 0° 8° — .004 — 0.10 Notes: Notes 1. Dimensioning and tolerancing per ANSI Y14.5M-1982. 2. "D" and "E" do not include mold flash. Mold flash or protrusions shall not exceed .006 inch (0.15mm). 3. "L" is the length of terminal for soldering to a substrate. 4. Terminal numbers are shown for reference only. 5. Symbol "N" is the maximum number of terminals. 2 2 3 5 D E H C A1 A B e SEATING PLANE –C– α L LEAD COPLANARITY ccc C 6 REV. 1.0 8/11/00 PRODUCT SPECIFICATION FMS72509 Ordering Information Product Number Tape & Reel Package FMS72509MTC FMS72509MTCT TSSOP-24 LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com 8/11/00 0.0m 002 Stock#DS300072509 2000 Fairchild Semiconductor Corporation