DATA SHEET MOS INTEGRATED CIRCUIT µ PD431000A 1M-BIT CMOS STATIC RAM 128K-WORD BY 8-BIT Description The µPD431000A is a high speed, low power, and 1,048,576 bits (131,072 words by 8 bits) CMOS static RAM. The µPD431000A has two chip enable pins (/CE1, CE2) to extend the capacity. And battery backup is available. In addition to this, A and B versions are low voltage operations. The µPD431000A is packed in 32-pin plastic DIP, 32-pin plastic SOP and 32-pin plastic TSOP (I) (8 × 13.4 mm) and (8 × 20 mm). Features • 131,072 words by 8 bits organization • Fast access time: 70, 85, 100, 120, 150 ns (MAX.) • Low voltage operation (A version: VCC = 3.0 to 5.5 V, B version: VCC = 2.7 to 5.5 V) • Operating ambient temperature: TA = 0 to 70 °C • Low VCC data retention: 2.0 V (MIN.) • Output Enable input for easy application • Two Chip Enable inputs: /CE1, CE2 Part number Access time ns (MAX.) µPD431000A-xxL 70, 85 Operating supply Operating ambient Supply current voltage temperature At operating At standby At data retention V °C mA (MAX.) µA (MAX.) µA (MAX.) Note1 4.5 to 5.5 0 to 70 70 100 15 20 3 µPD431000A-xxLL µPD431000A-Axx µPD431000A-Bxx 70 70 Note2 Note2 , 100 3.0 to 5.5 35 Note3 13 Note5 , 120, 150 2.7 to 5.5 30 Note4 11 Note6 Notes 1. TA ≤ 40 °C 2. VCC = 4.5 to 5.5 V 3. 70 mA (VCC > 3.6 V) 4. 70 mA (VCC > 3.3 V) 5. 20 µA (VCC > 3.6 V) 6. 20 µA (VCC > 3.3 V) The information in this document is subject to change without notice. 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Document No. M11657EJAV0DS00 (10th edition) Date Published April 2001 NS CP (K) Printed in Japan The mark ★ shows major revised points. © 1990, 1993, 1995 µPD431000A Ordering Information Part number Package Access time Operating supply Operating ambient ns (MAX.) µPD431000ACZ-70L 32-PIN PLASTIC DIP 70 µPD431000ACZ-85L (15.24mm (600)) 85 µPD431000ACZ-70LL 70 µPD431000ACZ-85LL 85 µPD431000AGW-70L 32-PIN PLASTIC SOP 70 µPD431000AGW-85L (13.34 mm (525)) 85 voltage temperature V °C 4.5 to 5.5 0 to 70 Remark L version LL version 4.5 to 5.5 L version µPD431000AGW-70LL 70 µPD431000AGW-85LL 85 µPD431000AGW-A10 100 3.0 to 5.5 A version µPD431000AGW-B12 120 2.7 to 5.5 B version µPD431000AGW-B15 150 4.5 to 5.5 L version µPD431000AGZ-85L-KJH 32-PIN PLASTIC TSOP(I) 85 µPD431000AGZ-70LL-KJH (8x20) (Normal bent) 70 LL version LL version µPD431000AGZ-85LL-KJH 85 µPD431000AGZ-B15-KJH 150 2.7 to 5.5 B version µPD431000AGZ-70LL-KKH 32-PIN PLASTIC TSOP(I) 70 4.5 to 5.5 LL version µPD431000AGZ-B15-KKH (8x20) (Reverse bent) 150 2.7 to 5.5 B version µPD431000AGU-B12-9JH 32-PIN PLASTIC TSOP(I) 120 2.7 to 5.5 B version µPD431000AGU-B15-9JH (8x13.4) (Normal bent) 150 2 Data Sheet M11657EJAV0DS µPD431000A Pin Configurations (Marking Side) /xxx indicates active low signal. 32-PIN PLASTIC DIP (15.24 mm (600)) [µPD431000ACZ-xxL] [µPD431000ACZ-xxLL] NC 1 32 VCC A16 2 31 A15 A14 3 30 CE2 A12 4 29 /WE A7 5 28 A13 A6 6 27 A8 A5 7 26 A9 A4 8 25 A11 A3 9 24 /OE A2 10 23 A10 A1 11 22 /CE1 A0 12 21 I/O8 I/O1 13 20 I/O7 I/O2 14 19 I/O6 I/O3 15 18 I/O5 GND 16 17 I/O4 A0 - A16 : Address inputs I/O1 - I/O8 : Data inputs / outputs /CE1, CE2 : Chip Enable 1, 2 /WE : Write Enable /OE : Output Enable VCC : Power supply GND : Ground NC : No connection Remark Refer to Package Drawings for the 1-pin index mark. Data Sheet M11657EJAV0DS 3 µPD431000A 32-PIN PLASTIC SOP (13.34 mm (525)) [µPD431000AGW-xxL] [µPD431000AGW-xxLL] [µPD431000AGW-Axx] [µPD431000AGW-Bxx] NC 1 32 VCC A16 2 31 A15 A14 3 30 CE2 A12 4 29 /WE A7 5 28 A13 A6 6 27 A8 A5 7 26 A9 A4 8 25 A11 A3 9 24 /OE A2 10 23 A10 A1 11 22 /CE1 A0 12 21 I/O8 I/O1 13 20 I/O7 I/O2 14 19 I/O6 I/O3 15 18 I/O5 GND 16 17 I/O4 A0 - A16 : Address inputs I/O1 - I/O8 : Data inputs / outputs /CE1, CE2 : Chip Enable 1, 2 /WE : Write Enable /OE : Output Enable VCC : Power supply GND : Ground NC : No connection Remark Refer to Package Drawings for the 1-pin index mark. 4 Data Sheet M11657EJAV0DS µPD431000A 32-PIN PLASTIC TSOP(I) (8x20) (Normal bent) [µPD431000AGZ-xxL-KJH] [µPD431000AGZ-xxLL-KJH] [µPD431000AGZ-Bxx-KJH] A11 A9 A8 A13 /WE CE2 A15 VCC NC A16 A14 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 /OE A10 /CE1 I/O8 I/O7 I/O6 I/O5 I/O4 GND I/O3 I/O2 I/O1 A0 A1 A2 A3 32-PIN PLASTIC TSOP(I) (8x20) (Reverse bent) [µPD431000AGZ-xxLL-KKH] [µPD431000AGZ-Bxx-KKH] /OE A10 /CE1 I/O8 I/O7 I/O6 I/O5 I/O4 GND I/O3 I/O2 I/O1 A0 A1 A2 A3 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A0 - A16 : Address inputs I/O1 - I/O8 : Data inputs / outputs /CE1, CE2 : Chip Enable 1, 2 /WE : Write Enable /OE : Output Enable VCC : Power supply GND : Ground NC : No connection A11 A9 A8 A13 /WE CE2 A15 VCC NC A16 A14 A12 A7 A6 A5 A4 Remark Refer to Package Drawings for the 1-pin index mark. Data Sheet M11657EJAV0DS 5 µPD431000A 32-PIN PLASTIC TSOP(I) (8x13.4) (Normal bent) [µPD431000AGU-Bxx-9JH] A11 A9 A8 A13 /WE CE2 A15 VCC NC A16 A14 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 A0 - A16 : Address inputs I/O1 - I/O8 : Data inputs / outputs /CE1, CE2 : Chip Enable 1, 2 /WE : Write Enable /OE : Output Enable VCC : Power supply GND : Ground NC : No connection Remark Refer to Package Drawings for the 1-pin index mark. 6 Data Sheet M11657EJAV0DS /OE A10 /CE1 I/O8 I/O7 I/O6 I/O5 I/O4 GND I/O3 I/O2 I/O1 A0 A1 A2 A3 µPD431000A Block Diagram VCC GND A0 Address buffer A16 Row decoder I/O1 Input data controller I/O8 Memory cell array 1,048,576 bits Sense amplifier / Switching circuit Output data controller Column decoder Address buffer /CE1 CE2 /OE /WE Truth Table /CE1 CE2 /OE /WE Mode I/O Supply current H × × × Not selected High impedance ISB × L × × L H H H Output disable L H L H Read DOUT L H × L Write DIN ICCA Remark × : VIH or VIL Data Sheet M11657EJAV0DS 7 µPD431000A Electrical Specifications Absolute Maximum Ratings Parameter Symbol Supply voltage Condition Rating VCC –0.5 –0.5 Note Note Unit to +7.0 V to VCC + 0.5 V Input / Output voltage VT Operating ambient temperature TA 0 to 70 °C Storage temperature Tstg –55 to +125 °C Note –3.0 V (MIN.) (Pulse width: 30 ns) Caution Exposing the device to stress above those listed in Absolute Maximum Rating could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Recommended Operating Conditions Parameter Symbol Condition µPD431000A-xxL µPD431000A-Axx µPD431000A-Bxx Unit µPD431000A-xxLL MIN. MAX. MIN. MAX. MIN. MAX. Supply voltage VCC 4.5 5.5 3.0 5.5 2.7 5.5 V High level input voltage VIH 2.2 VCC+0.5 2.2 VCC+0.5 2.2 VCC+0.5 V Low level input voltage VIL –0.3 +0.5 V Operating ambient temperature TA 0 70 °C Note +0.8 70 –0.3 Note 0 +0.5 –0.3 70 0 Note Note –3.0 V (MIN.) (Pulse width: 30 ns) Capacitance (TA = 25 °C, f = 1 MHz) Parameter Symbol Test conditions MIN. TYP. MAX. Unit Input capacitance CIN VIN = 0 V 6 pF Input / Output capacitance CI/O VI/O = 0 V 10 pF Remarks 1. VIN : Input voltage VI/O : Input / Output voltage 2. These parameters are not 100% tested. 8 Data Sheet M11657EJAV0DS µPD431000A DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) (1/2) Parameter Input leakage Symbol Test condition µPD431000A-xxL µPD431000A-xxLL µPD431000A-Axx MIN. TYP. MAX. MIN. TYP. MAX. MIN. TYP. MAX. Unit ILI VIN = 0 V to VCC –1.0 +1.0 –1.0 +1.0 –1.0 +1.0 µA ILO VI/O = 0 V to VCC, –1.0 +1.0 –1.0 +1.0 –1.0 +1.0 µA 70 mA current I/O leakage current /CE1 = VIH or CE2 = VIL or /WE = VIL or /OE = VIH Operating ICCA1 supply current /CE1 = VIL, CE2 = VIH, 40 70 40 70 40 II/O = 0 mA VCC ≤ 3.6 V – – 35 /CE1 = VIL, CE2 = VIH, II/O = 0 mA, 15 15 15 Cycle time = ∞ – – 8 10 10 10 – – 8 3 3 3 – – 2 Minimum cycle time ICCA2 ICCA3 VCC ≤ 3.6 V /CE1 ≤ 0.2 V, CE2 ≥ VCC – 0.2 V, Cycle time = 1 µs, II/O = 0 mA, VIL ≤ 0.2 V, VIH ≥ VCC – 0.2 V VCC ≤ 3.6 V Standby ISB /CE1 = VIH or CE2 = VIL VCC ≤ 3.6 V supply current ISB1 /CE1 ≥ VCC − 0.2 V, CE2 ≥ VCC − 0.2 V ISB2 2 VCC ≤ 3.6 V VOH1 CE2 ≤ 0.2 V 20 1 20 – 0.5 13 2 100 1 20 1 20 – – – – 0.5 13 2.4 2.4 2.4 IOH = –0.5 mA – – 2.4 VOH2 IOH = –0.02 mA – – VCC–0.1 VOL1 IOL = 2.1 mA, VCC ≥ 4.5 V output voltage Low level IOH = –1.0 mA, VCC ≥ 4.5 V 1 – VCC ≤ 3.6 V High level 100 output voltage VOL2 mA µA V 0.4 0.4 0.4 IOL = 1.0 mA – – 0.4 IOL = 0.02 mA – – 0.1 V Remarks 1. VIN : Input voltage VI/O : Input / Output voltage 2. These DC characteristics are in common regardless product classification. Data Sheet M11657EJAV0DS 9 µPD431000A DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) (2/2) Parameter Symbol µPD431000A-Bxx Test condition MIN. TYP. Unit MAX. Input leakage current ILI VIN = 0 V to VCC –1.0 +1.0 µA I/O leakage current ILO VI/O = 0 V to VCC, /CE1 = VIH or CE2 = VIL –1.0 +1.0 µA 70 mA or /WE = VIL or /OE = VIH Operating supply current ICCA1 /CE1 = VIL, CE2 = VIH, II/O = 0 mA Minimum cycle time ICCA2 VCC ≤ 3.3 V 30 /CE1 = VIL, CE2 = VIH, II/O = 0 mA, Cycle time = ∞ ICCA3 40 15 VCC ≤ 3.3 V 7 /CE1 ≤ 0.2 V, CE2 ≥ VCC – 0.2 V, 10 Cycle time = 1 µs, II/O = 0 mA, VIL ≤ 0.2 V, VIH ≥ VCC – 0.2 V Standby supply current ISB VCC ≤ 3.3 V 7 /CE1 = VIH or CE2 = VIL 3 VCC ≤ 3.3 V ISB1 2 /CE1 ≥ VCC − 0.2 V, CE2 ≥ VCC − 0.2 V VCC ≤ 3.3 V ISB2 CE2 ≤ 0.2 V VCC ≤ 3.3 V High level output voltage Low level output voltage 20 0.5 11 1 20 0.5 11 2.4 IOH = –0.5 mA 2.4 VOH2 IOH = –0.02 mA VCC–0.1 VOL1 IOL = 2.1 mA, VCC ≥ 4.5 V 0.4 IOL = 1.0 mA 0.4 IOL = 0.02 mA 0.1 VOL2 Remarks 1. VIN : Input voltage VI/O : Input / Output voltage 2. These DC characteristics are in common regardless product classification. 10 1 IOH = –1.0 mA, VCC ≥ 4.5 V VOH1 Data Sheet M11657EJAV0DS mA µA V V µPD431000A AC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) AC Test Conditions [µPD431000A-70L, µPD431000A-85L, µPD431000A-70LL, µPD431000A-85LL] Input Waveform (Rise and Fall Time ≤ 5 ns) 2.2 V 1.5 V Test points 1.5 V 1.5 V Test points 1.5 V 0.8 V Output Waveform Output Load AC characteristics should be measured with the following output load conditions. Figure 1 Figure 2 (tAA, tCO1, tCO2, tOE, tOH) (tLZ1, tLZ2, tOLZ, tHZ1, tHZ2, tOHZ, tWHZ, tOW ) +5 V +5 V 1.8 kΩ 1.8 kΩ I/O (Output) I/O (Output) 990 Ω 990 Ω 100 pF CL 5 pF CL Remark CL includes capacitance of the probe and jig, and stray capacitance. [µPD431000A-A10, µPD431000A-B12, µPD431000A-B15] Input Waveform (Rise and Fall Time ≤ 5 ns) 2.2 V 1.5 V Test points 1.5 V 1.5 V Test points 1.5 V 0.5 V Output Waveform Output Load AC characteristics should be measured with the following output load conditions. Part number Output load condition tAA, tCO1, tCO2, tOE, tOH tLZ1, tLZ2, tOLZ, tHZ1, tHZ2, tOHZ, tWHZ, tOW µPD431000A-A10, 431000A-B12 1TTL + 50 pF 1TTL + 5 pF µPD431000A-B15 1TTL + 100 pF 1TTL + 5 pF Data Sheet M11657EJAV0DS 11 µPD431000A Read Cycle (1/2) Parameter VCC ≥ 4.5 V Symbol µPD431000A-70 VCC ≥ 3.0 V µPD431000A-85 Unit Condition µPD431000A-A10 µPD431000A-Axx µPD431000A-Bxx MIN. MAX. MIN. 70 MAX. 85 MIN. MAX. Read cycle time tRC 100 ns Address access time tAA 70 85 100 ns /CE1 access time tCO1 70 85 100 ns CE2 access time tCO2 70 85 100 ns /OE to output valid tOE 35 45 50 ns Output hold from address change tOH 10 10 10 ns /CE1 to output in low impedance tLZ1 10 10 10 ns CE2 to output in low impedance tLZ2 10 10 10 ns /OE to output in low impedance tOLZ 5 5 5 ns /CE1 to output in high impedance tHZ1 25 30 35 ns CE2 to output in high impedance tHZ2 25 30 35 ns /OE to output in high impedance tOHZ 25 30 35 ns Note Note See the output load. Remark These AC characteristics are in common regardless of package types. Read Cycle (2/2) Parameter VCC ≥ 2.7 V Symbol µPD431000A-B12 MIN. MAX. 120 Unit µPD431000A-B15 MIN. MAX. Read cycle time tRC Address access time tAA 120 150 ns /CE1 access time tCO1 120 150 ns CE2 access time tCO2 120 150 ns /OE to output valid tOE 60 70 ns Output hold from address change tOH 10 10 ns /CE1 to output in low impedance tLZ1 10 10 ns CE2 to output in low impedance tLZ2 10 10 ns /OE to output in low impedance tOLZ 5 5 ns /CE1 to output in high impedance tHZ1 40 50 ns CE2 to output in high impedance tHZ2 40 50 ns /OE to output in high impedance tOHZ 40 50 ns 150 Note See the output load. Remark These AC characteristics are in common regardless of package types. 12 Data Sheet M11657EJAV0DS Condition ns Note µPD431000A Read Cycle Timing Chart tRC Address (Input) tAA tOH /CE1 (Input) tHZ1 tCO1 tLZ1 CE2 (Input) tCO2 tHZ2 tLZ2 /OE (Input) tOE tOHZ tOLZ I/O (Output) High impedance Data out Remark In read cycle, /WE should be fixed to high level. Data Sheet M11657EJAV0DS 13 µPD431000A Write Cycle (1/2) Parameter VCC ≥ 4.5 V Symbol µPD431000A-70 ` VCC ≥ 3.0 V µPD431000A-85 Unit Condition µPD431000A-A10 µPD431000A-Axx µPD431000A-Bxx MIN. MAX. MIN. MAX. MIN. MAX. Write cycle time tWC 70 85 100 ns /CE1 to end of write tCW1 55 70 80 ns CE2 to end of write tCW2 55 70 80 ns Address valid to end of write tAW 55 70 80 ns Address setup time tAS 0 0 0 ns Write pulse width tWP 50 60 60 ns Write recovery time tWR 5 5 0 ns Data valid to end of write tDW 35 35 60 ns Data hold time tDH 0 0 0 ns /WE to output in high impedance tWHZ Output active from end of write tOW 25 30 5 35 5 5 ns Note ns Note See the output load. Remark These AC characteristics are in common regardless package types. Write Cycle (2/2) Parameter VCC ≥ 2.7 V Symbol µPD431000A-B12 MIN. MAX. Unit µPD431000A-B15 MIN. MAX. Write cycle time tWC 120 150 ns /CE1 to end of write tCW1 100 120 ns CE2 to end of write tCW2 100 120 ns Address valid to end of write tAW 100 120 ns Address setup time tAS 0 0 ns Write pulse width tWP 85 100 ns Write recovery time tWR 0 0 ns Data valid to end of write tDW 60 80 ns Data hold time tDH 0 0 ns /WE to output in high impedance tWHZ Output active from end of write tOW 40 5 50 5 Note See the output load. Remark These AC characteristics are in common regardless of package types. 14 Data Sheet M11657EJAV0DS Condition ns ns Note µPD431000A Write Cycle Timing Chart 1 (/WE Controlled) tWC Address (Input) tCW1 /CE1 (Input) tCW2 CE2 (Input) tAW tAS tWP tWR /WE (Input) tOW tWHZ I/O (Input / Output) Indefinite data out tDW High impedance tDH Data in High impedance Indefinite data out Cautions 1. During address transition, at least one of pins /CE1, CE2, /WE should be inactivated. 2. Do not input data to the I/O pins while they are in the output state. Remarks 1. Write operation is done during the overlap time of a low level /CE1, /WE and a high level CE2. 2. If /CE1 changes to low level at the same time or after the change of /WE to low level, or if CE2 changes to high level at the same time or after the change of /WE to low level, the I/O pins will remain high impedance state. 3. When /WE is at low level, the I/O pins are always high impedance. When /WE is at high level, read operation is executed. Therefore /OE should be at high level to make the I/O pins high impedance. Data Sheet M11657EJAV0DS 15 µPD431000A Write Cycle Timing Chart 2 (/CE1 Controlled) tWC Address (Input) tAS tCW1 /CE1 (Input) tCW2 CE2 (Input) tAW tWP tWR /WE (Input) tDW High impedance Data in I/O (Input) tDH High impedance Cautions 1. During address transition, at least one of pins /CE1, CE2, /WE should be inactivated. 2. Do not input data to the I/O pins while they are in the output state. Remark 16 Write operation is done during the overlap time of a low level /CE1, /WE and a high level CE2. Data Sheet M11657EJAV0DS µPD431000A Write Cycle Timing Chart 3 (CE2 Controlled) tWC Address (Input) tCW1 /CE1 (Input) tAS tCW2 CE2 (Input) tAW tWP tWR /WE (Input) tDW High impedance I/O (Input) Data in tDH High impedance Cautions 1. During address transition, at least one of pins /CE1, CE2, /WE should be inactivated. 2. Do not input data to the I/O pins while they are in the output state. Remark Write operation is done during the overlap time of a low level /CE1, /WE and a high level CE2. Data Sheet M11657EJAV0DS 17 µPD431000A Low VCC Data Retention Characteristics (TA = 0 to 70 °C) Parameter Symbol µPD431000A-xxL Test Condition µPD431000A-xxLL Unit µPD431000A-Axx µPD431000A-Bxx MIN. Data retention VCCDR1 Data retention VCCDR2 CE2 ≤ 0.2 V ICCDR1 VCC = 3.0 V, /CE1 ≥ VCC − 0.2 V, MIN. TYP. MAX. 2.0 5.5 2.0 5.5 2.0 5.5 2.0 5.5 V 1 50 Note1 1 50 Note1 0.5 10 Note2 0.5 10 Note2 µA CE2 ≥ VCC − 0.2 V supply current ICCDR2 Chip deselection MAX. CE2 ≥ VCC − 0.2 V supply voltage /CE1 ≥ VCC − 0.2 V, TYP. VCC = 3.0 V, CE2 ≤ 0.2 V tCDR 0 0 ns tR 5 5 ms to data retention mode Operation recovery time Notes 1. 15 µA (TA ≤ 40 °C) 2. 3 µA (TA ≤ 40 °C) 18 Data Sheet M11657EJAV0DS µPD431000A Data Retention Timing Chart (1) /CE1 Controlled tCDR Data retention mode tR VCC Note 4.5 V /CE1 VIH (MIN.) VCCDR (MIN.) /CE1 ≥ VCC – 0.2 V VIL (MAX.) GND Note A version : 3.0 V, B version : 2.7 V Remark On the data retention mode by controlling /CE1, the input level of CE2 must be CE2 ≥ VCC − 0.2 V or CE2 ≤ 0.2 V. The other pins (Address, I/O, /WE, /OE) can be in high impedance state. (2) CE2 Controlled tCDR Data retention mode tR VCC Note 4.5 V VIH (MIN.) VCCDR (MIN.) CE2 VIL (MAX.) CE2 ≤ 0.2 V GND Note A version : 3.0 V, B version : 2.7 V Remark On the data retention mode by controlling CE2, the other pins (/CE1, Address, I/O, /WE, /OE) can be in high impedance state. Data Sheet M11657EJAV0DS 19 µPD431000A Package Drawings 32-PIN PLASTIC DIP (15.24mm(600)) 32 17 1 16 A K J I P L F D C N M R M B H G NOTES 1. Each lead centerline is located within 0.25 mm of its true position (T.P.) at maximum material condition. 2. Item "K" to center of leads when formed parallel. ITEM MILLIMETERS A 40.64 MAX. B C 1.27 MAX. 2.54 (T.P.) D F 0.50±0.10 1.1 MIN. G H 3.2±0.3 0.51 MIN. I 4.31 MAX. J 5.08 MAX. K 15.24 (T.P.) L 13.2 M 0.25 +0.10 −0.05 N 0.25 P 0.9 MIN. R 0 - 15° P32C-100-600A-2 20 Data Sheet M11657EJAV0DS µPD431000A 32-PIN PLASTIC SOP (13.34 mm (525)) 32 17 detail of lead end P 1 16 A H F I G J S N B S C D M L K M E NOTE Each lead centerline is located within 0.12 mm of its true position (T.P.) at maximum material condition. ITEM A MILLIMETERS 20.61 MAX. B 0.78 MAX. C 1.27 (T.P.) D 0.40+0.10 −0.05 E F G H 0.15±0.05 2.95 MAX. 2.7 14.1±0.3 I 11.3 J 1.4±0.2 K 0.20 +0.10 −0.05 L M N P 0.8±0.2 0.12 0.10 3° +7° −3° P32GW-50-525A-1 Data Sheet M11657EJAV0DS 21 µPD431000A 32-PIN PLASTIC TSOP(I) (8x20) detail of lead end 1 32 F G R Q 16 L 17 S E P I J A S B C D K N M M S NOTES ITEM MILLIMETERS 1. Each lead centerline is located within 0.10 mm of its true position (T.P.) at maximum material condition. A 8.0±0.1 B 0.45 MAX. 2. "A" excludes mold flash. (Includes mold flash : 8.3 mm MAX.) C 0.5 (T.P.) D 0.22±0.05 E 0.1±0.05 F 1.2 MAX. G 0.97±0.08 I 18.4±0.1 J 0.8±0.2 K 0.145±0.05 L 0.5 M 0.10 N 0.10 P 20.0±0.2 Q 3°+5° −3° R S 0.25 0.60±0.15 S32GZ-50-KJH1-2 22 Data Sheet M11657EJAV0DS µPD431000A 32-PIN PLASTIC TSOP(I) (8x20) detail of lead end E 1 32 S L Q R 16 G 17 F D K N S M M C B S I J A P NOTES 1. Each lead centerline is located within 0.10 mm of its true position (T.P.) at maximum material condition. 2. "A" excludes mold flash. (Includes mold flash : 8.3 mm MAX.) ITEM MILLIMETERS A 8.0±0.1 B 0.45 MAX. C 0.5 (T.P.) D 0.22±0.05 E 0.1±0.05 F 1.2 MAX. G 0.97±0.08 I 18.4±0.1 J 0.8±0.2 K 0.145±0.05 L 0.5 M 0.10 N 0.10 P 20.0±0.2 Q 3° +5° −3° R S 0.25 0.60±0.15 S32GZ-50-KKH1-2 Data Sheet M11657EJAV0DS 23 µPD431000A 32-PIN PLASTIC TSOP(I) (8x13.4) detail of lead end 1 32 S T R L 16 17 U Q P I J A G S H K B C N S NOTES D M M ITEM MILLIMETERS 1. Each lead centerline is located within 0.08 mm of its true position (T.P.) at maximum material condition. A B 8.0±0.1 0.45 MAX. 2. "A" excludes mold flash. (Includes mold flash : 8.3 mm MAX.) C D 0.5 (T.P.) 0.22±0.05 G 1.0±0.05 H 12.4±0.2 I 11.8±0.1 J 0.8±0.2 K 0.145 +0.025 −0.015 L 0.5 M 0.08 N 0.08 P 13.4±0.2 Q 0.1±0.05 R 3° +5° −3° S 1.2 MAX. T 0.25 U 0.6±0.15 P32GU-50-9JH-2 24 Data Sheet M11657EJAV0DS µPD431000A Recommended Soldering Conditions The following conditions must be met when soldering conditions of the µPD431000A. For more details, refer to our document “SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL” (C10535E). Please consult with our sales offices in case other soldering process is used, or in case soldering is done under different conditions. Types of Surface Mount Device µPD431000AGW-xxL : 32-PIN PLASTIC SOP (13.34 mm (525)) µPD431000AGW-xxLL : 32-PIN PLASTIC SOP (13.34 mm (525)) µPD431000AGW-Axx : 32-PIN PLASTIC SOP (13.34 mm (525)) µPD431000AGW-Bxx : 32-PIN PLASTIC SOP (13.34 mm (525)) µPD431000AGZ-xxL-KJH : 32-PIN PLASTIC TSOP(I) (8x20) (Normal bent) µPD431000AGZ-xxLL-KJH : 32-PIN PLASTIC TSOP(I) (8x20) (Normal bent) µPD431000AGZ-xxLL-KKH : 32-PIN PLASTIC TSOP(I) (8x20) (Reverse bent) µPD431000AGZ-Bxx-KJH : 32-PIN PLASTIC TSOP(I) (8x20) (Normal bent) µPD431000AGZ-Bxx-KKH : 32-PIN PLASTIC TSOP(I) (8x20) (Reverse bent) µPD431000AGU-Bxx-9JH : 32-PIN PLASTIC TSOP(I) (8x13.4) (Normal bent) Please consult with our sales offices. Types of Through Hole Mount Device µPD431000ACZ-xxL: 32-PIN PLASTIC DIP (15.24 mm (600)) µPD431000ACZ-xxLL: 32-PIN PLASTIC DIP (15.24 mm (600)) Soldering process Soldering conditions Wave soldering (Only to leads) Solder temperature: 260 °C or below, Flow time: 10 seconds or below Partial heating method Pin temperature : 300 °C or below, Time: 3 seconds or below (Per one lead) Caution Do not jet molten solder on the surface of package. Data Sheet M11657EJAV0DS 25 µPD431000A [MEMO] 26 Data Sheet M11657EJAV0DS µPD431000A NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. Data Sheet M11657EJAV0DS 27 µPD431000A • The information in this document is current as of April, 2001. The information is subject to change without notice. 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