ETC VSLI2002_1MB_MRAM

To be published at VLSI Symposium 2002
A low power 1Mbit MRAM based on 1T1MTJ bit cell integrated with Copper
Interconnects
M. Durlam, P. Naji, A. Omair, M. DeHerrera, J. Calder, J. M. Slaughter, B. Engel, N. Rizzo, G.
Grynkewich, B. Butcher, C. Tracy, K. Smith, K. Kyler, J. Ren, J. Molla, B. Feil, R. Williams, S. Tehrani
Motorola Labs and Motorola Semiconductor Products Sector
7700 S. River Parkway
Tempe, AZ 85284
Abstract
Introduction
Magnetoresistive
Random
Access
Memory
(MRAM) is a high-speed, low-voltage, high-density,
nonvolatile memory with unlimited read/write endurance. A
512b and 256kb MRAM based on 1T1MTJ 1,2 and a 1kb
MRAM based on 2T2MTJ3 have been previously reported in
the literature. This paper reports the first demonstration of a
1T1MTJ 1Mb MRAM.
The magnetic tunnel junction (MTJ) material stack
(Fig. 1) is composed of two magnetic layers separated by a
thin AlOx dielectric barrier. A layer of antiferromagnetic
material with strong exchange coupling, such as FeMn or
IrMn, is in contact with the bottom magnetic layer, pinning it
in one direction. This layer is separated from the next
magnetic layer by a thin layer of Ru, creating a synthetic
antiferromagnet (SAF). The strong exchange between the
magnetic layers in the SAF structure fixes the magnetic
polarization of the fixed layer in one direction and prevents
the fixed layer from switching during write operations.
The polarization of the top magnetic layer is free to
rotate and is thus called the free layer. The resistance of the
memory bit is either low or high dependent on the relative
polarization, parallel or anti-parallel, of the free layer with
respect to the fixed layer4. The switching of the free layer
between the two polarization states is hysteretic, giving the
device two stable memory states. Topological roughness of
the magnetic layers causes a weak ferromagnetic coupling
shifting the hysteresis loop. The SAF structure provides a
mechanism for adjusting the magnetostatic charge of the
bottom magnetic electrode, enabling the hysteresis loop to be
centered by adjusting the balance of the SAF layers,
canceling out the topological coupling.
Top electrode
Free Layer
AlOx
Fixed Layer
Ru
Pinned
AF pinning layer
}
SAF
Base electrode
Fig. 1. MTJ Material Stack with Synthetic Antiferromagnet (SAF)
4.8
4.6
RA (kΩ-µm2 )
A low power 1Mb Magnetoresistive Random Access
Memory (MRAM) based on a 1-Transistor and 1-Magnetic
Tunnel Junction (1T1MTJ) bit cell is demonstrated. This is
the largest MRAM memory demonstration to date. In this
circuit, MTJ elements are integrated with CMOS using
copper interconnect technology. The copper interconnects
are cladded with a high permeability layer which is used to
focus magnetic flux generated by current flowing through the
lines toward the MTJ devices and reduce the power needed
for programming the bits. The 25mm2 1Mb MRAM circuit
operates with address access times of less than 50ns,
consuming 24mW at 3.0V and 20MHz. The circuit is
fabricated in a 0.6µm CMOS process utilizing five layers of
metal and two layers of poly.
4.4
4.2
4
44%
change
3.8
3.6
3.4
3.2
3
-75
-50
-25
0
25
50
Easy Axis Field (Oe)
Fig. 2. Hysteresis loop of 0.6x1.2µm2 device at low bias.
75
To be published at VLSI Symposium 2002
A. Cell Architecture
The cell architecture is based on a minimum-sized
active transistor as the isolation device in conjunction with a
magnetic tunnel junction element. In the 1T1MTJ MRAM,
the MTJ element has one electrode connected to the drain of a
pass transistor for isolation and the other electrode connected
to the bit line. Neighboring cells share the pass transistor
source and isolation region to minimize cell area. The MTJ
element is integrated into a five-layer metal, 0.6µm CMOS
process with 1.8µm metal pitches resulting in a cell size of
7.2µm2 or 9F2, where F is one-half the metal pitch.
1-MTJ/1-Transistor Memory Cell
Program Mode
Bit Line
50
40
H (Oe)
1T1MTJ Memory Cell
shows measured field response from cladded and uncladded
lines, demonstrating a factor of 2 improvement in field
generated for a given current, but also showing a slight
remanence characteristic. An additional benefit of the flux
concentrators is that they focus the generated magnetic field
over the target cell, reducing cross talk during programming.
The conductors are arranged in a cross-point halfselect architecture where the intersection of two currentcarrying lines generates a field sufficient to switch the bit at
the intersection, but leave other bits on either line
undisturbed. One line provides the field that affects the
“easy” magnetic axis of the bit, while another line provides
the field that affects the “hard” magnetic axis of the bit.
i
Magnetic
Field
D
ig
it
Flux concentrating
cladding layer
Inlaid Copper
interconnects
20
0
Fixed Layer
ne
With cladding
10
Free Layer
Tunnel Barrier
Li
30
i
Without cladding
0
0.1 0.2 0.3 0.4
Distance above line (µm)
Fig. 4. Calculated field generated at a distance from a 0.4x0.9µm2
line with and without cladding using 4mA current.
Isolation
Transistor
“OFF”
2
Cladded line
Fig. 3. Magnetic Tunnel Junction device cell with 1-MTJ/1Transistor showing Write Mode operation with flux
concentrating cladding layers.
B. Programming bits
The MRAM bit cell is programmed by a magnetic
field, which is generated by current flowing through two
conductors while the transistor is in the cutoff state (shown in
Fig. 3). The direction of polarization of free layer is
controlled via the direction of current flow through the
bitlines. Each conductor supplies half the field required to
switch the bit.
These conductors are inlaid copper
interconnects with flux concentrating cladding to focus the
generated magnetic field. The flux-concentrating layer is
composed of a thin layer of soft ferromagnetic material that is
integrated into the inlaid copper interconnect process. The
flux concentrators reduce the required current by
approximately a factor of 2 as compared to lines without
cladding (see Fig. 4). The requirements for the flux
concentrating cladding are that the remanence and coercivity
are minimized and the magnetic response is linear. Fig. 5
1
0
-4
Uncladded digit line
-2
0
2
4
Current in Line (mA)
Fig. 5. Normalized measured field at 0.3µm above 0.9µm wide,
0.4µm thick cladded and uncladded lines.
C. Reading bits
Achieving a high percentage change in resistance
between the high and low resistance states (MR=(Rmax-
To be published at VLSI Symposium 2002
Rmin)/Rmin) is critical for high-speed read circuitry. We
have been able to achieve MR signals over 45% at low bias
and over 30% at operating voltage with wafer uniformity
better than 1%. Another key element in the memory circuitry
is the reference cell. In our 1Mb architecture, we have
utilized a new concept for the reference cell. The reference
cell in the 1Mb circuit generates a signal that is mid-way
between the Rmax and Rmin resistance states of the MTJ (see
Fig. 6). The reference generator block is composed of a
column of mid-point reference cells located in the middle of
each 32kb block as seen in Fig. 7. Each mid-point reference
generator is composed of 4 MTJ devices in a series-parallel
combination. A MTJ device pair connected in series is
additionally connected in parallel with another series device
pair. The series device pairs are programmed such that one
device in the pair is anti-parallel and the other device is
parallel resulting in a resistive high and low state for the two
MTJ cells.
The resulting series/parallel resistance
combination is a resistance that is ½(Rmax + Rmin) or midway between Rmax and Rmin. The mid-point generator
improves matching between the target cells and the reference
due to the close proximity and the additional averaging of the
4MTJ reference cell. The averaging and close proximity
enables the mid-point generator to closely track the active
elements and to account for variations in processing.
14
Rmax
13
RA (kΩ-µm2 )
12
Rmid
11
10
Rmin
9
8
Midpt gen
Calc Midpt
7
6
-0.5 -0.4 -0.3 -0.2 -0.1
0
0.1
0.2
0.3
0.4
0.5
Bias Voltage (V)
Fig. 6. Measured minimum, maximum and middle resistance
and calculated middle resistance curves vs. bias for a
midpoint generator reference cell.
MRAM 32Kb Memory Block with Mid-Point Reference Generator
Midpoint Reference
Generator
½ Memory block - 1024X16
Rmax
Rmax
BL0
BL1
BL14
BL15
Rmin
½ Memory block - 1024X16
Rmin
(Rmax+Rmin)//(Rmax+Rmin)=
1/2*(Rmax+Rmin)
BL16
BL17
BL30
BL31
Current Conveyors
and Differential Amp
Fig. 7. MRAM memory core block with mid-point reference generator circuitry.
1Mb MRAM
The 1Mb MRAM circuit (shown in Fig. 8) is a
demonstration vehicle for the development of the MRAM
technology. The circuit has onboard bias, reference, and
clock generation subcircuits, so no external reference
voltage, bias voltage, or clock signal is required. There are
three modes available: active, sleep, and standby. Active
mode has full power consumption and the circuit is ready
for random access. In sleep mode, random access and
other functions are disabled, but power consumption is
reduced. There is no power-up procedure required from
sleep mode to active mode. There is almost no power
consumption when the chip is in standby mode, but a
Fig. 8.
Microphotograph showing Motorola’s 1Mb
MRAM circuit integrated with copper interconnects.
Current/Source or Sink
Current/Source or Sink
16
16
Row
Decode
Current Switch
Current Switch
BL 511-0
BL 511-0
GL 0
Ground Switch
MRAM Array
512 columns
1024 Rows
16 Ref.
Columns
GL 0
0
MRAM Array
512 columns
1024 Rows
16 Ref.
Columns
DL
Row
Select
DL
1024
GL 512
1024
GL 512
Column Select
Column Select
Current
Source A
16
16
Current/Source or Sink
Current/Source or Sink
16
16
Read Circuit
dq0
Ground Switch
Current Sink B
0
Current Sink B
To be published at VLSI Symposium 2002
power-up sequence is required to put the chip into active
mode.
The 1Mb MRAM circuit is arranged in two 524kb
banks (see Fig. 9). Each bank contains sixteen 32Kb
blocks, with each block containing a mid-point reference
generator column (see Fig. 7). Within each block the midpoint generator services sixteen bits to the left and sixteen
bits to the right of its column. The mid-point reference
generators are set to their operational states during the
initial power up sequence. The information in a target bit
is read by comparing the target bit resistance with the
associated mid-point reference generator.
The read
operation is as follows: a memory cell is selected by
driving a wordline/digitline to vdd, selecting a column, and
turning on all ground switches. A current conveyor is
shared by every 32 bitlines and every reference bitline has
its own current conveyor. Once the current conveyors are
turned on, they clamp the target bitlines and reference
bitlines to their respective voltages, take the resulting target
and reference bitline currents and convert them to a voltage
signal with substantial boost. The target and reference
current conveyors form a differential pair and their outputs
are fed into a two stage differential comparator followed by
a regenerator, which again boosts the signal. The read
circuitry has been optimized to achieve high bandwidth,
maintain offset insensitivity, and consume minimal silicon
area. Read access times of 50ns have been measured at 3V
operation.
Read Circuit
dq15
dq15
dq0
Fig. 9. Block diagram of 1Mb MRAM.
Summary
A 1Mbit MRAM has been demonstrated in a
0.6µm CMOS technology. This 1Mbit demonstration is
the largest MRAM circuit to date and the first using copper
interconnects and flux concentrating layers for a low power
operation. This demonstration was done on 200mm
substrates. A new reference cell for MRAM has been
demonstrated with excellent results.
References
[1] M. Durlam, P. Naji, M. DeHerrera, S. Tehrani, G.
Kerszykowski, and K. Kyler, “Nonvolatile RAM based on Magnetic
Tunnel Junction Elements”, ISSCC Digest of Technical Papers, PP.
130-131, Feb. 2000.
[2] P. Naji, M. Durlam, S. Tehrani, J. Calder, M. DeHerrera, “A
256kb 3.0V 1T1MTJ Nonvolatile Magnetoresistive RAM”, ISSCC
Digest of Technical Papers, PP. 122-123, Feb. 2001.
[3] R. Scheuerlein, W. Gallagher, S. Parkin, A. Lee, S. Ray, R.
Robertazzi, and W. Reohr, “A 10ns Read and Write Non-Volatile
Memory Array Using a Magnetic Tunnel Junction and FET Switch
in each Cell”, ISSCC Digest of Technical Papers, PP. 128-129, Feb.
2000.
[4] S. Tehrani, B. Engel, J. M. Slaughter, E. Chen, M. DeHerrera,
M. Durlam, P. Naji, R. Whig, J. Janesky, and J. Calder, “Recent
Developments in Magnetic Tunnel Junction MRAM”, IEEE Trans.
on Magnetics, Sept. 2000.