Revised August 2000 100353 Low Power 8-Bit Register General Description Features The 100353 contains eight D-type edge triggered, master/ slave flip-flops with individual inputs (Dn), true outputs (Qn), a clock input (CP), and a common clock enable pin (CEN). Data enters the master when CP is LOW and transfers to the slave when CP goes HIGH. When the CEN input goes HIGH it overrides all other inputs, disables the clock, and the Q outputs maintain the last state. ■ Low power operation ■ 2000V ESD protection ■ Voltage compensated operating range = −4.2V to −5.7V ■ Available to industrial grade temperature range The 100353 output drivers are designed to drive 50Ω termination to −2.0V. All inputs have 50 kΩ pull-down resistors. Ordering Code: Order Number Package Number 100353PC N24E Package Description 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide 100353QC V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square 100353QI V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square Industrial Temperature Range (−40°C to +85°C) Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbol Connection Diagrams 24-Pin DIP Pin Descriptions Pin Names Description D0–D7 Data Inputs CEN Clock Enable Input CP Clock Input (Active Rising Edge) Q0–Q7 Data Outputs NC No Connect © 2000 Fairchild Semiconductor Corporation 28-Pin PLCC DS009882 www.fairchildsemi.com 100353 Low Power 8-Bit Register July 1988 100353 Truth Table Inputs Dn CEN L L Outputs CP Qn L H L X X L NC X X H NC X H X NC H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care NC = No Change = LOW-to-HIGH Transition Logic Diagram www.fairchildsemi.com 2 H Recommended Operating Conditions −65°C to +150°C Storage Temperature (TSTG) +150°C Maximum Junction Temperature (TJ) Case Temperature (TC) −7.0V to +0.5V VEE Pin Potential to Ground Pin Output Current (DC Output HIGH) −50 mA ESD (Note 2) ≥2000V 0°C to +85°C Commercial VEE to + 0.5V Input Voltage (DC) 100353 Absolute Maximum Ratings(Note 1) −40°C to +85°C Industrial −5.7V to −4.2V Supply Voltage (VEE) Note 1: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum rating. The “Recommended Operating Conditions” table will define the conditions for actual device operation. Note 2: ESD testing conforms to MIL-STD-883, Method 3015. Commercial Version DC Electrical Characteristics (Note 3) VEE = −4.2V to −5.7V, VCC = VCCA = GND, TC = 0°C to +85°C Min Typ Max Units VOH Symbol Output HIGH Voltage Parameter −1025 −955 −870 mV VIN = VIH (Max) Conditions Loading with VOL Output LOW Voltage −1830 −1705 −1620 mV or VIL (Min) 50Ω to −2.0V VOHC Output HIGH Voltage −1035 VOLC Output LOW Voltage VIH Input HIGH Voltage VIL Input LOW Voltage IIL Input LOW Current 0.50 IIH Input HIGH Current IEE Power Supply Current mV VIN = VIH (Min) Loading with −1610 mV or VIL (Max) 50Ω to −2.0V −1165 −870 mV Guaranteed HIGH Signal for all Inputs −1830 −1475 mV Guaranteed LOW Signal for all Inputs µA VIN = VIL (Min) µA 240 VIN = VIH (Max) Inputs OPEN −119 −61 −122 −61 mA VEE = −4.2V to −4.8V VEE = −4.2V to −5.7V Note 3: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee operation under “worst case” conditions. DIP AC Electrical Characteristics VEE = −4.2V to −5.7V, VCC = VCCA = GND Symbol Parameter fMAX Toggle Frequency tPLH Propagation Delay tPHL CP to Output tTLH Transition Time tTHL 20% to 80%, 80% to 20% tS Setup Time tH TC = +25°C Max Min 425 Max 425 TC = +85°C Min Max 425 Units MHz Conditions Figures 1, 2 Figures 1, 2 1.40 3.00 1.40 3.00 1.50 3.10 ns 0.45 2.00 0.45 2.00 0.45 2.00 ns Figures 1, 2 ns Figures 1, 3 (Note 4) Dn 1.10 1.10 CEN (Disable Time) 0.40 0.40 0.40 CEN (Release Time) 1.10 1.10 1.10 0.10 0.10 0.10 ns Figures 1, 4 2.00 2.00 2.00 ns Figures 1, 2 Hold Time Dn tPW(H) TC = 0°C Min Pulse Width HIGH CP 1.10 Note 4: The propagation delay specified is for single output switching. Delays may vary up to 300 ps with multiple outputs switching. 3 www.fairchildsemi.com 100353 PLCC AC Electrical Characteristics VEE = −4.2V to −5.7V, VCC = VCCA = GND Symbol TC = 0°C Parameter Min fMAX Toggle Frequency tPLH Propagation Delay tPHL CP to Output tTLH Transition Time tTHL 20% to 80%, 80% to 20% tS Setup Time TC = +25°C Max Min 425 Max 425 TC = +85°C Min 425 1.50 2.90 ns 0.45 1.90 0.45 1.90 0.45 1.90 ns Figures 1, 2 ns Figures 1, 3 Figures 1, 4 1.00 1.00 0.30 0.30 CEN (Release Time) 1.00 1.00 1.00 tOSHL Maximum Skew Common Edge Dn CP Output-to-Output Variation Figures 1, 2 2.80 1.00 Pulse Width HIGH Figures 1, 2 1.40 0.30 Hold Time MHz 2.80 Dn tPW(H) Conditions 1.40 CEN (Disable Time) tH Units Max 0 0 0 ns 2.00 2.00 2.00 ns (Note 5) Figures 1, 2 PLCC Only 200 200 200 ps 200 200 200 ps 260 260 260 ps 280 280 280 ps (Note 6) Data to Output Path tOSLH Maximum Skew Common Edge Output-to-Output Variation PLCC Only (Note 6) Data to Output Path tOST Maximum Skew Opposite Edge Output-to-Output Variation PLCC Only (Note 6) Data to Output Path tPS Maximum Skew Pin (Signal) Transition Variation PLCC Only (Note 6) Data to Output Path Note 5: The propagation delay specified is for single output switching. Delays may vary up to 300 ps with multiple outputs switching. Note 6: Output-to-Output Skew is defined as the absolute value of the difference between the actual propagation delay for any outputs within the same packaged device. The specifications apply to any outputs switching in the same direction either HIGH-to-LOW (tOSHL), or LOW-to-HIGH (tOSLH), or in opposite directions both HL and LH (tOST). Parameters tOST and tPS guaranteed by design. www.fairchildsemi.com 4 100353 Industrial Version PLCC DC Electrical Characteristics VEE = −4.2V to −5.7V, VCC = VCCA = GND, TC = −40°C to +85°C (Note 7) TC = 0°C to +85°C TC = −40°C Symbol Parameter Min Max Min Max Units Conditions VOH Output HIGH Voltage −1085 −870 −1025 −870 mV VIN = VIH (Max) Loading with VOL Output LOW Voltage −1830 −1575 −1830 −1620 mV or VIL (Min) 50Ω to −2.0V −1095 −1035 VOHC Output HIGH Voltage VOLC Output LOW Voltage VIH Input HIGH Voltage −1170 −870 VIL Input LOW Voltage −1830 −1480 IIL Input LOW Current 0.50 IIH Input HIGH Current IEE Power Supply Current mV VIN = VIH (Min) Loading with −1610 mV or VIL (Max) 50Ω to −2.0V −1165 −870 mV Guaranteed HIGH Signal for all Inputs −1830 −1475 mV Guaranteed LOW Signal for all Inputs µA VIN = VIL (Min) −1565 0.50 240 240 µA VIN = VIH (Max) Inputs OPEN −119 −61 −119 −61 −122 −61 −122 −61 mA VEE = −4.2V to −4.8V VEE = −4.2V to −5.7V Note 7: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee operation under “worst case” conditions. PLCC AC Electrical Characteristics VEE = −4.2V to −5.7V, VCC = VCCA = GND Symbol Parameter fMAX Toggle Frequency tPLH Propagation Delay tPHL CP to Output tTLH Transition Time tTHL 20% to 80%, 80% to 20% tS Setup Time TC = −40°C Min TC = +25°C Max Min 425 Max 425 TC = +85°C Min 425 2.80 1.50 2.90 ns 0.40 2.50 0.45 1.90 0.45 1.90 ns Figures 1, 2 ns Figures 1, 3 1.00 0.90 0.30 0.30 CEN (Release Time) 1.40 1.00 1.00 Hold Time Dn CP Figures 1, 2 Figures 1, 2 1.40 0.60 Pulse Width HIGH MHz Conditions 2.80 CEN (Disable Time) tPW(H) Units 1.40 Dn tH Max (Note 8) 1.00 0.30 0 0 ns Figures 1, 4 2.00 2.00 2.00 ns Figures 1, 2 Note 8: The propagation delay specified is for single output switching. Delays may vary up to 300 ps with multiple outputs switching. 5 www.fairchildsemi.com 100353 Test Circuitry Note: • VCC, VCCA = +2V, VEE = −2.5V • L1 and L2 = equal length 50Ω impedance lines • RT = 50Ω terminator internal to scope • Decoupling 0.1 µF from GND to VCC and VEE • All unused outputs are loaded with 50Ω to GND • CL = Fixture and stray capacitance ≤ 3 pF FIGURE 1. AC, Toggle Frequency Test Circuit Switching Waveforms FIGURE 2. Propagation Delay (Clock) and Transition Times FIGURE 3. Setup and Pulse Width Times Note: tS is the minimum time before the transition of the clock that information must be present at the data input. tH is the minimum time after the transition of the clock that information must remain unchanged at the data input. FIGURE 4. Data Setup and Hold Time www.fairchildsemi.com 6 100353 Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide Package Number N24E 7 www.fairchildsemi.com 100353 Low Power 8-Bit Register Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square Package Number V28A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com www.fairchildsemi.com 8