Revised August 2000 100343 Low Power 8-Bit Latch General Description Features The 100343 contains eight D-type latches, individual inputs, (Dn), outputs (Qn), a common enable pin (E), and a latch enable pin (LE). A Q output follows its D input when both E and LE are LOW. When either E or LE (or both) are HIGH, a latch stores the last valid data present on its D input prior to E or LE going HIGH. ■ Low power operation ■ 2000V ESD protection ■ Voltage compensated operating range = −4.2V to −5.7V ■ Available to industrial grade temperature range The 100343 outputs are designed to drive a 50Ω termination resistor to −2.0V. All inputs have 50 kΩ pull-down resistors. Ordering Code: Order Number Package Number 100343PC N24E Package Description 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide 100343QC V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square 100343QI V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square Industrial Temperature Range (−40°C to +85°C) Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbol Connection Diagrams 24-Pin DIP 28-Pin PLCC Pin Descriptions Pin Names Description D0–D7 Data Inputs E Enable Input LE Latch Enable Input Q0–Q7 Data Inputs NC No Connect © 2000 Fairchild Semiconductor Corporation DS010250 www.fairchildsemi.com 100343 Low Power 8-Bit Latch October 1989 100343 Truth Table Inputs Outputs Dn E LE L L L L H L L H X H X Latched (Note 1) X X H Latched (Note 1) H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care Note 1: Retains data present before either LE or E went HIGH Logic Diagram www.fairchildsemi.com 2 Qn Recommended Operating Conditions −65°C to +150°C Storage Temperature (TSTG) +150°C Maximum Junction Temperature (TJ) Case Temperature (TC) −7.0V to +0.5V VEE Pin Potential to Ground Pin Output Current (DC Output HIGH) −50 mA ESD (Note 3) ≥2000V 0°C to +85°C Commercial VEE to +0.5V Input Voltage (DC) 100343 Absolute Maximum Ratings(Note 2) −40°C to +85°C Industrial −5.7V to −4.2V Supply Voltage (VEE) Note 2: The “Absolute Maximum Ratings” re those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the absolute maximum rating. The “Recommended Operating Conditions” table will define the conditions for actual device operation. Note 3: ESD testing conforms to MIL-STD-883, Method 3015. Commercial Version DC Electrical Characteristics (Note 4) VEE = −4.2V to −5.7V, VCC = VCCA = GND, TC = 0°C to +85°C Min Typ Max Units VOH Symbol Output HIGH Voltage Parameter −1025 −955 −870 mV VIN = VIH (Max) Conditions VOL Output LOW Voltage −1830 −1705 −1620 mV or VIL (Min) 50Ω to −2.0V VOHC Output HIGH Voltage −1035 mV VIN = VIH (Min) Loading with 50Ω to −2.0V Loading with VOLC Output LOW Voltage −1610 mV or VIL (Max) VIH Input HIGH Voltage −1165 −870 mV Guaranteed HIGH Signal for All Inputs −1475 mV Guaranteed LOW Signal for All Inputs µA VIN = VIL (Min) VIL Input LOW Voltage −1830 IIL Input LOW Current 0.50 IIH Input HIGH Current IEE Power Supply Current µA 240 VIN = VIH (Max) Inputs Open −95 −55 −97 −55 VEE = −4.2V to −4.8V mA VEE = −4.2V to −5.7V Note 4: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee operation under “worst case” conditions. AC Electrical Characteristics VEE = −4.2V to −5.7V, VCC = VCCA = GND Symbol TC = 0°C Parameter tPLH Propagation Delay tPHL Dn to Output tPLH Propagation Delay tPHL LE, E to Output tTLH Transition Time tTHL 20% to 80%, 80% to 20% TC = +25°C TC = +85°C Units Conditions Min Max Min Max Min Max 0.80 2.00 0.80 2.00 0.80 2.20 ns 1.40 2.90 1.40 2.90 1.60 3.10 ns 0.45 2.00 0.45 2.00 0.45 2.00 ns Figures 1, 3 Figures 1, 4 Figures 1, 2, 3 (Note 5) Figures 1, 2, 3 (Note 5) tS Setup Time D0–D7 1.0 1.0 1.1 ns tH Hold Time D0–D7 0.1 0.1 0.1 ns Figures 1, 4 tPW(H) Pulse Width HIGH LE, E 2.00 2.00 2.00 ns Figures 1, 4 Note 5: The propagation delay specified is for single output switching. Delays may vary up to 300 ps with multiple outputs switching. 3 www.fairchildsemi.com 100343 Commercial Version (Continued) PLCC AC Electrical Characteristics VEE = −4.2V to −5.7V, VCC = VCCA = GND Symbol TC = 0°C Parameter TC = +25°C TC = +85°C Units Conditions Min Max Min Max Min Max 0.80 1.80 0.80 1.80 0.80 2.00 ns 1.40 2.70 1.40 2.70 1.60 2.90 ns 0.45 1.90 0.45 1.90 0.45 1.90 ns Figures 1, 3 Figures 1, 4 tPLH Propagation Delay tPHL Dn to Output tPLH Propagation Delay tPHL LE, E to Output tTLH Transition Time tTHL 20% to 80%, 80% to 20% tS Setup Time D0–D7 0.90 0.90 1.00 ns tH Hold Time D0–D7 0.0 0.0 0.0 ns Figures 1, 4 tPW(H) Pulse Width HIGH LE, E 2.00 2.00 2.00 ns Figures 1, 4 tOSHL Maximum Skew Common Edge Output-to-Output Variation Figures 1, 2, 3 (Note 6) Figures 1, 2, 3 (Note 6) PLCC Only 340 340 340 ps 440 440 440 ps 480 480 480 ps 300 300 300 ps (Note 7) Data to Output Path tOSLH Maximum Skew Common Edge Output-to-Output Variation PLCC Only (Note 7) Data to Output Path tOST Maximum Skew Opposite Edge Output-to-Output Variation PLCC Only (Note 7) Data to Output Path tPS Maximum Skew Pin (Signal) Transition Variation PLCC Only (Note 7) Data to Output Path Note 6: The propagation delay specified is for single output switching. Delays may vary up to 300 ps with multiple outputs switching. Note 7: Output-to-Output Skew is defined as the absolute value of the difference between the actual propagation delay for any outputs within the same packaged device. The specifications apply to any outputs switching in the same direction either HIGH-to-LOW (tOSHL), or LOW-to-HIGH (tOSLH), or in opposite directions both HL and LH (tOST). Parameters tOST and tPS guaranteed by design. www.fairchildsemi.com 4 100343 Industrial Version PLCC DC Electrical Characteristics (Note 8) VEE = −4.2V to −5.7V, VCC = VCCA = GND, TC = −40°C to +85°C TC = −40°C TC = 0°C to +85°C Symbol Parameter Min Max Min Max Units Conditions VOH Output HIGH Voltage −1085 −870 −1025 −870 mV VIN = VIH (Max) Loading with VOL Output LOW Voltage −1830 −1575 −1830 −1620 mV or VIL (Min) 50Ω to −2.0V VOHC Output HIGH Voltage −1095 mV VIN = VIH (Min) Loading with VOLC Output LOW Voltage −1610 mV or VIL (Max) 50Ω to −2.0V VIH Input HIGH Voltage −1170 −870 −1165 −870 mV Guaranteed HIGH Signal VIL Input LOW Voltage −1830 −1480 −1830 −1475 mV Guaranteed LOW Signal IIL Input LOW Current 0.50 IIH Input HIGH Current IEE Power Supply Current −1035 −1565 for All Inputs for All Inputs µA 0.50 240 240 µA VIN = VIL (Min) VIN = VIH (Max) Inputs Open −95 −50 −95 −55 −97 −50 −97 −55 mA VEE = −4.2V to −4.8V VEE = −4.2V to −5.7V Note 8: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee operation under “worst case” conditions. PLCC AC Electrical Characteristics VEE = −4.2V to −5.7V, VCC = VCCA = GND Symbol TC = −40°C Parameter TC = +25°C TC = +85°C Min Max Min Max Min Max 0.80 1.80 0.80 1.80 0.80 2.00 tPLH Propagation Delay tPHL Dn to Output tPLH Propagation Delay tPHL LE, E to Output tTLH Transition Time tTHL 20% to 80%, 80% to 20% ts Setup Time D0–D7 0.60 0.90 tH Hold Time D0–D7 0.8 0.0 tpw(H) Pulse Width HIGH LE, E 2.40 2.00 Units ns Conditions Figures 1, 2, 3 (Note 9) Figures 1, 2, 3 1.40 2.70 1.40 2.70 1.60 2.90 ns 0.40 2.50 0.45 1.90 0.45 1.90 ns Figures 1, 3 1.00 ns Figures 1, 4 0.0 ns Figures 1, 4 2.00 ns Figures 1, 4 (Note 9) Note 9: The propagation delay specified is for single output switching. Delays may vary up to 300 ps with multiple outputs switching. 5 www.fairchildsemi.com 100343 Test Circuitry Note: • VCC, VCCA = +2V, VEE = −2.5V • L1 and L2 = equal length 50Ω impedance lines • RT = 50Ω terminator internal to scope • Decoupling 0.1 µF from GND to VCC and VEE • All unused outputs are loaded with 50Ω to GND • CL = Fixture and stray capacitance ≤ 3 pF FIGURE 1. AC Test Circuit Switching Waveforms FIGURE 2. Propagation Delays FIGURE 3. Propagation and Transition Times FIGURE 4. Setup, Hold and Pulse Width Times www.fairchildsemi.com 6 100343 Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide Package Number N24E 7 www.fairchildsemi.com 100343 Low Power 8-Bit Latch Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square Package Number V28A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com www.fairchildsemi.com 8