74LVX74 LOW VOLTAGE DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: fMAX = 145 MHz (TYP.) at VCC = 3.3V INPUT VOLTAGE LEVEL: VIL = 0.8V, VIH = 2V at VCC = 3V LOW POWER DISSIPATION: ICC = 2 µA (MAX.) at TA = 25 oC LOW NOISE: VOLP = 0.3 V (TYP.) at VCC = 3.3V SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 4 mA (MIN) BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 3.6V (1.2V Data Retention) PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 74 IMPROVED LATCH-UP IMMUNITY POWER DOWN PROTECTION ON INPUTS DESCRIPTION The 74LVX74 is a low voltage CMOS DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low power and low noise 3.3V applications. SOP TSSOP ORDER CODES PACKAGE T UBE T& R SOP 74LVX74M 74LVX74MTR TSSOP 74LVX74TTR A signal on the D INPUT is transferred to the Q OUTPUT during the positive going transition of the clock pulse. CLEAR and PRESET are independent of the clock and accomplished by a low setting on the appropriate input. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. PIN CONNECTION AND IEC LOGIC SYMBOLS February 2000 1/11 74LVX74 INPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No SYMBOL 1, 13 1CLR, 2CLR Asyncronous Reset Direct Inputs NAME AND FUNCT ION 2, 12 1D, 2D Data Inputs 3, 11 1CK, 2CK Clock Inputs (LOW-to-HIGH, EdgeTriggered) 4, 10 1PR, 2PR Asyncronous Set - Direct Inputs 5, 9 1Q, 2Q True Flip-Flop Outputs 6, 8 1Q, 2Q Complement Flip-Flop Outputs 7 GND Ground (0V) 14 VCC Positive Supply Voltage TRUTH TABLE INPUTS OUT PUT S CLR PR D CK L H X H L X Q X L H CLEAR X H L PRESET X H H L H L L X H H L H H H H L H H X Qn Qn X:Don’t Care LOGIC DIAGRAM Thislogic diagram has notbe used to esimate propagation delays 2/11 F UNCTION Q NO CHANGE 74LVX74 ABSOLUTE MAXIMUM RATINGS Symbol VCC Parameter Supply Voltage VI DC Input Voltage VO DC Output Voltage Value Unit -0.5 to +7.0 V -0.5 to 7.0 V -0.5 to VCC + 0.5 V IIK DC Input Diode Current -20 mA IOK DC Output Diode Current ± 20 mA IO DC Output Current ± 25 mA ± 50 mA ICC or IGND DC VCC or Ground Current Tstg Storage Temperature TL Lead Temperature (10 sec) -65 to +150 o 300 o C C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is not implied. RECOMMENDED OPERATING CONDITIONS Symbol VCC Parameter Supply Voltage (note 1) Valu e Unit 2 to 3.6 V V VI Input Voltage 0 to 5.5 VO Output Voltage 0 to VCC Top dt/dv Operating Temperature: Input Rise and Fall Time (VCC = 3V) (note 2) -40 to +85 0 to 100 V o C ns/V 1) Truth Table guaranteed: 1.2V to 3.6V 2) VIN from 0.8V to 2V 3/11 74LVX74 DC SPECIFICATIONS Symb ol VIH VIL VOH VOL II ICC Parameter High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage Test Co nditions Valu e T A = 25 oC Un it -40 to 85 o C V CC (V) Min. 2.0 1.5 1.5 3.0 2.0 2.0 3.6 2.4 T yp. Max. Min. Max. V 2.4 2.0 0.5 0.5 3.0 0.8 0.8 3.6 0.8 0.8 2.0 I O=-50 µA 1.9 2.0 1.9 3.0 IO=-50 µA 2.9 3.0 2.9 3.0 IO=-4 mA 2.58 2.0 I O =50 µA 0.0 0.1 0.1 3.0 IO=50 µA 0.0 0.1 0.1 V V 2.48 V 3.0 IO=4 mA 0.36 0.44 Input Leakage Current 3.6 VI = 5V or GND ±0.1 ±1 µA Quiescent Supply Current 3.6 VI = VCC or GND 2 20 µA DYNAMIC SWITCHING CHARACTERISTICS Symb ol Parameter Test Co nditions Dynamic Low Voltage Quiet Output (note 1, 2) 3.3 VIHD Dynamic High Voltage Input (note 1, 3) 3.3 VILD Dynamic Low Voltage Input (note 1, 3) 3.3 VOLP VOLV Valu e T A = 25 oC V CC (V) Min. -0.5 T yp. Max. 0.3 0.5 Min. Max. -0.3 2 C L = 50 pF Un it -40 to 85 o C V 0.8 1) Worst case package 2) Max number of outputs defined as (n). Data inputs are driven 0V to 3.3V, (n -1) outputs switching and one output at GND 3) max number of data inputs (n) switching. (n-1) switching 0V to3.3V. Inputs under test switching: 3.3V to threshold (VILD), 0V to threshold (VIHD). f=1MHz 4/11 74LVX74 AC ELECTRICAL CHARACTERISTICS (Input t r = tf =3 ns) Symb ol Parameter T est Con ditio n CL (p F) V CC (V) tPLH tPHL tPLH tPHL tw tw(L) ts th tREM fMAX tOSLH tOSHL Propagation Delay Time CK to Q or Q Valu e T A = 25 oC -40 to Min. T yp. Max. Min. 7.3 15.0 1.0 9.8 18.5 1.0 Un it 85 o C Max. 18.5 22.0 2.7 2.7 15 50 3.3(*) 3.3(*) 2.7 2.7 3.3(*) 3.3(*) 2.7 15 50 15 50 15 50 50 3.3 (*) 50 6.0 7.0 Minimum Pulse Width LOW, PR or CLR 2.7 3.3(*) 50 50 8.5 6.0 10.0 7.0 ns Minimum Setup Time D to CK HIGH or LOW 2.7 3.3(*) 50 8.0 5.5 9.5 6.5 ns Minimum Hold Time D to CK HIGH or LOW 2.7 3.3(*) 0.5 0.5 0.5 0.5 ns Minimum Removal Time PR or CLR to CK 50 6.5 7.5 3.3 (*) 50 5.0 5.0 2.7 2.7 3.3(*) 3.3(*) 2.7 3.3(*) 15 50 15 50 50 Propagation Delay Time PR or CLR to Q or Q Minimum Pulse Width HIGH or LOW, CK Maximum Clock Frequency Output to Output Skew Time (note 1, 2) 2.7 5.7 8.2 8.4 10.9 6.6 9.1 9.7 13.2 15.6 19.1 10.1 13.6 8.5 50 50 50 55 45 95 60 135 60 145 85 1.0 1.0 1.0 1.0 1.0 1.0 11.5 15.0 18.5 22.0 12.0 15.5 10.0 50 40 80 50 1.5 1.5 50 ns ns ns ns MHz 1.5 1.5 ns 1) Skew is defined as the absolute value of the difference between the actual propagation delay for any twooutputs of the same device switching in the same direction, either HIGH or LOW 2) Parameter guaranteed by design (*) Voltage range is 3.3V ± 0.3V CAPACITIVE CHARACTERISTICS Symb ol Parameter Test Co nditions C IN Input Capacitance 3.3 CPD Power Dissipation Capacitance (note 1) 3.3 Valu e o Min. fIN = 10 MHz -40 to 85 C T yp. Max. 4 10 25 Un it o T A = 25 C V CC (V) Min. Max. 10 pF pF 1) CPD isdefined as the value of the IC’sinternal equivalent capacitance which is calculated fromthe operating current consumption without load. (Referto Test Circuit).Average operting current can be obtained by the following equation. ICC(opr) = CPD • VCC • fIN + ICC/2(per circuit) 5/11 74LVX74 TEST CIRCUIT CL = 15/50 pF or equivalent (includes jig and probe capacitance) RT = ZOUT of pulse generator (typically 50Ω) WAVEFORM 1: PROPAGATION DELAYS, SETUP AND HOLD TIMES (f=1MHz; 50% duty cycle) 6/11 74LVX74 WAVEFORM 2: PROPAGATION DELAYS (f=1MHz; 50% duty cycle) 7/11 74LVX74 WAVEFORM 3: RECOVERY TIMES (f=1MHz; 50% duty cycle) WAVEFORM 4: PULSE WIDTH 8/11 74LVX74 SO-14 MECHANICAL DATA mm DIM. MIN. TYP. A a1 inch MAX. MIN. TYP. 1.75 0.1 0.068 0.2 a2 MAX. 0.003 0.007 1.65 0.064 b 0.35 0.46 0.013 0.018 b1 0.19 0.25 0.007 0.010 C 0.5 0.019 c1 45 (typ.) D 8.55 8.75 0.336 0.344 E 5.8 6.2 0.228 0.244 e 1.27 e3 0.050 7.62 0.300 F 3.8 4.0 0.149 0.157 G 4.6 5.3 0.181 0.208 L 0.5 1.27 0.019 0.050 M S 0.68 0.026 8 (max.) P013G 9/11 74LVX74 TSSOP14 MECHANICAL DATA mm DIM. MIN. inch TYP. A MAX. MIN. MAX. 1.1 0.433 A1 0.05 0.10 0.15 0.002 0.004 0.006 A2 0.85 0.9 0.95 0.335 0.354 0.374 b 0.19 0.30 0.0075 0.0118 c 0.09 0.20 0.0035 0.0079 D 4.9 5 5.1 0.193 0.197 0.201 E 6.25 6.4 6.5 0.246 0.252 0.256 E1 4.3 4.4 4.48 0.169 0.173 0.176 e 0.65 BSC 0.0256 BSC K 0o 4o 8o 0o 4o 8o L 0.50 0.60 0.70 0.020 0.024 0.028 A A2 A1 b e K c E1 PIN 1 IDENTIFICATION 1 L E D 10/11 TYP. 74LVX74 Information furnished is believed to be accurate and reliable. However, STMicroelectronic s assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems withoutexpress written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics 2000 STMicroelectronics – Printed in Italy – All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com . 11/11