54FCT377 Octal D-Type Flip-Flop with Clock Enable General Description Features The ’FCT377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) input loads all flip-flops simultaneously, when the Clock Enable (CE) is LOW. n Clock enable for address and data synchronization applications n Eight edge-triggered D flip-flops n Buffered common clock n See ’FCT273 for master reset version n See ’FCT373 for transparent latch version n See ’FCT374 for TRI-STATE ® version n TTL input and output level compatible n CMOS power consumption n Output sink capability of 32 mA, source capability of 12 mA n Standard Microcircuit Drawing (SMD) 5962-8762701 The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop’s Q output. The CE input must be stable only one setup time prior to the LOW-to-HIGH clock transition for predictable operation. Ordering Code Military Package Package Description Number 54FCT377DMQB J20A 20-Lead Ceramic Dual-In-Line 54FCT377FMQB W20A 20-Lead Cerpack 54FCT377LMQB E20A 20-Lead Ceramic Leadless Chip Carrier, Type C Connection Diagram Pin Assignment for LCC Pin Assignment for DIP and Cerpack DS100952-11 DS100952-1 Pin Names D0–D7 Description Data Inputs CE Clock Enable (Active LOW) CP Clock Pulse Input Q0–Q7 Data Outputs TRI-STATE ® is a registered trademark of National Semiconductor Corporation. © 1999 National Semiconductor Corporation DS100952 www.national.com 54FCT377 Octal D-Type Flip-Flop with Clock Enable October 1999 54FCT377 Truth Table Mode Select-Function Table Operating Mode Inputs Output CE Dn Qn Load “1” I h H Load “0” I I L Hold h X No Change H X No Change CP (Do Nothing) X H = HIGH Voltage Level h = HIGH Voltage Level one setup time prior to the LOW-to-HIGH Clock Transition L = LOW Voltage Level I = LOW Voltage Level one setup time prior to the LOW-to-HIGH Clock Transition X = Immaterial = LOW-to-HIGH Clock Transition Logic Diagram DS100952-3 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.national.com 2 Current Applied to Output in LOW State (Max) Twice the rated IOL (mA) DC Latchup Source Current −500 mA (Across Comm Operating Range) Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias Ceramic VCC Pin Potential to Ground Pin Input Voltage (Note 2) Input Current (Note 2) Voltage Applied to Any Output in the Disabled or Power-Off State in the HIGH State −65˚C to +150˚C −55˚C to +125˚C Recommended Operating Conditions −55˚C to +175˚C Free Air Ambient Temperature Military Supply Voltage Military Minimum Input Edge Rate Data Input Enable Input −0.5V to +7.0V −0.5V to +7.0V −30 mA to +5.0 mA −0.5V to +4.75V −0.5V to VCC −55˚C to +125˚C +4.5V to +5.5V (∆V/∆t) 50 mV/ns 20 mV/ns DC Electrical Characteristics Symbol Parameter FCT377 Min Typ Units VCC Conditions Max VIH Input HIGH Voltage VIL Input LOW Voltage 0.8 V VCD Input Clamp Diode Voltage −1.2 V Min VOH Output HIGH Voltage V Min V Min IOH = −300 uA IOH = −12 mA IOL = 300 uA µA Max IOL = 32mA VIN = VCC VOL Output LOW Voltage IIH Input HIGH Current IIL Input LOW Current IOS Output Short-Circuit Current ICCQ Quiescent Power Supply Current ∆ICC Maximum ICC/Input 2.0 54FCT 4.3 54FCT 2.4 V 54FCT 0.2 54FCT 0.5 5 Recognized HIGH Signal Recognized LOW Signal IIN = −18 mA µA Max mA Max 1.5 mA Max VIN = 0.5V VOUT = 0.0V VI = 0.2V or VI = 5.3V, VCC = 5.5V 2.0 mA Max VI = VCC − 2.1V Data Input VI = VCC − 2.1V 0.4 mA/ Max −5 −60 All Others at VCC or GND ICCD Dynamic ICC MHz ICC Total Power Supply Current 6.0 mA Outputs Open One bit Toggling, 50% Duty Cycle Max VCC = 5.5V, Outputs Open, fCP = 10MHz, 50% Duty Cycle, One bit Toggling at fI = 5 MHz, 50% Duty Cycle Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs. 3 www.national.com 54FCT377 Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. 54FCT377 AC Electrical Characteristics Symbol Parameter 54FCT TA = −55˚C to +125˚C VCC = 4.5V to 5.5V Units Fig. No. ns Figure 4 CL = 50 pF Min Max tPLH Propagation Delay 2.0 15.0 tPHL CP to On 2.0 8.3 AC Operating Requirements Symbol Parameter 54FCT TA = −55˚C to +125˚C VCC = 4.5V to 5.5V Fig. Units No. ns Figure 6 ns Figure 6 ns Figure 6 ns Figure 6 ns Figure 5 CL = 50 pF Min ts(H) Setup Time, HIGH 4.0 ts(L) or LOW Dn to CP 4.0 th(H) Hold Time, HIGH 2.5 th(L) or LOW Dn to CP 2.5 ts(H) Setup Time, HIGH 4.5 ts(L) or LOW CE to CP 4.5 th(H) Hold Time, HIGH 2.0 th(L) or LOW CE to CP 2.0 tw(H) Pulse Width, CP, 7.0 tw(L) HIGH or LOW 7.0 Max Capacitance Max Units CIN Symbol Input Capacitance Parameter 10 pF COUT (Note 3) Output Capacitance 12 pF Note 3: COUT is measured at frequency f = 1 MHz, per MIL-STD-883B, Method 3012. www.national.com 4 Conditions VCC = 0V, TA = 25˚C VCC = 5.0V 54FCT377 AC Loading DS100952-4 *Includes jig and probe capacitance DS100952-5 FIGURE 1. Standard AC Test Load FIGURE 5. Propagation Delay, Pulse Width Waveforms DS100952-6 FIGURE 2. VM = 1.5V DS100952-9 Input Pulse Requirements FIGURE 6. Setup Time, Hold Time and Recovery Time Waveforms Amplitude Rep. Rate tw tr tf 3.0V 1 MHz 500 ns 2.5 ns 2.5 ns FIGURE 3. Test Input Signal Requirements DS100952-8 FIGURE 4. Propagation Delay Waveforms for Inverting and Non-Inverting Functions 5 www.national.com 54FCT377 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Ceramic Chip Carrier NS Package Number E20A www.national.com 6 54FCT377 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Ceramic Dual-In-Line Package NS Package Number J20A 20-Lead Ceramic Flatpack NS Package Number W20A 7 www.national.com 54FCT377 Octal D-Type Flip-Flop with Clock Enable Notes LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation Americas Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: [email protected] www.national.com National Semiconductor Europe Fax: +49 (0) 1 80-530 85 86 Email: [email protected] Deutsch Tel: +49 (0) 1 80-530 85 85 English Tel: +49 (0) 1 80-532 78 32 Français Tel: +49 (0) 1 80-532 93 58 Italiano Tel: +49 (0) 1 80-534 16 80 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Asia Pacific Customer Response Group Tel: 65-2544466 Fax: 65-2504466 Email: [email protected] National Semiconductor Japan Ltd. Tel: 81-3-5639-7560 Fax: 81-3-5639-7507 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.