SHARP LRS1329

PRELIMINARY PRODUCT SPECIFICATIONS
®
Integrated Circuits Group
LRS1329
Stacked Chip
16M Flash and 2M SRAM
(Model No.: LRS1329)
Spec No.: MFM2-J11601
Issue Date: June 10, 1999
SHARP
LRS1329
l
Handle this document carefully
for it contains material protected
by international
full
or
in
part,.
of
this
material
is prohibited
copyright
law. Any reproduction,
without
the express written
permission
of the company.
l
When using the products covered herein, please observe.the
conditions
written
herein
and the precautions
outlined
in the following
paragraphs.
In no event shall the
company be liable for any damages resulting
from failure
to strictly
adhere to these
conditions
and precautions.
(1) The products covered herein are designed and manufactured for the following
application
areas.
When using the products
covered herein for the equipment
listed in Paragraph (2), even for the following
application
areas, be sure
to observe the precautions
given in Paragraph (2).
Never use the products
for the equipment listed
in Paragraph (3).
*Office
electronics
* Instrumentation
and measuring
*Machine tools
-Audiovisual
equipment
*Home appliances
* Communication equipment other
equipment
than for trunk
lines
(2) Those contemplating
using the products
covered herein for the following
equipment which demands high reliability,
should first
contact a sales
representative
of the company and then accept responsibility
for incorporating
redundancy, and other appropriate
measures
into the design fail-sale
operation,
for ensuring reliability
and safety of the equipment and the overall
system.
*Control
and safety devices for airplanes,
trains,
transportation
equipment
* Mainframe computers
-Traffic
control systems
. Gas leak detectors
and automatic cutoff devices
*Rescue and security
equipment
. Other safety devices and safety equipment,etc.
automobiles,
and other
(3) Do not use the products
covered herein for the following
equipment which
demands extremely high performance
in terms of functionality,
reliability,
.
accuracy.
* Aerospace equipment
. Communications equipment for trunk lines
*Control
equipment for the nuclear power industry
-Medical equipment related to life support,
etc.
(4) Please direct
all queries and comments regarding
above three Paragraphs
to a sales representative
l
Please direct
representative
all queries regarding
of the company.
the products
covered
the interpretation
of the company.
herein
to a sales
of the
or
SHARP
1
LRS1329
Contents
1. Description
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
. . . . . . . . . . . . . . . . . . . . . . . . . .
4
- * - - * - * - - - - - * - - - -
5
. . . . . . . . . . . . . . . f . . . . .
8
. . . . . . . . . . . . . . .
8
. - . . . . . a . . . . . a . - . a s s s s s ‘- s - e
8
4. Block Diagram
5. Command Definitions
8. Absolute
for Flash
Maximum Ratings
9. Recommended DC Operating
10. pi*
Memory
Capacitance
Conditions
- * - * - * * * + * - * - - * - * - *
11. DC Electrical
Characteristics
12. AC Electrical
Characteristics
(Flash Memory)
13. AC Electrical
Characteristic’s
(SRAM)
14. Data Retention
15. Notes
Characteristics
- * - * * - * * - * - * -
- - * - * - - - - - - * - - - * -
for SRM
* - * - * - - - * - - - * - - -
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17. Design Consideration
. . . . . . . . . . . . , . . . . . . . . . . . .
9
11
18
21
22
24
SHARI=
LRS1329
2
Part 1 Overview
1. Description
The LR S 1 3 2 9 is a combination memory organized as lMx16/2M
flash memory and 256K x8 bit static
RAM in one package.
~8 bit
Features
OPower
. . . .
supply
OOperat ing temperature
ONot
0
designed
72 pin
OFlash
Flash
or rated
as radiation
memory has
to
3.6 V
-25
“c to
+85 ‘c
bulk
silicon.
hardened
( LCSPO72-P-0811
CSP
2.7 v
. . . .
) plastic
P-type bulk silicon,
package
and SRAM has
P-type
Memory
OAccess
. . . .
Time
OOperating
current
(Ihe current
Read
for
Word/Byte
Block
ODeep power down current
OOptimized
F-V,
100 ns
pin)
. . . - 25 mA (Max. t,U=200ns)
. . . . 17 mA (Max.)
. . . - 17 mA (Max.)
write
erase
(The current
Array Blocking
(Max.)
* * * * 10
for F-V,, pin)
Architecture
Two 4X-word/8K-byte
Boot Blocks/
Six 4K-word/8K-byte
Thirty-one
32X-word/64K-byte
Main Blocks/
Top
0 Extended Cycling
PA (Max. F-ZZF-Vcc-0.
F-EsO.
ZV, F-V&O.
Parameter Blocks/
Boot Location
Capabi 1 i ty
~100,000 Block
Erase Cycles
0 Enhanced Automated Suspend Options
Word/Byte
write
Suspend
to Read
Block Erase Suspend to Nerd/Byte
Block Erase Suspend to Read
SRAM
.
OAccess
Time
OOperat
ing current
OStandby
OData
current
retention
current
write
. . . .
85 ns
. . . .
30 d
. . . .
3
. . . .
15 PA (Max.)
. . . .
15 ,uA (Max.)
&ax. >
OhL >
mA (Max. t,, t,=lp
s)
2V,
2V)
SHARP
LRS1329
2. Pin Configuration
r
INDEX
Block erase and Word/Byte Write : Vi, or V w,
Read 1 V,, or V k,,
Deep Power Down: VIL
F7@
Write Protect (Flash)
Two Boot Blocks Locked : ViL
(With F-&V m,Erase/Write can operate to all block)
F-BYTE
Byte Enable (Flash);
x8 mode: VIL, x16 mode: VI,
Ready/Busy (Flash)
F-RY/BY
During an Erase or Write operation: V,,
Block Erase and Word/Byte Write Suspend: High-Z
Deep Power Down: V,
DQ,to
DQ,
Data Input/Outputs (Common)
F-DQ 8 to F-DQ is Data Inputs/Outputs (Flash) ; Not used in x8 mode.
Power Supply (Flash)
F-V,,
Power Supply (SRAl4)
s-“cc
Write, Erase Power Supply (Flash)
F-V,,
Block Erase and Word/Byte Write : F-V,,=V,,,
:
Al 1 Blocks Locked 1 F-V,,<Vppll(
F-GND
GND (Flash)
GND (SRAM)
S-GND
No
Connect
NC
r
T, to T,
Test pins (Should be open)
3
SHARI=
4
LRS1329
3. Truth Table (*l)
Note
SRAM
Flash
F-B
*4.5
Read
F-3
Standby
’
Standby
L
H
*6
Write
*6
*6
DIN
DIN
High-Z
DOUT
L
H
H
’
’
L
H
H
X
High-Z
High-Z
DIN
L
DOUT
L
*6
H
X
XLXXLH
H
High-Z
DIN
L
*6
H
H
*6
x
L
Standby -
x
L=V,,, H=V,, , X=H or L . Refer
x
x
*7
Bigh-2
-
*6
’
Power
H
L
L
H
Write
*l.
x
*7
*6
Read
output
Disable
Read
Power Output
Disable
Reset
Down
S*
L
*2,3,4
Standby
F-DQ
F-mtoDPh
, to hu&
H
DOUT
L
DOUT 1 High-Z
Bigh-Z
x.7-.
S-CE, S-GE, S-s
H
Write
Reset
Down
F-E
H
output
Disable
tes)
F-a
x
High-Z
x
to DC Characteristics.
*2. Command writes
involving block erase or word/byte
write are reliably
executed when
F-V,,+.,
and F-V,=2.7V to 3-W. Block erase or word/byte
write with V,,<F-B<V,
produce spurious
results
and should not be attempted.
*3. Refer Section 5. Flash Memory Comand Definition
for valid DIN during a write operation.
*4. Never hold F-2 low and F-s
low at the same timing.
*5. F-A., set to V,, or VI, in byte mode (F-BYTE=Vn).
-1
*6. F-‘RP set to V,, or V,, .
*7. See the following
SRAM Standby mode.
Block Diagram
F-V,
F-V,
F-GND
----------------,
.
.F-?i?
i
F-X
F-E
F-m
F*
F-BYTE
:’
+
:>
:T
> F-RY/?%
=-
16M(x8/x16) b i t
Flash memory
F-D’& to F-W,,
+DQ,
S-A,,
S-E,
s-c>
S-OE
S-IRE
4 b
I >
j >
; >
2M (x8) bit
SRAM
s-v,
S-GND
to W,
SHARP
I 5 Command Definitions
for Flash Memory (*I)
Word/Byte Write
Block
Write
Block
Write
5
LRS1329
Erase and Word/Byte
Suspend
Erase and Word/Byte
Resume
I
2
*5
Wr i t,e
WA
4OH or
10H
1
*5
Write
XA
Boll
1
*5
Write
XA
DOH
Note)
*l.
Write
WA
Commands other than those shown above are reserved by SHARP for future device
implementations
and should not be used. ’
*2. BUS operations
are defined in 3. Truth Table.
*3. XA=Any valid address within
the device.
IA=Identifier
Code Address.
BA=Address within
the block being erased.
WA=Address of memory location
to be written.
SRD=Data read from status
register(See
the next page”Status
Register
Definition”).
WD=Data to be written
at location WA. Data is latched on the rising
edge of
F-%?or F-5 (whichever
goes high first).
II&Data read from identifier
codes.
*4. See the Following
Identifier
Codes.
*5. See the following
Write Protection
Alternatives.
Write
Operation
Block Erase
or
Word/Byte Write
F-V,,
VIL
>V,,
F-i@
X
V
“t
v
IH
VIH
Protection
Alternatives
F?@
X
X
X
VIL
VIH
Effect
All Blocks Locked.
All Blocks Locked.
All Blocks Unlocked.
2 Boot Blocks Locked.
All Blocks Unlocks.
WD
SHARP
6. Status
WSMS
7
LRS1329
Register
6
Definition
ESS
ES
6
5
WBWS
VPPS
4
3
WBWSS
2
DPS
R
1
0
NOTES:
S R. 7= WRITE STATE MACHINE STATUS( W SMS)
1 = Ready
0 = Busy
SR.
6= ERASE SUSPEND STATUS( ESS)
1 = Block Erase Suspended
0 = Block Erase in Progress/Completed
If both SR. 5 and SR.4 are “1”s after a block
erase attempt, an improper command sequence
was entered.
SR.5=ERASESTATUS(
ES )
1 = Error in Block Erasure
0 = Successful
Block Erase
S R. 4= WORD/BYTE WRITE STATUS ( WBWS
1 = Error in Word/Byte Write
0 = Successful
Word/Byte Write
SR.
Check RYm or SR.7 to determine block erase OI
word/byte
write completion.
SR.6-0 are invalid
whi 1e SR. 7=“0”.
3= V,, STATUS ( VPPS
)
1 = F-V,, Low Detect, Operation
0 = F-V,, OK
Abort
S R. 2 = WORD/BYTE WRITE SUSPENDED STATUS
(WBWSS)
1 =Word/ByteWrite
0 =Word/ByteWrite
)
SR.3 does not provide a continuous
of F-V,, level. The WSM interrogates
indication
and
indicates
the F-V,, level only after Block
Erase or Word/ByteWrite
command sequences.
SR.:
is not guaranteed to reports
accurate
feedback
on 1y when F-V, +Vepm,2.
Suspended
in Progress/Completed
S R . l= DEVICE PROTECT STATUS ( D P S )
1 = F-‘WP or F-@’ Lock Detected,
Operation Abort
0 = Unlock
The WSM interrogates
the F-s and F-E only
after Block Erase orWord/ByteWrite
command
sequences. It informs the system, depending
on the attempted operation,
if the F-w is
not VIM, F-E is not Vm+
S R. 0 = RESERVEDFOR FUTURE ENBANCEMENTS
4,R >
SR.0 is reserved for future use and should
masked out when polling the status
register.
be
SHARP
7
LRS1329
Memory Map for Flash
Memory
Address
[A,.-hl
4K*word/8K-byte
Parameter
4K-word/BK-byte
Parameter
Block
4K-word/BK-byte
Parameter
Block
32K-word/64K-byte
Main
Block
32X-word/64K-byte
Main
Block
323.word/64K-byte
Main
Block
32K-word/64K-byte
Main
Block
32K-word/64K.byte
Main
Block
32K-word/64K-byte
Main
Block
32K-word/64K-byte
Main
Block
32K-word/64K-byte
Main
Block
32K-word/64K-byte
Main
Block
32K-word/64K-byte
Main
Block
32K-word/64K-byte
Main
Block
32K-aord/64K-byte
Main
Block
32K-word/64K-byte
tdain
Block
32K-word/64K-byte
Main
Block
32K-word/64K-byte
Main
Block
32K-word/64K-byte
Main
Block
32K-word/64K-byte
Main
Block
32K-word/64K-byte
Main
Block
32K-word/64K-byte
Main
Block
32K-word/64K-byte
Main
Block
32K-word/64K-byte
Main
Block
32X-word/64K-byte
Main
Block
32K-word/64K-byte
Main
Block
32K-word/64K-byte
Main
Block
32K-word/64K-byte
Main
Block
32K-word/64K-byte
Main
Block
32K-word/64K-byte
Main
Block
32K-word/64K-byte
32K-word/64K-byte
Main
Main
Block
Block
32K-word/64K-byte
I ~~~
32K-word/64K-byte
19
MSB
18
17
X8
.....
Mode
Block
2
1
0
LSB
Main
Block
Main
Block
20
YSB
19
I
18
X16
.....
Mode
2
1
0
LSB
I
SHARP
8.Absolute
LRS1329
I?
Maximum Ratings
Parameter
Ratings
Symbo 1
* Supply voltage (*l, 2)
-0.2
Input voltage (*l, 3)
Vcc
VIN
Operating
TOPT
-25
T,
-65
Storage
temperature
temperature
F-V,, voltage (*l)
F-E
Notes)
voltage (*l)
*l.
-0.2
(*4)
Unit
to
+4.6
V
to vcc+o.3
V
to
to
‘c
c
V
V
+85
+125
F-;pr
-0.2
(*4) to
+14.0(*5)
F-E
-0.5
04
+14.0(*5)
The maximum applicable
voltage
to
on any pins with
respect
.
CND.
to
*2. Except F-V,,.
*3. Except F-E.
*4. -2.OV undershoot
is allowed
when the pulse width
is less
than 20nsec.
*5.
is allowed
when the pulse width
is less
than 20nsec.
i-14.OV overshoot
9.Recommended DC Operating
Conditions
(T,= -25
Parameter
Supply voltage
Input voltage
Notes)
Symbo1
v,
VIII
Min.
TYP.
2.7
3.0
2.2
VIL
-0.2
v, (*3)
11.4
(*2)
10. Pin Capacitance
Input
(T,=25r,
Symbo 1
Condition
Min.
TYP.
“c
Max.
Unit
3.6
V
v,+o.
*1. V, is the lower one of S-V,, and F-V, _
*2. -2.OV undershoot
is allowed when the pulse width
*3. This voltage is applicable
to F-B Pin only.
Parameter
“c to +85
3(*1)
0.8
v
V
12.6
V
is less
)
than 20nsec.
f=lMHz)
kx.
Unit
capacitance
Crw
vIN=ov
20
pF
*I
I/O capac i tance
CI/o
VI/o=oV
22
pF
*l
Note)
*1 Sampled but not 100% Jested
SHARI=
9
LRS1329
11. DC Characteristics
Character
Symbo1
Parameter
Input leakage current
)utput’
F-V,
istics
(Iti)
leakage current
(IJ
V, Standby Current
ILX
(T.= -25 “r: to +85
c,
V,=
2.7V
G#pJy
Conditions
V,, =V, or CND
Ll
bcs
(*2,7)
F--%F-V,
+1.5
-1.5
VOIR=V, or GND
F-E=F-3=F-V,
fO.2V
Current
(*7)
T-VPI
V, Deep Power-Down
S-V,
I cm
I,,,
I PPS
I
I PPP
F-V,, = F-V,,
F-V, > F-V,,
I PPD
F-@=F-GNDfO. 2V
VP, Block Erase ‘Current
F - ‘4,
slack Erase Suspend
Zurrent
Standby Current
Operation Current
I
I4mA
I
I
I I I6b
F-CE=V,,
F-V, =v,,,
Word/Byte Write or
I
F-Vpp=vpp”
Current
fpp Word/Byte Write Curren I PW
I,,
II
LOUT
(F-RY~bC-mA
2mA
F-V, =vpp,
J,, Word/Byte Write Current
V, Block Erase Current
J, Word/Byte Write Block
!rase Suspend Current
VP, St andby or
ReadCurrent
0.2
MOS Input
:-Cj?=F-GND,
f=5Mlz. I,,, =OmA I
TL Input
%=F-GND, f=SMBz, Iom =omA
V, Read Current
PA
or F-CNDfO. 2V
:-%=F-CNDfO. 2V,
bCD
pA
50
25
fO.2V
F-z=F -@=V,,
F-%‘=V,, or VIL
Deep Power-Down
to 3.6V)
I PPE
I PPIS
I PPES
,I I lo1
2ool
pA
F-V, =V,,,
.
I
S-CE,=V,aor S- CEa=ViL
I cc1
s -CE,=V,,,
s -C&=V,,
VIN=VI~
I
pA
15
S-CE,IO. 2V
ISBl
I cc2
I
S-CE,, s-cE.&s-v,-0.2v
or
I
I
=VPPII
I
I SB
I
or
3.0
DlA
3o
DlA
t ,,=Min.
II/O=omA
V,II
s -CE,=o.2v,
s-C&=S-vcc-0.2v
VIN=S-vCC-O.
2V
or 0.2V
t cYa.B=~
Ps
Im--om
I I I 31*
I
I
I
I
SHARP
10
LRS1329
DC Characteristics
(Continue)
-25’c
to
+ss”c
, V,=
2.7 V to 3.6v)
Notes)
1. Reference values at V,=3.OV and T,=+25”C.
2. Includes F-RY/BY.
3. Automatic Power Savings (APS) for Flash Memory reduces typical I,,, to 3mA
at 2.7V V, in static
operation.
4. CMOS inputs are either V, fO.2V or GNMO.2V. TTL inputs are either Vi, or Vi,.
5. Block erases and word/byte
writes
are inhibited
when F-V,, SV,,, and not guaranteed
in the range between V,, (max) and V,, (min), and above V,, (max).
6. F-3 connection to a V, supply is allowed for a maximum cumulative
7. F-m
is V&O.2V in word mode and is CWO.2V
in byte mode.
F-@
is V&O.ZV
or CNDztO. 2V.
period
of 80 hours.
SHARP
12. Flash
memory AC Characteristics
AC Test Condtions
Input pulse level
Input
rise
Input
and Output
~ Output
and fall
0 v to 2.7
ns
5
time
timing
Ref.
level
load
1.35
*l.
Write
F-n
Cycle
V
V
lTTLfc, (30pF)
CT,= -25°C
Read Cycle
Notes)
11
LRS1329
may be delayed
(F-E
up to tuQ,-k,,after
Controlled)
(*2)
to
+SS”c
the falling
edge of F-OEwithout
(T,=
to
-25°C
+85”c
Parameter
Write
Recovery
before
F-V,, Hold from Valid
F-E
F-w
1
V,,,,Hold from Valid
Vi, Hold from Valid
SRD, F-RY/k@-High
SRD, F-RY/B?High
F-BYTE Setup to F-E Going High
F-BYTE Hold from F% Hinh
I
impact
on t,,
to
Max.
3.6V)
Unit
ns
t9VPH
0
ns
t9VSL
0
ns
hlH
50
ns
WL
Z
3.6V )
0
0
hHCL
Z
to
, V$ 2.7v
Min.
Read
SRD, F-RY/BTHigh
) v,(y 2.7
tn
I
100
ns
1
I
ns
I
SHARP
Write
Notes)
Cycle
12
LRS1329
(F-z
Control led) (*2)
(T,=
-25°C
to +85X
) V,F
2.7v
to 3.6v)
*2. Read timing characteristics
during block erase and word/byte
write operations
are th
same as during read-only
operations.
Refer to AC Characteristics
for Read Cycle.
*3. Refer to Section 5. Flash Memory Command Definition
for valid &N and DIN for block
erase or word/byte
write.
LRS1329
Block
Erase and Word/Byte
Write
Performance
(T,= -25°C
hHav2
t MPVZ
Block Erase
32K-word
Block
Time
64K-byte
Block
huur
Word/ByteWrite
hnRz1
Latency
hm3z2
Erase Suspend Latency
to Read
hlmz2
4K-word
Block
8K-byte
Block
to
+85 c,
Suspend
V,= 2.7 V to 3.6 V j
1.2
s
0.5
s
7.5
8.6
PS
19.3
23.6
P’s
Time to Read
Time
^-
- --. __ - _--
SHARP
LRS1329
Flash Memory AC Characteristic
Read Cycle timing chart
Timing Chart
Device
Address Selection
Address
Address
Data Valid
Stable
L
HIGH Z
DQ
F-V,
F-BYTE timing
Waveform
Device
Address Selection
Standby
Address
Address
Data Valid
Stable
m
F-BYTE
)ATA (D/Q>
(IQ,-W>
HIGH Z
c
DATA @/Cl)
HIGH Z
t AVPV
k
I
t Pm
HIGH Z
SHARP
Write
cycle
LRS1329
timeng chart
*1
I-l-A
(F-E
controlled)
*2
,
Address
F-E
w
F-Bm
F-RY/BY
t,
(
b.L
L
F-WP
\
/
hWH)
himlII>
l-
F-i@
(
~Wvll
>
F-V,,
Notes:
*l. V,, Power -up and standby.
*2. Write block erase or word/byte
write setup.
*3. Write block erase confirm or valid address and data.
*4. Automated erase or program delay.
*5. Read status register
data.
*6. Write Read Array command.
tjt
am
*6
,_
SHARP
Write
cycle
LRS1329
timing
*1
l-V--%
chart
(F-E
controlled)
A
Address
F-E
F-Z
F-E
w
F-BYTE
F-RY/BY
Notes:
*l. V,, Power-up and standby.
*2. Write block erase or word/byte
write setup.
*3. Write block erase confirm or valid address and data.
*4. Automated erase or program delay.
*5. Read status register
data.
%. Wri te Read Array command.
16
SHARP
17
LRS1329
Reset Operations
(T,= -25 ‘c to
Parameter
F-E Pulse Low Time
(If F-E.is
tied to Vcc, this specification
applicable.)
F?@ Low to Reset during Block Erase or
Write
F-V,, 2.7V to F-B High
is not
+85 ‘c ,
SW.
Min.
true
100
Vcc= 2.7V to 3.6 V )
Max.
ns
23.6
hz
h
Unit
100
,u s
*1,2
ns
*3
iotes)*l.
If F-B is asserted while a block erase or word/bytewrite
operation
is not
executing, the reset will complete with loons.
*2. A reset time, t,,. is required from the later of F-RY/BY going High Z of F-E going
high until outputs are valid.
*3. When the device power-up, holding F-3 low minimum 1oOns is required after Vcc has
been in predefined range and also has been in stable there.
AC Waveform for Reset Oneration
High Z
FRY/BY @)
voL
VIII
F -@ (P)
VI, -
\
(
/
)
t,m
(A)Reset During Read Array Mode
High Z
F-RY/BY(R)
7
VOL
I(
tpu.2
>
VIII
F-B (P)
VIL
r
I-
(
>
t,LPil
.
(B)Reset During Block Erase or Word/Byte
F-i@(P)
(C)F-E
Rising
Timing
Write
SHARP
LRS1329
13. SRAM AC Electrical
18
Characteristics
SRAM AC Test Conditions
Input pulse
Input
level
rise
and fall
Input and
1Output
0.4 v to 2.2
I
Output
time
5 ns
timing
Ref.level
1.5
load
Note)
*l.
Read
Cycle
scope and jig
=C to
+85
Sym.
Parameter
hc
Read Cycle Time
access
‘c
, v,=
Min.
V)
Unit
.
ns
85
85
ns
hcE1
85
ns
hca
85
ns
time(S-E)
(s-c&J
2.7Vto3.6
Max.
hA
time
Chip enable access
(*l)
capacitance.
(T,= -25
Address
V
llTLtC, (30pF)
Including
v
*2
*2
*2
*2
*2
*2
Write
Cycle
(T,= -25 “c to +85
L
S-z
High to output
S-B
Low to output
*2. Active
specified
output
for
active
in High impedance
t 01
5
t,
0
C
from steady
state
V to
25
to High impedance and High impedance to output
a f20OmV transition
, v,=2.7
levels
active
into
3.6 V )
ns
*2
ns
*2
tests
the test
load.
SHARP
SRAM AC Charaterestics
Read cycle
19
LRS1329
timing
Timing Chart
chart-
(*3)
Address
s -CE,
S-C&
S-X
DOOI
*3 S%? is high for Read cycle.
Write
cycle
timing
chart-
(S-E
Controlled)
tic
<
Jf
Address
>
‘(
S-OE
S-CE,
S-CE,
t OIL?
(*I
’
I
tow
>
<
(*lo)
DOUT
\\\\\\\\\\\\\\
trn
DIN
(*8)
/
\
,,
/'
Data Valid
km
SHARI=
Write
cycle
LRS1329
timing
chart-(S-aLow
20
fixed)
Address
Dwr
/ /
/
,
,
,
,
,
I I
I
I
I,
ta
<
(*s)
./
/‘A
/
DIN
I-
tm
Data Valid
Notes)
*4.
A write
occurs
during
A write
begins
at the latest
high and S-mgoing
A write
going
tcr is measured
of a low SE,,
a high S-C& and a low S-x,
transition
among S-m
going low,
transition
among S-z,
going high,
S-CE,going
low.
ends at the earliest
and S-E
*5.
the overlap
high.
twis
measured from the beginning
from the later
of S-going
S-CE, going
of write
low
to the end of write.
low or S-C& going high
to the end of write.
*6.
tAs is measured
.
from the address
*7.
tm is measured
from the end of write
a.
During
*9.
this
W pins
signals
of opposite
If S-E,
goes low or S-C&
S-WE going
*10.
period,
If S-XI
S-E
low,
to the beginning
to the address
are in the output
phase to the outputs
state,
the outputs
the outputs
of write.
change.
therefore
the input
must not be applied.
goes high simultaneously
goes high or S-C&
going high,
valid
remain in high
S-E
going
low or after
impedance state.
goes low simultaneously
remain in high
with
with
S%
impedance state.
going high or
SHARP
LRS1329
14.SRAM Data
Retention
21
Characteristics
(T,=
Parameter
Conditions
sym.
Data Retention
Min.
VCCDB S-C& SO. 2V or
S-CE,~V,w-O.
2v (*2>
Supply volotage
Data Retention
I cccm
-25°C
to
+35”c
Typ. (*l)
2.0
>
Max.
Unit
3.6
V
15
pA
v,,=3v
Supply current
S-C&SO.
S-E
2V or
LV,,-0.2v
0.2
(*2)
Chip enable
setup
time
bDR
0
ns
tR
5
lCS
Chip enable
hold time
Notes)
*l. Reference value at T,=25’c, S-V,=3. OV.
*2. S-CE,ZV,-O.2V,
S-CE.&V,-0.2V
(S-E, control
Data Retention
timing
chart
Data Retention
-VCC
-_---
timing
chart
Data Retention
- . ....---..
0. 8
v
led)
mode
.
... ....--..--
(S-CEz Control led)
_.. . ...- -i-‘
Data Retention
. .._. _. .. ..__._._-_..__._._ ._-_.--.-__-.
CDP
. CE,
control
____I__.___..._ _....-.....- -_ -I-..._- -I_
-.-----s-e-
/
2.JV
2V (S-C&
(S-%Controlled)(*3)
L
()v --.---I
led) or S-C&SO.
mode
.
/
_.-._.... _.._. .. ... .. .. .. . _..__.._ _..__ .. .. ...-_.... _..._.._...__.._----_
. . .. .. .. .. .. ...
,
___.._..__.___ _________._. __________________.........~ _.__.____.____.______
__.____. ___________.__._______...................... ._..___._.__.........................
Note) *3. To control
the data retention
mode at S-z,,
fix the input level of
S-C& between V,, and Vcc, -0.2V or OV or 0.2V and during the data retetion
_. . .. .. .. ._.. .. ..
mode.
SHARP
22
LRS1329
15. Notes
This product is a stacked
CSp package that a
2M (x8) bit SWAMare assembled into.
and a
Supply Power
Maximum difference
(between F-V,x and S-V,)
16M(x8/x16)
of the voltage
bit
Flash Memory
is less than 0.3V.
Power Supply and Chip Enable of Flash Memory and SRAM
S-E1 should not be LOW and S-Q should not be BIGH when F-Eis
LOW
simulataneously.
.If the two memories are active together, possibly they may not operate normally by
interference
noises or data collision
on W bus.
Both F-V, and S-V, are needed to be applied by the recommended supply voltage at the
same time except SWAMdata retention
mode.
Power UP Sequence
When turping on Flash memory power supply, keep F-B LOW. After F-V,, reaches over
2.7V, keep F-a LOW for more than 100nsec.
Device Decoupling
The power supply is needed to be designed carefully
because one of the SRAM and the
Flash Memory is in standby mode when the other is active. A careful decoupling of power
supplies is necessary between SWAMand Flash Memory. Note peak current caused by transition
of control signals (F-E, S-CE,, S-C&).
SHARP
16.Flash
LRS1329
23
Memory Data Protection
Noises having a level exceeding the limit specified
in the specification
may be generated
under specific operating conditions on some systems.
Such noises, when induced onto F-W signal or power supply may be interpreted
as false
commands, causing undesired memory updating.
To protect the data stored in the flash memory against unwanted overwriting,
systems
operating with the flash memory should have the following write protect designs, as
appropriate:
1) Protecting
data in specific block
By setting a F?? to low, only the boot block can be protected
Parameter and main blocks cannot be locked.
System program, etc., can be locked by storing them in the boot
When a high voltage is applied to F-E, overwrite operation is
For further information
on setting/resetting
of block bit,and
refer to the specification.
(See 5.Command Definitions
P.5)
against
overwriting.
block.
enabled for all blocks.
controlling
of F-e and F-D,
2) Data protection
through Vpp
When the level of Vpp is lower than VPPLK(lockout
voltage),
write operation on the
flash memory is disabled.
All blacks are locked and the data in the blocks are completely
write protected.
For the lockout voltage,
refer to the specification.
(See Chapter 11. DC Characteristics
P-10)
Data protection
during
voltage
transition
1) Data protection
thorough F-s
When the F-E is kept low during power up and power down sequence, write
the flash memory is disabled,
write protecting
all blocks.
For the details of F-E control,
refer to the specification.
(See chapter
AC Electrical.Characteristics)
operation
on
.
12. Flash Memory
SHARF)
24
LRS1329
17. Design Considerations
1. Power Supply Decoupling
To avoid a bad effect to the system by flash memory power switching characteristics,
each device should have a O.lpF ceramic capacitor connected between its V, and GND
and between its V,,and CND. Low inductance capacitors should be placed as close as
possible to package leads.
2. V,,Trace on Printed
Circuit
Boards
Updating the memory contents of flash memories that reside in the target system requires
that the printed circuit
board designer pay attention
to the Vr, Power Supply trace.
Use similar trace widths and layout considerations
given to the Vcc power bus.
3. The Inhibition
of Overwrite
Operation
Please do not execute reprogramming “0” for’the bit which has already been
programed “0”. Overwrite operation may generate unerasable bit.
In case of reprogramming “0” to the data which has been programed “1”.
* Program “0” for the bit in which you want to change data from “1” to “0”.
* Program “1” for the bit which has already been programmed “0”.
For example, changing data from “1011110110111101”
“1110111111111110” programming.
to “1010110110111100”
requires
4. Power Supply
Block erase, full chip erase, word/byte write and lock-bit
configuration
with an invalid
V,,(See 11. DC Characteristics)
produce spurious results and should not be attempted.
Device operations at invalid Vcc voltage(see
ll.DC Characteristics)
produce spurious
results and should not be attempted.
I
INDEX
I
01
6
-- +o
I
TOP
VIEW-,--
---e-e
-----a
-i-
0
ai
0
I
:
0
----.
---
0
1
\\\ 1’
,
\i\ i
/II‘
I’ \/
----____
1
II 1 u c-1 ,:\j,
\\\
,II ”
1. 1 TYP. =
,=
0. 8 TYP.
0. 4 TYP.
/
a
4
BOTTOM
--VIEW
C
to
I
I
I
?z000bOL!000OOO
”
0000~0000
P
oooo;ooo~
m
.----e-vP
0000~0000
”
m
OJ
3
\/
\
/I
ti
c
a,
d
v
I
I
1
1
0 0 0 oT~~~j-cc.----
I
OOOOiOOOO
0000~0000
~0000601000000
1 2 3
4
5
6,171
i=?ESSCALE
I
6
9101112
WI UNIT
I
slF%H
APPL
5/l
-
-
SC’b’J71
MATRIX
l=l/lmm
t
16M
c.4aLz
FLASH
+ZM
.yEMORYCXL6aa)
SRAM
CXSI
MODEL
LCSPO72-P-081