PE-A2 Optimizing the Output Configuration of Semtech Bipolar Pin Drivers TEST AND MEASUREMENT PRODUCTS Background: Connecting a Pin Driver to a Test Device Ideally, the Driver output from a Driver/Comparator/Load (DCL) IC would be connected to the Device Under Test (DUT) pin with a perfect transmission line. The most common connection scheme is for the DCL to be impedance-matched to the transmission line while the DUT end of the line is unterminated. In this case, the driver waveform would be exactly reproduced at the DUT, and DUT waveforms would be perfectly reproduced at the Comparator. This perfect transmission line includes perfect impedance matching at the DCL end as well as no parasitic resistance, capacitance or inductance anywhere along the line. If the real impedance is correctly matched, but there is a capacitive or inductive mismatch (imaginary portion of the source impedance), then there will be a glitch in the waveform when driving an unterminated transmission line as shown in Figure 2. This effect is greatest at the fastest rise/fall times, so checking and optimizing this behavior should be done at the fastest slew rates of interest. Note that when the L-C balance is correct, the amount of slowing of the rise/fall times caused by the impedance mismatch is minimized. This can be seen by expanding Figure 2 around the pulse rising edge as done in Figure 3. The amount of improvement will be maximized for the fastest rise/fall times. In practice, there are usually a number of things which degrade the AC performance. For instance, if the source impedance of the DCL is not perfectly matched to the transmission line impedance, there will be amplitude errors in the waveform. If the low frequency (real) portion of the source impedance is incorrect, then there will be a step in the waveform when driving an unterminated transmission line, as shown in Figure 1. DC Impedance Matching 4.0 R-out<50 ohms R-out=50 ohms R-out>50 ohms 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 -0.5 0.0 5.0 10.0 15.0 20.0 Time(ns) Figure 1. Typical Waveforms When Driving a 3.3V Signal into a 50Ω Transmission Line with Varying DC Source Impedance Revision 1 / December 18, 2002 1 www .semtech.com PE-A2 Optimizing the Output Configuration of Semtech Bipolar Pin Drivers TEST AND MEASUREMENT PRODUCTS AC Impedance Matching 4.0 3.5 3.0 2.5 impedance too inductive correct L-C balance impedance too capacitive 2.0 1.5 1.0 0.5 0.0 -0.5 0.0 5.0 10.0 15.0 20.0 Time(ns) Figure 2. Typical Effects from AC (Capacitive/Inductive) Impedance Mismatch AC Impedance Matching 4.0 3.5 3.0 2.5 impedance too inductive correct L-C balance impedance too capacitive 2.0 1.5 1.0 0.5 0.0 -0.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 Time(ns) Figure 3. Effect of AC Impedance Matching on Rise/Fall Times Revision 1 / December 18, 2002 2 www .semtech.com PE-A2 Optimizing the Output Configuration of Semtech Bipolar Pin Drivers TEST AND MEASUREMENT PRODUCTS This sort of impedance mismatch not only effects the waveform of the signal going to the DUT, but also that of the return signal. These waveform distortions can cause errors in timing, especially when the comparator voltage is set near the high or low voltage levels for measuring rise/fall times or enable/disable times. Since even the best compensation will still be a lumped approximation of a transmission line, every effort should be made to minimize the parasitics in order to achieve the smallest possible waveform distortion. Matching the DCL to the Transmission Line Impedance Correcting for a resistive mismatch simply requires a change in the value of the driver backmatch resistor. Correcting for a capacitive/inductive mismatch requires adding a complementary component into the signal path. For a parasitic capacitance, a series inductor needs to be added. For a parasitic inductance (less common), a parallel capacitance to ground should be added. In Semtech DCL’s, the driver, comparator and load are pinned out separately in order to get the optimum flexibility and performance from the process used to create these parts. When all three functions are used together, the load and comparator pins act as small (~3pF) capacitors which, if uncorrected, will create an impedance mismatch at high frequencies as described above. The idea behind adding series inductance or parallel capacitance is to create a lumped approximation to the continuous series inductance and parallel capacitance of a transmission line. For an ideal 50Ω transmission line, 2.5nh of inductance should be added for each pF of parasitic capacitance or 0.4pF of capacitance should be added for each nh of parasitic inductance. In practice, other imperfections in the transmission line characteristics will cause slightly more inductance (2.6nh/pF – 3.0nh/ pF) or less capacitance (0.33pF/nh – 0.38pF/nh) to be required for optimum compensation. When the Load circuit has a series resistor to match it to 50Ω, the optimum compensation circuit on Semtech’s EVM boards has been found to be as shown in Figure 4. Normally, with two identical (or nearly identical) parasitic capacitors, two identical value inductors would be used. However, the output impedance of the Semtech bipolar drivers is slightly inductive rather than capacitive in nature, so the inductor between the Driver output pin (DOUT) and Load pin is somewhat smaller than the one between the Load and Comparator (VINP) pins. When correcting for multiple parasitics, it is important to remember that one is attempting to approximate a continuous series L-parallel C structure. The best waveforms will be obtained when each parasitic is connected separately to the signal path and each has its own compensating component. For instance, if a PPMU is directly connected to the transmission line for relayless operation, the Force and Sense lines should be connected separately, each with its own compensation inductor. Lumping multiple parasitics to a single point and using a single compensation component saves components, but does a poorer job of approximating a transmission line, so will cause more distortion to the waveforms. This will be worse for faster slew rates and larger parasitic values. Revision 2 25, 2002 1 / July December 18, 2002 3 www .semtech.com PE-A2 Optimizing the Output Configuration of Semtech Bipolar Pin Drivers TEST AND MEASUREMENT PRODUCTS 50Ω VINP DUT Pin Transmission Line 8.2nh 0603 40.2 DCL Part LOAD 0603 3.3nh 0603 46.5 DOUT 0805 Figure 4. External Components for Obtaining DCL AC Performance the overshoot or undershoot as previously shown in Figure 2. It is important that this be done with the fastest rise/fall time signals. At slower rise/fall times the effect of the lumped capacitance will be less making it more difficult to obtain the ideal values for the higher frequency signals. On the other hand, once the high-speed signals are optimized, the lower speed signals will also have their best performance. Optimum inductance values will change somewhat depending on the amount of board parasitic capacitance. The larger the board parasitics, the larger the inductors will need to be. Semtech’s EVM boards typically use 0.014” (0.35mm) thick dielectric in order to minimize the amount of board parasitic capacitance. If thinner dielectric is used in order to get thinner 50Ω transmission line width (often done to get the high board density), the ground plane directly beneath the LOAD and VINP pins and the inductors between the pins can be removed to reduce the parasitic capacitance. Since the DOUT pin is inductive, removing the ground plane underneath this pin and the series resistor will not generally yield much improvement. If only the comparator or load is connected to the driver (but not both), then the inductance of the driver almost perfectly matches the capacitance of the comparator or load pin so the optimum circuit does not need any compensation as shown in Figure 4. If needed, a small series inductor can be added between the Driver output and the VINP or LOAD pin to compensate for the board parasitic capacitance. For different board parasitic capacitances, approximate inductor values can be calculated by using the data sheet values for the comparator and load capacitances (~3.5pF each for the E715C), assuming a Driver inductance of ~5nh and using compensation of 2.5nh/pF inductance for the LOAD pin and VINP pin nodes. If needed, further refinement of these values can be done after the board is assembled by measuring the waveform at the DUT pin using a high-impedance (500Ω or higher) probe and increasing or decreasing the inductor values to remove If only the driver is connected to the transmission line without the comparator or load, then the source impedance will be slightly inductive. To get optimum impedance matching, a parallel capacitor should be connected as shown in Figure 6. 50Ω VINP (or Load) DUT Pin Transmission Line DCL Part 46.5 DOUT 0805 Figure 5. External Components for Obtaining Optimum Performance with Driver-Comparator or Driver-Load Only Connected Revision 1 / December 18, 2002 4 www .semtech.com PE-A2 Optimizing the Output Configuration of Semtech Bipolar Pin Drivers TEST AND MEASUREMENT PRODUCTS 46.5 DOUT DCL Part 0805 50Ω DUT Pin Transmission Line ~3pF Figure 6. External Components for Obtaining Optimum Impedance Matching to a Transmission Line with only the Driver Connected Component Placement Effect of DUT Capacitance Waveform distortion also occurs if the signal travels too far through the external components and traces before being injected into the transmission line, so these external components should be placed as close to the part as possible and the connecting traces should be as short as possible. Since Semtech EVM boards were designed to allow a socket to be used for testing parts, the external components are not always placed as close to the socket as would be possible otherwise. It is recommended that the external resistors and inductors be moved as close as possible to the corresponding DCL pins to minimize the time delay/reflection distortions. The DUT pin often has a parasitic capacitance associated with it which slows down the rise/fall times of the incoming signal. Since this capacitance is usually at the unterminated end of the transmission line, inductor compensation, as described previously, is not useful. Adding an inductor in series at this point will actually increase the amount of waveform distortion rather than decrease it, so this approach is not recommended in this situation. (If the transmission line continues on past the DUT, such as in a fly-by test situation, then using an inductor for compensation can be useful). Placement of the external components can also be improved by using smaller components or smaller pad sizes. For instance, 0603 size inductors are used on Semtech EVM boards in order to make switching components when finding optimum inductor values easier. In a production system where board space is at a premium, 0402 or smaller inductors may be used. Since the external impedance-matching resistors may have to dissipate a significant amount of power, the size of these components cannot usually be reduced significantly. However, it may be possible to reduce the size of the pads beneath these components since boards in ATE systems do not experience the temperature and mechanical stress many other boards experience. For instance, 0805 components can often be installed on 0603 pad sizes, reducing the amount of board space required. The reliability expert at the board assembly house used should be consulted for determining the amount of pad size reduction that can be used in a particular case. When the DUT is at the end of the transmission line, the rise/fall time at the DUT pin is the rise/fall time of the driver in combination with the rise fall time due to the R-C time constant of the 50 ohm transmission line and the parasitic capacitance. Since one R-C time constant is equal to the voltage changing a factor of (1 - 1/e) or 63.2% of the way to the final value, the 10% to 90% transition time is 2.20 times the R-C time constant and the 20% to 80% transition time is 1.39 times the R-C time constant. The transition time at the DUT pin is then: Revision 1 / December 18, 2002 DUT r/f time = (Driver r/f time)2 + (R–C r/f time)2 5 www .semtech.com PE-A2 Optimizing the Output Configuration of Semtech Bipolar Pin Drivers TEST AND MEASUREMENT PRODUCTS For example, if the driver has a 20%-80% rise/fall time of 500ps for a 0.8V pulse, the transmission line impedance is 50Ω and the DUT capacitance is 3pF, then the 20%80% rise/fall time for the R-C time constant of the transmission line and 3pF capacitance is 208ps and the final 20%-80% rise/fall time at the DUT pin will be 542ps. An example of this effect is shown in Figure 7 below. 0.9 0.8 0.7 0.6 0.5 0.4 0pf load 3pf load 5pf load 10pf load 15pf load 22pf load 0.3 0.2 0.1 0.0 -0.1 2.0 3.0 4.0 5.0 6.0 7.0 8.0 Time (ns) Figure 7. Rise/Fall Time Variation with Changing DUT Capacitance Revision 1 / December 18, 2002 6 www .semtech.com