NSC 54ACTQ16374

54ACTQ16374
16-Bit D Flip-Flop with TRI-STATE ® Outputs
General Description
Features
The ’ACTQ16374 contains sixteen non-inverting D flip-flops
with TRI-STATE outputs and is intended for bus oriented applications. The device is byte controlled. A buffered clock
(CP) and Output Enable (OE) are common to each byte and
can be shorted together for full 16-bit operation.
The ’ACTQ16245 utilizes NSC Quiet Series technology to
guarantee quiet output switching and improved dynamic
threshold performance. FACT Quiet Series ® features GTO ®
output control for superior performance.
n Utilizes NSC FACT Quiet Series technology
n Guaranteed simultaneous switching noise level and
dynamic threshold performance
n Buffered Positive edge-triggered clock
n Separate control logic for each byte
n 16-bit version of the ’ACTQ374
n Outputs source/sink 24 mA
n Standard Microcircuit Drawing (SMD) 5962-9452801
Logic Symbol
Connection Diagram
Pin Assignment for
CERPAK
DS010935-1
Pin Description
Pin
Description
Names
OEn
Output Enable Input (Active Low)
CPn
Clock Pulse Input
I0–I15
Inputs
O0–O15
Outputs
DS010935-2
GTO™ is a trademark of National Semiconductor Corporation.
TRI-STATE ® is a registered trademark of National Semiconductor Corporation.
FACT™ and FACT Quiet Series™ are trademarks of Fairchild Semiconductor Corporation.
© 1998 National Semiconductor Corporation
DS010935
www.national.com
54ACTQ16374 16-Bit D Flip-Flop with TRI-STATE Outputs
September 1998
Functional Description
Truth Tables
The ’ACTQ16374 consists of sixteen edge-triggered
flip-flops with individual D-type inputs and TRI-STATE true
outputs. The device is byte controlled with each byte functioning identically, but independent of the other. The control
pins can be shorted together to obtain full 16-bit operation.
Each byte has a buffered clock and buffered Output Enable
common to all flip-flops within that byte. The description
which follows applies to each byte. Each flip-flop will store
the state of their individual D inputs that meet the setup and
hold time requirements on the LOW-to-HIGH Clock (CPn)
transition. With the Output Enable (OE n) LOW, the contents
of the flip-flops are available at the outputs. When OEn is
HIGH, the outputs go to the high impedance state. Operation
of the OEn input does not affect the state of the flip-flops.
Inputs
Outputs
CP1
OE1
I0–I7
O0–O7
N
L
H
H
N
L
L
L
L
L
X
(Previous)
H
X
X
Inputs
Z
Outputs
CP2
OE2
I8–I15
O8–O15
N
L
H
H
N
L
L
L
L
L
X
(Previous)
X
H
X
Z
H = High Voltage Level
L = Low Voltage Level
X = Immaterial
Z = High Impedance
Logic Diagrams
Byte 1 (0:7)
DS010935-3
Byte 2 (8:15)
DS010935-4
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2
Absolute Maximum Ratings (Note 1)
Recommended Operating
Conditions
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (VCC)
DC Input Diode Current (IIK)
VI = −0.5V
VI = VCC + 0.5V
DC Output Diode Current (IOK)
VO = −0.5V
VO = VCC + 0.5V
DC Output Voltage (VO)
DC Output Source/Sink Current (IO)
DC VCC or Ground Current
per Output Pin
Junction Temperature
CDIP
Storage Temperature
Supply Voltage (VCC)
’ACTQ
Input Voltage (VI)
Output Voltage (VO)
Operating Temperature (TA):
54ACTQ
Minimum Input Edge Rate (dV/dt)
’ACTQ Devices
VIN from 0.8V to 2.0V
VCC @ 4.5V, 5.5V
−0.5V to +7.0V
−20 mA
+20 mA
−20 mA
+20 mA
−0.5V to VCC + 0.5V
± 50 mA
4.5V to 5.5V
0V to VCC
0V to VCC
−55˚C to +125˚C
125 mV/ns
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception to ensure that the system design is reliable over its power supply,
temperature, and output/input loading variables. National does not recommend operation of FACT™ circuits outside databook specifications.
± 50 mA
+175˚C
−65˚C to +150˚C
DC Electrical Characteristics for ’ACTQ Family Devices
Symbol
Parameter
54ACTQ
TA = −55˚C
VCC
(V)
Units
Conditions
to +125˚C
Guaranteed Limits
VIH
VIL
VOH
VOL
IOZ
Minimum High
4.5
2.0
Input Voltage
5.5
2.0
Maximum Low
4.5
0.8
Input Voltage
5.5
0.8
Minimum High
4.5
4.4
Output Voltage
5.5
5.4
4.5
3.70
5.5
4.70
Maximum Low
4.5
0.1
Output Voltage
5.5
0.1
Maximum TRI-STATE
V
VOUT = 0.1V
V
or VCC − 0.1V
VOUT = 0.1V
V
or VCC − 0.1V
IOUT = −50 µA
V
(Note 2)
VIN = VIL or VIH
IOH = −24 mA
V
IOH = −24 mA
IOUT = 50 µA
V
(Note 2)
VIN = VIL or VIH
IOL = 24 mA
4.5
0.50
5.5
0.50
5.5
± 10.0
µA
IOL = 24 mA
VI = VIL, VIH
5.5
± 1.0
µA
VO = VCC, GND
VI = VCC, GND
Leakage Current
IIN
Maximum Input
Leakage Current
ICCT
Maximum ICC/Input
5.5
1.6
mA
ICC
Max Quiescent
5.5
160.0
µA
VI = VCC − 2.1V
VIN = VCC
50
mA
or GND (Note 6)
VOLD = 1.65V Max
VOHD = 3.85V Min
Supply Current
IOLD
(Note 3)
Minimum Dynamic
IOHD
Output Current
VOLP
Quiet Output
5.5
50
mA
5.0
0.8
V
5.0
-0.8
V
Maximum Dynamic VOL
VOLV
Quiet Output
(Notes 4, 5)
Minimum Dynamic VOL
(Notes 4, 5)
3
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DC Electrical Characteristics for ’ACTQ Family Devices
(Continued)
Note 2: All outputs loaded; thresholds associated with output under test.
Note 3: Maximum test duration 2.0 ms; one output loaded at a time.
Note 4: Maximum number of outputs that can switch simultaneously is n. (n − 1) outputs are switched LOW and one output held LOW.
Note 5: Maximum number of outputs that can switch simultaneously is n. (n − 1) outputs are switched HIGH and one output held HIGH.
Note 6: ICC for 54ACTQ @ 25˚C is identical to 74ACTQ @ 25˚C.
AC Electrical Characteristics
Symbol
Parameter
VCC
(V)
(Note 7)
54ACTQ
TA =
Units
−55˚C to +125˚C
CL = 50 pF
Min
fmax
Maximum Clock
5.0
Max
65
MHz
Frequency
tPLH,
Propagation Delay
tPHL
CP to On
tPZH,
Output Enable Time
5.0
5.0
tPZL
tPHZ,
Output Disable Time
5.0
tPLZ
3.0
10.5
3.0
10.5
3.0
10.5
3.0
11.5
2.0
9.0
2.0
9.0
ns
ns
ns
Note 7: Voltage Range 5.0 is 5.0V ± 0.5V.
AC Operating Requirements
Symbol
Parameter
VCC
(V)
(Note 8)
54ACTQ
TA =
Units
−55˚C to +125˚C
CL = 50 pF
Guaranteed Limits
tS
Setup Time, HIGH or
5.0
3.0
ns
5.0
1.0
ns
5.0
5.0
ns
LOW, Input to Clock
tH
Hold Time, High or
LOW, Input to Clock
tW
CP Pulse Width,
HIGH or LOW
Note 8: Voltage Range 5.0 is 5.0V ± 0.5V.
Capacitance
Symbol
Typ
Units
CIN
Input Capacitance
Parameter
4.5
pF
CPD
Power Dissipation
95
pF
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4
Conditions
VCC = 5.0V
VCC = 5.0V
5
54ACTQ16374 16-Bit D Flip-Flop with TRI-STATE Outputs
Physical Dimensions
inches (millimeters) unless otherwise noted
48-Lead CERPAK
NS Package Number WA48A
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