19-4569; Rev 1; 6/10 WHB࣡ాۣઐ ``````````````````````````````````` ᄂቶ NBY59:6Fૹ߅࢟ຳᓞધદߡLjᆐWHBቧᄋSĂHĂ C࣡ాۣઐă ♦ I2ĂW2ĂTEB2ĂTDM2ĂSĂHĂC࣡ᎌFTEۣઐ ±26lW—ཽᄏෝါ ±9lW—JFD! 72111.5.3Lj߿ह࢟ NBY59:6FᎌIĂW )ቲĂ࢟*ޝຳᓞધદߡLjభᔈ ᅄተၒ߲ࡼࢅ࢟ຳDNPTၒྜྷᓞધ߅൸ᔗ,6/1WĂUUMରྏ ࢟ຳࡼၒ߲ăඛവၒ߲భᄋ±21nBདࣅLj൸ᔗWFTB® ਖपăࠥᅪLjୈથభ၊,6/1WĂᒇၫᔊ఼ᒜ)EED* ቧLj݀ᓞધᆐᅄተୈჅኊࡼ୷ࢅ࢟ຳăઓభ ᅄተఌၒ߲࢟ᏎೌᒗW M ࢾক࢟ຳăSĂHĂCۣ࣡ઐ ᅄተၒ߲୭Ljဧ၊ஸ࢟ह࢟)FTE*ߡૣऎႼડLj໕വ ၒ߲ᎌኹFTEۣઐă ♦ ࢅஸზ࢟ഗLjJR ≤ 6μB! )ᔢࡍᒋ* ♦ 4qG! )ᔢࡍᒋ*ࢅ࢟ྏ)SĂHĂC࣡ా* ♦ EED࢟ຳᓞધۣઐᎧಭ ♦ ቲᄴݛĂޝᄴ࢟ݛຳᓞધ0દߡ ♦ ၒྜྷରྏ᎖WM ♦ ၒ߲ରྏ᎖,6/1W! UUM࢟ຳ)९WFTB* NBY59:6FᔫᏴ.51°Dᒗ,96°D౫ᐱᆨࣞपᆍLjᄋ27 ୭Ă4nn y 4nn URGOॖᓤă ♦ ඛৈIĂW࣡ాభᄋ±21nBདࣅ ``````````````````````````````````` ። ``````````````````````````````` ࢾ৪ቧᇦ ♦ ஂဏహମࡼ27୭)4nn! y! 4nn*! URGOᇄॖᓤ ܊࢟۾ฎ PART გါଐႯ૦ MAX4895EETE+ ॲᇗ TEMP RANGE PIN-PACKAGE -40°C to +85°C 16 TQFN-EP* ,ܭာᇄ)Qc*0९SpITܪᓰࡼॖᓤă *FQ! >! ൡă ᅄተఌ WFTBဵ၁ຫ࢟ᔇܪᓰ્ࡼᓖॲݿᇗܪᒔă ```````````````````````````````````````````````````````````````````````` ࢜ቯᔫ࢟വ +3.3V +5V 1μF 1μF VL VCC EN VGA OUTPUTS 2 2 H0, V0 MAX4895E H1, V1 SDA1, SCL1 SDA0, SCL0 2 VGA PORT 2 R G B N.C. GND ________________________________________________________________ Maxim Integrated Products 1 ۾ᆪဵ፞ᆪၫᓾ೯ࡼፉᆪLjᆪᒦభถࡀᏴडፉࡼݙᓰཀྵࡇᇙăྙኊጙݛཀྵཱྀLj༿Ᏼิࡼଐᒦݬఠ፞ᆪᓾ೯ă ᎌਈଥৃĂૡૺࢿ৪ቧᇦLj༿ೊNbyjnᒴሾ၉ᒦቦǖ21911!963!235:!)۱ᒦਪཌ*Lj21911!263!235:!)ฉᒦਪཌ*Lj षᆰNbyjnࡼᒦᆪᆀᐶǖdijob/nbyjn.jd/dpnă NBY59:6F ``````````````````````````````````` গၤ NBY59:6F WHB࣡ాۣઐ ABSOLUTE MAXIMUM RATINGS (All voltages referenced to GND.) VCC ........................................................................-0.3V to +6.0V VL .............................................................-0.3V to +(VCC + 0.3V) R, G, B, H1, V1, SCL1, SDA1...................-0.3V to +(VCC + 0.3V) EN, H0, V0, SCL0, SDA0 ............................-0.3V to +(VL + 0.3V) Continuous Current through SDA_, SCL_.........................±30mA Continuous Short-Circuit Current H1, V1..........................±20mA Continuous Power Dissipation (TA = +70°C) for multilayer board: 16-Pin TQFN (derate 20.8mW/°C above +70°C) .......1667mW Junction-to-Case Thermal Resistance (θJC) (Note 1) ......7°C/W Junction-to-Ambient Thermal Resistance (θJA) (Note 1) ........................................................................48°C/W Operating Temperature Range ...........................-40°C to +85°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Soldering Temperature (reflow) .......................................+260°C Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a fourlayer board. For detailed information on package thermal considerations, refer to china.maxim-ic.com/thermal-tutorial. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VCC = +4.5V to +5.5V, VL = +2.0V to VCC, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VCC = +5.0V, VL = +3.3V, and TA = +25°C.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 5.5 V 3.3 5.5 V SUPPLY OPERATION Supply Voltage VCC 4.5 Logic Supply Voltage VL VL VCC VCC Supply Current ICC VH0, VV0 = 0V, VEN = VL 0.5 5.0 μA IL VH0, VV0 = 0V, VEN = VL (no load) 0.5 5.0 μA C OUT f = 1MHz, VR,G,B = 1V P-P (Note 3) 2.2 VL Supply Current 2 RGB CHANNELS R, G, B Capacitance R, G, B Leakage VCC = +5.5V -1 pF +1 μA 0.8 V H_, V_, EN CHANNELS Input Threshold Low VIL VL = +3.0V Input Threshold High VIH VL = +3.6V Input Hysteresis VHYST Input Leakage Current ILEAK V 100 VL = +3.3V, VCC = +5.5V Output-Voltage Low VOL I OUT = 10mA sink, VCC = +4.5V Output-Voltage High VOH I OUT = 10mA source, VCC = +4.5V Propagation Delay t PD RL = 2.2k, CL = 10pF, VOL = +0.8V, VOH = +2.4V Enable Time 2.0 -1 mV +1 μA 0.8 V 2.4 t ON, t OFF V 15 ns 15 ns SDA_, SCL_ (DDC) CHANNELS On-Resistance, SDA, SCL R ON VCC = +5.5V, I SDA, SCL = ±10mA, VSDA, SCL = +0.5V Leakage Current, SDA, SCL ILEAK VL = 0V 2 20 -1 _______________________________________________________________________________________ 55 +1 μA WHB࣡ాۣઐ (VCC = +4.5V to +5.5V, VL = +2.0V to VCC, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VCC = +5.0V, VL = +3.3V, and TA = +25°C.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS ESD PROTECTION SDA1, SCL1, H1, V1, R, G, B Human Body Model (Note 4) SDA1, SCL1, H1, V1, R, G, B IEC 61000-4-2 Contact ±15 kV ±8 kV Note 2: All devices are 100% production tested at TA = +25°C. All temperature limits are guaranteed by design. Note 3: Guaranteed by design, not production tested. Note 4: Tested terminals to GND; 1μF bypass capacitors on VCC and VL. ``````````````````````````````````````````````````````````````````````````` ࢜ቯᔫᄂቶ (VCC = +5.0V, VL = +3.3V, and TA = +25°C, unless otherwise noted.) 6.0 MAX4895E toc01 60 SDA0, SCL0 ARE INTERCHANGEABLE IOUT = 8mA OUTPUT VOLTAGE (V) RON (Ω) 45 VL = +3.3V 30 TA = +85°C 15 TA = +25°C VL = +5V TA = -40°C TA = +85°C MAX4895E toc02 HV BUFFER OUTPUT-VOLTAGE HIGH vs. TEMPERATURE RON vs. VSDA0 5.5 5.0 4.5 TA = +25°C TA = -40°C 0 4.0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 -40 -15 VSDA0 (V) 10 35 60 85 TEMPERATURE (°C) 1.0 IOUT = 8mA OUTPUT VOLTAGE (V) 0.8 MAX4895E toc03 HV BUFFER OUTPUT-VOLTAGE LOW vs. TEMPERATURE 0.6 0.4 0.2 0 -40 -15 10 35 60 85 TEMPERATURE (°C) _______________________________________________________________________________________ 3 NBY59:6F ELECTRICAL CHARACTERISTICS (continued) ``````````````````````````````````````````````````````````````````````````````` ୭ᒙ H1 H0 SCL1 SCL0 TOP VIEW 12 11 10 9 V0 13 V1 14 MAX4895E VCC 15 EP 2 3 4 GND 1 B + G EN 16 R NBY59:6F WHB࣡ాۣઐ 8 SDA1 7 SDA0 6 N.C. 5 VL TQFN (3mm × 3mm) ``````````````````````````````````````````````````````````````````````````` ୭ႁී 4 ୭ ߂ 1 R ᎖ۣઐSHCቧࡼኹFTEۣઐऔă ถ 2 G ᎖ۣઐSHCቧࡼኹFTEۣઐऔă 3 B ᎖ۣઐSHCቧࡼኹFTEۣઐऔă 4 GND ă ࢟Ꮞ࢟ኹLj,3/1WᒗWDDăᄰਭጙৈ2μGࡼჿࠣ࢟ྏWM വᒗHOEă 5 VL 6 N.C. ᎌೌLjॳహă 7 SDA0 TEB! J0PLjTEB1ጲWM ᆐݬఠă 8 SDA1 TEB! J0PLjTEB2ጲWDD ᆐݬఠă 9 SCL0 TDM! J0PLjTDM1ጲWM ᆐݬఠă 10 SCL1 TDM! J0PLjTDM2ጲWDD ᆐݬఠă 11 H0 12 H1 ቲᄴݛၒ߲ă 13 V0 ޝᄴݛၒྜྷă 14 V1 ޝᄴݛၒ߲ă 15 VCC ࢟Ꮞ࢟ኹLj,5/6Wᒗ,6/6Wăᄰਭጙৈ2μGࡼჿࠣ࢟ྏWDD വᒗHOEă 16 EN I2ਜ਼W2ၒ߲ဧถă — EP ൡLjFQೌࡵHOEॳహăᆐখ࿖ྲེLj።কFQೌࡵభถࡍࡼᄵཌᎮăݙገFQᔫᆐ ᆎጙࡼೌ࣡ă ቲᄴݛၒྜྷă _______________________________________________________________________________________ WHB࣡ాۣઐ VL VCC SDA1 ±15kV SDA0 CLAMP SCL0 ±15kV SCL1 H1 ±15kV H0 EN V1 ±15kV V0 B ±15kV MAX4895E G ±15kV ±15kV R GND ``````````````````````````````` ።ቧᇦ NBY59:6Fᄋܘገࡼ࢟ຳᓞધLj᎖དࣅೝവܪᓰWHB ࣡ాLjၒྜྷቧᔈᅄተ఼ᒜLj࢟ኹభࢅᒗ,3/3Wăด ݝદߡITZODਜ਼WTZODቧདࣅᒗWHBܪᓰࡼUUM ࢟ຳăEEDఎਈቧὥᆡᏴࢅ᎖WM ጙৈऔኹଢ଼ࡼ ࢟ኹᒋLjᄋ࢟ຳᓞધ)ݬ࢜ቯᔫ࢟വ*ăᑵޟᔫဟLj WM ೌᒗ,4/4Wă ࢟ᏎབྷẮ ಽ2μGჿࠣ࢟ྏॊܰWDD ਜ਼WM വᒗLj࢟ྏ።భ ถణதୈڔᓤă QDCݚ ᆐࡻᔢଛቶถLjNBY59:6FႥఎਈኍݧಯࡼQDC ݚăཀྵۣႥቧݧᔜఝ၊఼ࡼQDCሣLjཀྵۣሣ ࣞޠጙᒘ݀భถăൡೌࡵށă _______________________________________________________________________________________ 5 NBY59:6F ```````````````````````````````````````````````````````````````````````````` ถౖᅄ NBY59:6F WHB࣡ాۣઐ ``````````````````````````````` ሮᇼႁී NBY59:6Fૹ߅࢟ຳᓞધદߡLjᆐWHBቧᄋSĂHĂ C࣡ాۣઐă ቲᄴݛਜ਼ޝᄴ)ݛI10W1*ၒྜྷᎌ࢟ຳᓞધદߡLjᑽߒ ࢅ࢟ኹDNPTܪᓰࡼUUMରྏᅄተ఼ᒜăকୈ൸ᔗ ±21nB! WFTBདࣅገཇăNBY59:6FݧೝৈoNPTୈ થభᄋJ3D࢟ຳᓞધă໕ৈ࣡ా)TEB2ĂTDM2ĂI2ĂW2Ă SĂHĂC*ࡼჅᎌၒ߲భߌ၊±26lWཽᄏෝါ)ICN*ጲૺ ±9lW! JFD! 72111.5.3߿ह࢟ࡼஸ࢟ߡૣăSĂHĂC࣡ా ᆐၫ0ෝᓞધ)EBD*ᄋۣઐLjᒑኊ଼݀ೊᏴEBDਜ਼ WHBࡼݹރSĂHĂCၒ߲ă ቲ0ޝᄴ࢟ݛຳᓞધ ITZOD0WTZODቧளਭદߡᄋ࢟ຳᓞધLjདࣅถೆ൸ ᔗWFTBਖपገཇăၒྜྷ൝࢟ຳ)WJMĂWJI*ೌᒗWM )ݬ Fmfdusjdbm Dibsbdufsjtujdt *ܭăࡩFOདࣅᒗࢅ࢟ຳဟLjள ࢟ຳᓞધઁࡼၒ߲)I2ਜ਼W2*ۻ౯ࢅ)ܭ2*ă൝࢟ຳၒ߲ )WPMĂWPI*ରྏ᎖,6/1W UUM࢟ຳă ܭ2/! IWᑞᒋܭ EN FUNCTION 1 HSYNC/VSYNC level shifting enabled 0 H1, V1 = 0 መာၫᄰࡸఎਈ NBY59:6FಽೝৈoNPTఎਈဣሚJ3D࢟ຳᓞધăTEBĂ TDM࣡࢟ኹὥᆡࡵࢅ᎖W M ጙৈऔኹଢ଼ࡼ࢟ኹᒋă࢟ ኹὥᆡᄋۣઐ݀ରྏ᎖TEBĂTDMਜ਼ࢅኹBTJD൝࢟ຳă WM ݧ,3/6Wᒗ,4/4W࢟࢟ᏎLj࢟ኹὥᆡࡵରྏ᎖WFTB J3Dቧࡼ࢟ຳăTEBĂTDMఎਈሤᄴLjඛৈఎਈ᎖༤ધ TEBTDMቧă SHC ୈᎌSĂHĂCྯৈ࢛࣡ăᑚቋ࢛࣡ࡼᆎጙᔫဵᏴۣ ߒSHCቧሣ࢟ྏᔢቃࡼ༄ᄋሆLjᆐᄋኹFTEۣઐă SĂHĂC࣡ᎌሤᄴஉ৩Ljྀੜጙৈ࣒భጲ᎖ۣઐĂ ൊĂ౸၁ຫቧă FTEۣઐ ᎧNbyjnࡼୈಢ႒LjୈࡼჅᎌ୭࣒ᄋFTEۣ ઐஉ৩LjᏴݷᔫᎧᓤਭ߈ᒦ߲ሚஸ࢟ह࢟ဟభ࣪ୈ ᄋۣઐăᅪLjNBY59:6FᏴSHC࣡ਜ਼I2ĂW2ĂTEB2Ă TDM2ၒ߲࣡ᄋ±26lWཽᄏෝါ)ICN*ஸۣ࢟ઐăᆐࡻ ᔢଛࡼFTEۣઐቶถLjಽ2μGჿࠣ࢟ྏWDD വᒗă FTEۣઐభጲݧݙᄴࡼऱजހ၂ăNBY59:6FࡼSĂHĂ C࣡ጲૺ I2ĂW2ĂTEB2ĂTDM2ၒ߲࣡ࡼۣઐถೆ၊ሢ᎖ǖ • ±26lWཽᄏෝါ • ±9lW! JFD! 72111.5.3߿ह࢟ ܭ3/! EEDᑞᒋܭ 6 FTEހ၂ᄟୈ EN FUNCTION 1 SDA0 to SDA1 SCL0 to SCL1 0 SDA1, SCL1, high impedance FTEቶถན᎖ࣶᒬᄟୈăྙਫኊገ۞౪ހ၂ᒙĂऱज ਜ਼உਫᏴดࡼభణቶۨসLj༿ᎧNbyjnೊᇹă _______________________________________________________________________________________ WHB࣡ాۣઐ CHARGE-CURRENTLIMIT RESISTOR DISCHARGE RESISTANCE CHARGE-CURRENTLIMIT RESISTOR HIGHVOLTAGE DC SOURCE RC 50MΩ TO 100MΩ RD 1500Ω Cs 100pF DEVICE UNDER TEST STORAGE CAPACITOR HIGHVOLTAGE DC SOURCE Cs 150pF NBY59:6F RC 1MΩ RD 330Ω DISCHARGE RESISTANCE STORAGE CAPACITOR DEVICE UNDER TEST ᅄ2d/! JFD! 72111.5.3! FTEހ၂ෝቯ ᅄ2b/! ཽᄏෝါFTEހ၂ෝቯ IP 100% 90% I 100% 90% PEAK-TO-PEAK RINGING (NOT DRAWN TO SCALE) IPEAK Ir AMPS 36.8% 10% 0 10% 0 tRL TIME tr = 0.7ns TO 1ns tDL CURRENT WAVEFORM t 30ns 60ns ᅄ2e/! JFD! 72111.5.3! FTEखည࢟ഗ݆ተ ᅄ2c/! ཽᄏෝါހ၂࢟ഗ݆ተ ཽᄏෝါ)ICN* ᅄ2bჅာᆐཽᄏෝါހ၂ෝቯLjᅄ2cჅာᆐ࣪ࢅᔜह࢟ ဟޘညࡼ࢟ഗ݆ተăকෝቯ۞౪ጙৈ211qG࢟ྏLjߠ ࢟ᒗჅገཇࡼFTE࢟ኹLjઁᄰਭ2/6lΩ࢟ᔜሶހۻୈ ह࢟ă JFD! 72111.5.3 JFD! 72111.5.3ܪᓰঙ೫߅ອ۸ࡼFTEހ၂ᎧቶถLjࡣ ݀ݙᑣ࣪ૹ߅࢟വăNBY59:6Fถ৫ۑᓐઓଐ९ JFD! 72111.5.3ገཇࡼ۸LjऎݙኊገऄᅪࡼFTEۣઐᏄୈă ဧཽᄏෝါᎧJFD! 72111.5.3ހ၂ࡼᓍገཌܰᏴ᎖JFD 72111.5.3ހ၂ࡼख़ᒋ࢟ഗৎLjᑚဵᎅ᎖JFD! 72111.5.3ෝ ቯݧৎቃࡼࠈೊ࢟ᔜăፐࠥLjJFD! 72111.5.3ހ၂ࡼFTE ง၊࢟ኹᄰࢅޟ᎖ཽᄏෝါހ၂ࡼஉਫăᅄ2dჅာᆐJFD 72111.5.3ހ၂ෝቯLjᅄ2eჅာᆐJFD 72111.5.3 FTE߿ह ࢟ހ၂ࡼ࢟ഗ݆ተă ``````````````````````````````` በຢቧᇦ PROCESS: BiCMOS ``````````````````````````````` ॖᓤቧᇦ ྙኊᔢதࡼॖᓤᅪተቧᇦਜ਼ݚLj༿އኯ china.maxim-ic. com/packagesă༿ᓖፀLjॖᓤܠ൩ᒦࡼĐ,đĂĐ$đĐ.đஞܭာ SpITᓨზăॖᓤᅄᒦభถ۞ݙᄴࡼᆘᓮᔊ९LjࡣॖᓤᅄᒑᎧॖ ᓤᎌਈLjᎧSpITᓨზᇄਈă ॖᓤಢቯ ॖᓤܠ൩ ᅪተܠ ݚܠ 16 TQFN-EP T1633+4 21-0136 90-0031 _______________________________________________________________________________________ 7 NBY59:6F WHB࣡ాۣઐ ```````````````````````````````````````````````````````````````````````````` ኀࢿ಼ဥ ኀࢿ ኀࢿ྇໐ ႁී 0 4/09 ᔢ߱۾ۈă — 1 6/10 ࠭ࢾ৪ቧᇦᒦ࿎߹೫Đࢻܪđጙ౺ă 1 ኀখ Nbyjn ۱யࠀူێ ۱ய 9439ቧረ ᎆᑶܠ൩ 211194 ॅ࢟જǖ911!921!1421 ࢟જǖ121.7322 62:: ࠅᑞǖ121.7322 63:: Nbyjn࣪ݙNbyjnޘອጲᅪࡼྀੜ࢟വဧঌᐊLjጐݙᄋᓜಽభăNbyjnۣഔᏴྀੜဟମĂᎌྀੜᄰۨࡼ༄ᄋሆኀখޘອᓾ೯ਜ਼ਖৃࡼཚಽă 8 ______________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2010 Maxim Integrated Products Nbyjn ဵ Nbyjn!Joufhsbufe!Qspevdut-!Jod/ ࡼᓖݿܪă MAX4895E VGA端口保护 - 概述 ENGLISH • 简体中文 • 日本語 • 한국어 • РУССКИЙ Login | Register 最新内容 产品 方案 设计 应用 技术支持 销售联络 公司简介 Maxim > 产品 > 模拟开关和多路复用器 > MAX4895E MAX4895E VGA端口保护 为R、G、B终端提供电平转换缓冲和ESD端口保护 概述 技术文档 定购信息 相关产品 用户说明 (0) 所有内容 状况 状况：生产中。 概述 数据资料 MAX4895E集成电平转换缓冲器，为VGA信号提供R、G、B端口保护。 MAX4895E具有H、V (行、场)电平转换缓冲器，可将来自图形输出的低电平CMOS输入转换成满足 全+5.0V、TTL兼容的输出。每路输出可提供±10mA驱动，满足VESA®规范。此外，器件还可接 受+5.0V、直接数字控制(DDC)信号，并将其转换为图形器件所需的较低电平。用户将图形输出电源连 接至VL 设定该电平。R、G、B端保护图形输出引脚免受静电(ESD)冲击而损坏，七路输出均具有高 压ESD保护。 完整的数据资料 英文 下载 Rev. 1 (PDF, 152kB) 中文 下载 Rev. 1 (PDF, 596kB) MAX4895E工作在扩展级-40°C至+85°C温度范围，提供16引脚、3mm x 3mm TQFN封装。 关键特性 H1、V1、SDA1、SCL1、R、G、B端带有ESD保护 ±15kV—人体模型 ±8kV—IEC 61000-4-2、接触放电 低静态电流，IQ ≤ 5µA (最大值) 电容低至3pF (最大值) (R、G、B端口) DDC电平转换保护和隔离 行同步、场同步电平转换/缓冲 输入与VL 兼容 输出完全兼容于+5.0V TTL (符合VESA标准) 每个H、V端口可提供±10mA驱动 节省空间、无铅、16引脚(3mm x 3mm) TQFN封装 图表 典型工作电路 http://china.maxim-ic.com/datasheet/index.mvp/id/5775[2010-12-15 7:43:18] 应用/使用 台式计算机 图形卡 笔记本电脑 服务器 我的Maxim MAX4895E VGA端口保护 - 概述 更多信息 顶标 MAX4895E 新品发布 [ 2009-09-21 ] 没有找到你需要的产品吗？ 应用工程师帮助选型，下个工作日回复 参数搜索 应用帮助 概述 技术文档 定购信息 相关产品 概述 关键特性 应用/ 使用 关键指标 图表 注释、注解 数据资料 应用笔记 评估板 设计指南 可靠性报告 软件/ 模型 价格与供货 样品 在线订购 封装信息 无铅信息 类似功能器件 类似应用器件 评估板 类似型号器件 配合该器件使用的产品 参考文献： 19- 4569 Rev. 1; 2010- 07- 12 本页最后一次更新: 2010- 07- 12 联络我们：信息反馈、提出问题 • 对该网页的评价 • 发送本网页 • 隐私权政策 • 法律声明 © 2010 Maxim Integrated Products版权所有 http://china.maxim-ic.com/datasheet/index.mvp/id/5775[2010-12-15 7:43:18] 19-4569; Rev 1; 6/10 VGA Port Protector Features The MAX4895E integrates level-translating buffers and features R, G, B port protection for VGA signals. ♦ ESD Protection on H1, V1, SDA1, SCL1, R, G, and B ±15kV—Human Body Model The MAX4895E has H, V (horizontal, vertical) translating buffers that take low-level CMOS inputs from the graphics outputs to meet full +5.0V, TTL-compatible outputs. Each output can drive ±10mA and meet the VESA® specification. In addition, the device takes the +5.0V, direct digital control (DDC) signals and translates them to the lower level required by the graphics device. This level is set by the user by connecting VL to the graphics output supply. The R, G, B terminals protect the graphics output pins against electrostatic discharge (ESD) events. All seven outputs have high-level ESD protection. ±8kV—IEC 61000-4-2, Contact Discharge ♦ Low Quiescent Current, IQ ≤ 5µA (max) ♦ Low 3pF (max) Capacitance (R, G, B Ports) ♦ DDC Level-Shifting Protection and Isolation ♦ Horizontal Sync, Vertical Sync Level Shifting/ Buffering ♦ Input Compatible with VL The MAX4895E is specified over the extended -40°C to +85°C temperature range, and is available in a 16-pin, 3mm x 3mm TQFN package. ♦ Output Full +5.0V TTL Compatible (per VESA) ♦ ±10mA Drive on Each H, V Terminal Applications ♦ Space-Saving, Lead-Free, 16-Pin (3mm x 3mm) TQFN Package Notebook Computers Desktops Ordering Information Servers PART Graphics Cards MAX4895EETE+ TEMP RANGE PIN-PACKAGE -40°C to +85°C 16 TQFN-EP* +Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad. VESA is a registered service mark of Video Electronics Standards Association Corporation. Typical Operating Circuit +3.3V +5V 1μF 1μF VL VCC EN VGA OUTPUTS 2 2 H0, V0 MAX4895E SDA0, SCL0 H1, V1 SDA1, SCL1 2 VGA PORT 2 R G B N.C. GND ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX4895E General Description MAX4895E VGA Port Protector ABSOLUTE MAXIMUM RATINGS (All voltages referenced to GND.) VCC ........................................................................-0.3V to +6.0V VL .............................................................-0.3V to +(VCC + 0.3V) R, G, B, H1, V1, SCL1, SDA1...................-0.3V to +(VCC + 0.3V) EN, H0, V0, SCL0, SDA0 ............................-0.3V to +(VL + 0.3V) Continuous Current through SDA_, SCL_.........................±30mA Continuous Short-Circuit Current H1, V1..........................±20mA Continuous Power Dissipation (TA = +70°C) for multilayer board: 16-Pin TQFN (derate 20.8mW/°C above +70°C) .......1667mW Junction-to-Case Thermal Resistance (θJC) (Note 1) ......7°C/W Junction-to-Ambient Thermal Resistance (θJA) (Note 1) ........................................................................48°C/W Operating Temperature Range ...........................-40°C to +85°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Soldering Temperature (reflow) .......................................+260°C Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a fourlayer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VCC = +4.5V to +5.5V, VL = +2.0V to VCC, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VCC = +5.0V, VL = +3.3V, and TA = +25°C.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 5.5 V SUPPLY OPERATION Supply Voltage VCC 4.5 Logic Supply Voltage VL VL VCC 3.3 5.5 V VCC Supply Current ICC VH0, VV0 = 0V, VEN = VL 0.5 5.0 μA IL VH0, VV0 = 0V, VEN = VL (no load) 0.5 5.0 μA C OUT f = 1MHz, VR,G,B = 1V P-P (Note 3) 2.2 VL Supply Current 2 RGB CHANNELS R, G, B Capacitance R, G, B Leakage VCC = +5.5V -1 pF +1 μA 0.8 V H_, V_, EN CHANNELS Input Threshold Low VIL VL = +3.0V Input Threshold High VIH VL = +3.6V Input Hysteresis VHYST Input Leakage Current ILEAK V 100 VL = +3.3V, VCC = +5.5V Output-Voltage Low VOL I OUT = 10mA sink, VCC = +4.5V Output-Voltage High VOH I OUT = 10mA source, VCC = +4.5V Propagation Delay t PD RL = 2.2k, CL = 10pF, VOL = +0.8V, VOH = +2.4V Enable Time 2.0 -1 mV +1 μA 0.8 V 2.4 t ON, t OFF V 15 ns 15 ns SDA_, SCL_ (DDC) CHANNELS On-Resistance, SDA, SCL R ON VCC = +5.5V, I SDA, SCL = ±10mA, VSDA, SCL = +0.5V Leakage Current, SDA, SCL ILEAK VL = 0V 2 20 -1 _______________________________________________________________________________________ 55 +1 μA VGA Port Protector (VCC = +4.5V to +5.5V, VL = +2.0V to VCC, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VCC = +5.0V, VL = +3.3V, and TA = +25°C.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS ESD PROTECTION SDA1, SCL1, H1, V1, R, G, B Human Body Model (Note 4) SDA1, SCL1, H1, V1, R, G, B IEC 61000-4-2 Contact ±15 kV ±8 kV Note 2: All devices are 100% production tested at TA = +25°C. All temperature limits are guaranteed by design. Note 3: Guaranteed by design, not production tested. Note 4: Tested terminals to GND; 1µF bypass capacitors on VCC and VL. Typical Operating Characteristics (VCC = +5.0V, VL = +3.3V, and TA = +25°C, unless otherwise noted.) 6.0 MAX4895E toc01 60 SDA0, SCL0 ARE INTERCHANGEABLE IOUT = 8mA OUTPUT VOLTAGE (V) RON (Ω) 45 VL = +3.3V 30 TA = +85°C 15 TA = +25°C VL = +5V TA = -40°C TA = +85°C MAX4895E toc02 HV BUFFER OUTPUT-VOLTAGE HIGH vs. TEMPERATURE RON vs. VSDA0 5.5 5.0 4.5 TA = +25°C TA = -40°C 0 4.0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 -40 -15 VSDA0 (V) 10 35 60 85 TEMPERATURE (°C) 1.0 IOUT = 8mA OUTPUT VOLTAGE (V) 0.8 MAX4895E toc03 HV BUFFER OUTPUT-VOLTAGE LOW vs. TEMPERATURE 0.6 0.4 0.2 0 -40 -15 10 35 60 85 TEMPERATURE (°C) _______________________________________________________________________________________ 3 MAX4895E ELECTRICAL CHARACTERISTICS (continued) VGA Port Protector MAX4895E Pin Configuration H1 H0 SCL1 SCL0 TOP VIEW 12 11 10 9 V0 13 8 SDA1 V1 14 7 SDA0 6 N.C. 5 VL MAX4895E VCC 15 EP 2 3 4 GND R 1 B + G EN 16 TQFN (3mm × 3mm) Pin Description PIN 4 NAME FUNCTION 1 R High-ESD Protection Diodes for RGB Signals 2 G High-ESD Protection Diodes for RGB Signals 3 B High-ESD Protection Diodes for RGB Signals 4 GND 5 VL 6 N.C. No Connection. Leave unconnected. 7 SDA0 SDA I/O. SDA0 referenced to VL. 8 SDA1 SDA I/O. SDA1 referenced to VCC. 9 SCL0 SCL I/O. SCL0 referenced to VL. 10 SCL1 11 H0 Horizontal Sync Input 12 H1 Horizontal Sync Output 13 V0 Vertical Sync Input 14 V1 Vertical Sync Output 15 VCC 16 EN — EP Ground Supply Voltage, +2.0V to VCC. Bypass VL to GND with a 1μF ceramic capacitor. SCL I/O. SCL1 referenced to VCC. Power-Supply Voltage, +4.5V to +5.5V. Bypass VCC to GND with a 1μF ceramic capacitor. Enable for H1 and V1 Outputs Exposed Pad. Connect EP to GND or leave unconnected. For enhanced thermal dissipation, connect EP to a copper area as large as possible. Do not use EP as a sole ground connection. _______________________________________________________________________________________ VGA Port Protector VL VCC SDA1 ±15kV SDA0 CLAMP SCL0 ±15kV SCL1 H1 ±15kV H0 EN V1 ±15kV V0 B ±15kV MAX4895E G ±15kV ±15kV R GND Applications Information The MAX4895E provides the level shifting necessary to drive two standard VGA ports from a graphics controller as low as +2.2V. Internal buffers drive the HSYNC and VSYNC signals to VGA standard TTL levels. The DDC switch provides level shifting by clamping signals to a diode drop less than VL (see the Typical Operating Circuit). Connect VL to +3.3V for normal operation. Power-Supply Decoupling Bypass V CC and V L to ground with a 1µF ceramic capacitor as close as possible to the device. PCB Layout High-speed switches such as the MAX4895E require proper PCB layout for optimum performance. Ensure that impedance-controlled PCB traces for high-speed signals are matched in length and are as short as possible. Connect the exposed pad to a solid ground plane. _______________________________________________________________________________________ 5 MAX4895E Functional Diagram MAX4895E VGA Port Protector Detailed Description The MAX4895E integrates level-translating buffers and features R, G, B port protection for VGA signals. Horizontal and vertical synchronization (H0/V0) inputs feature level-shifting buffers to support low-voltage CMOS or standard TTL-compatible graphics controllers. The device meets ±10mA VESA drive requirements. The MAX4895E also features I2C level shifting using two nMOS devices. All outputs maintain ±15kV Human Body Model (HBM) and ±8kV Contact Discharge per IEC 61000-4-2 on seven terminals (SDA1, SCL1, H1, V1, R, G, B). The R, G, B pads protect the digital-to-analog converter (DAC) and are simply placed in parallel with the R, G, B outputs for the DAC and VGA socket. Horizontal/Vertical Sync Level Shifter HSYNC/VSYNC are buffered to provide level shifting and drive capability to meet the VESA specification. Input logic levels (VIL, VIH) are connected to VL (see the Electrical Characteristics table). The level-shifted outputs (H1 and V1) are pulled low when EN is driven low (see Table 1). Logic-level output (VOL, VOH) are +5.0V TTL compatible. Table 1. HV Truth Table EN FUNCTION 1 HSYNC/VSYNC level shifting enabled 0 H1, V1 = 0 Table 2. DDC Truth Table 6 EN FUNCTION 1 SDA0 to SDA1 SCL0 to SCL1 0 SDA1, SCL1, high impedance Display Data Channel Switches The MAX4895E incorporates two nMOS switches for I2C level shifting. The SDA, SCL terminals are voltage clamped to a diode drop less than the V L voltage. Voltage clamping provides protection and compatibility with SDA, SCL signals and low-voltage ASICs. Supply +2.5V to +3.3V on VL to provide voltage clamping for VESA I2C-compatible signals. The SDA, SCL switches are identical, and each switch can be used to route SDA or SCL signals. RGB There are three terminals for R, G, and B. The only function of these terminals is to provide high-level ESD protection to the RGB lines, while at the same time, keeping the capacitance on the RGB lines to a minimum. The R, G, B terminals are identical, and any of the three terminals can be used to protect red, green, or blue video signals. ESD Protection As with all Maxim devices, ESD-protection structures are incorporated on all terminals to protect against electrostatic discharges encountered during handling and assembly. Additionally, the MAX4895E is protected to ±15kV on the RGB terminals and outputs H1, V1, SDA1, and SCL1 by the Human Body Model (HBM). For optimum ESD performance, bypass VCC to ground with a 1µF ceramic capacitor. ESD protection can be tested in various ways. The R, G, B terminals and outputs H1, V1, SDA1, and SCL1 of the MAX4895E are characterized for protection to the following limits: • ±15kV using the Human Body Model • ±8kV IEC 61000-4-2 Contact Discharge ESD Test Conditions ESD performance depends on a variety of conditions. Contact Maxim for a reliability report documenting test setup, methodology, and results. _______________________________________________________________________________________ VGA Port Protector CHARGE-CURRENTLIMIT RESISTOR HIGHVOLTAGE DC SOURCE Cs 100pF RD 1500Ω RC 50MΩ TO 100MΩ DISCHARGE RESISTANCE CHARGE-CURRENTLIMIT RESISTOR DEVICE UNDER TEST STORAGE CAPACITOR DISCHARGE RESISTANCE STORAGE CAPACITOR DEVICE UNDER TEST I 100% 90% PEAK-TO-PEAK RINGING (NOT DRAWN TO SCALE) IPEAK Ir Cs 150pF RD 330Ω Figure 1c. IEC 61000-4-2 ESD Test Model Figure 1a. Human Body ESD Test Model IP 100% 90% HIGHVOLTAGE DC SOURCE MAX4895E RC 1MΩ AMPS 36.8% 10% 0 10% 0 tRL TIME tr = 0.7ns TO 1ns tDL CURRENT WAVEFORM t 30ns 60ns Figure 1d. IEC 61000-4-2 ESD Generator Current Waveform Figure 1b. Human Body Current Waveform Human Body Model (HBM) Figure 1a shows the Human Body Model, and Figure 1b shows the current waveform it generates when discharged into a low impedance. This model consists of a 100pF capacitor charged to the ESD voltage of interest that is then discharged into the test device through a 1.5kΩ resistor. IEC 61000-4-2 The IEC 61000-4-2 standard covers ESD testing and performance of finished equipment. However, it does not specifically refer to integrated circuits. The MAX4895E assists in designing equipment to meet IEC 61000-4-2 without the need for additional ESD-protection components. The major difference between tests done using the Human Body Model and IEC 61000-4-2 is higher peak current in IEC 61000-4-2 because series resistance is lower in the IEC 61000-4-2 model. Hence, the ESD withstand voltage measured to IEC 61000-4-2 is generally lower than that measured using the Human Body Model. Figure 1c shows the IEC 61000-4-2 model, and Figure 1d shows the current waveform for IEC 61000-4-2 ESD Contact Discharge test. Chip Information PROCESS: BiCMOS Package Information For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO. 16 TQFN-EP T1633+4 21-0136 90-0031 _______________________________________________________________________________________ 7 MAX4895E VGA Port Protector Revision History PAGES CHANGED REVISION NUMBER REVISION DATE 0 4/09 Initial release — 1 6/10 Deleted the “Top Mark” column from the Ordering Information 1 DESCRIPTION Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 8 _____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.