LM3450 LM3450 LM3450A LED Drivers with Active Power Factor Correction and Phase Dimming Decoder Literature Number: SNVS681C June 20, 2011 LED Drivers with Active Power Factor Correction and Phase Dimming Decoder General Description Features The LM3450/50A is a power factor controller (PFC) with separate phase dimming decoder. The PFC regulates the output voltage while maintaining excellent power factor. The phase dimming decoder interprets the phase angle and remaps it to a 500Hz PWM output. This device is ideal for implementing a dimmable off-line LED driver for 10-100W loads. The phase dimming decoder has several unique features. The input-output mapping is programmable for design flexibility, while a dynamic filter and variable sampling rate provide smooth uniform dimming. A dynamic hold circuit ensures that the phase dimmer angle is decoded properly while minimizing extra power loss. The LM3450A is identical to the LM3450 with the exception of one circuit operation. The dynamic hold current is sampled in the LM3450 while it continuously operates in the LM3450A. This difference between the two devices defines the suitable applications for each. The following is a general guideline for choosing the correct device: • Any 120V designs with POUT > 15W - LM3450A • Any 230V designs with POUT > 25W - LM3450A • 120V 2-Stage designs with POUT < 15W - LM3450 • 230V 2-Stage designs with POUT < 25W - LM3450 ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Critical conduction mode PFC Over-voltage protection Feedback short circuit protection 70:1 PWM decoded from phase dimmer Analog dimming Programmable dimming range Digital angle and dimmer detection Dynamic holding current Smooth dimming transitions Low power operation Start-up pre-regulator bias Precision voltage reference Applications ■ ■ ■ ■ Dimmable downlights, troffers, and lowbays Large form factor bulbs Indoor and outdoor area SSL Power supply PFC Typical Application 30127401 © 2011 National Semiconductor Corporation 301274 www.national.com LM3450 LM3450A LED Drivers with Active Power Factor Correction and Phase Dimming Decoder LM3450 LM3450A LM3450 LM3450A Connection Diagram Top View 30127402 16-Lead TSSOP NS Package Number MTC16 Ordering Information Order Number Spec. Package Type NSC Package Drawing Supplied As LM3450MT NOPB TSSOP-16 MTC16 92 Units, Rail LM3450MTX NOPB TSSOP-16 MTC16 2500 Units, Tape and Reel LM3450AMT NOPB TSSOP-16 MTC16 92 Units, Rail LM3450AMTX NOPB TSSOP-16 MTC16 2500 Units, Tape and Reel www.national.com 2 Pin 1 Name VREF Description Application Information 3V Reference Reference Output: Connect directly to VADJ or to resistor divider feeding VADJ and to necessary external circuits. Analog Dim and Phase Dimming Range Input: Connect directly to VREF to force standard 70% phase dimming range. Connect to resistor divider from VREF to extend usable range of some phase dimmers or for analog dimming. Connect to GND for low power mode. 2 VADJ Analog Adjust 3 FLT2 Filter 2 Ramp Comparator Input: Connect a series resistor from FLT1 capacitor and a capacitor to GND to establish second filter pole. 4 FLT1 Filter 1 Angle Decoder Output: Connect a series resistor to a capacitor to GND to establish first filter pole. 5 DIM 500 Hz PWM Output Open Drain PWM Dim Output: Connect to dimming input of output stage LED driver (directly or with isolation) to provide decoded dimming command. 6 VAC Sampled Rectified Line Multiplier and Angle Decoder Input: Connect to resistor divider from rectified AC line. 7 COMP Compensation Error Amplifier Output and PWM Comparator Input: Connect a capacitor to GND to set the compensation. Error Amplifier Inverting Input: Connect to output voltage via resistor divider to control PFC voltage loop for non-isolated designs. Connect a 5.11kΩ resistor to GND for isolated designs (bypasses error amplifier). Also includes over-voltage protection and shutdown modes. 8 FB Feedback 9 ISEN Input Current Sense 10 GND Power Ground System Ground 11 CS Current Sense MosFET Current Sense Input: Connect to positive terminal of sense resistor in PFC MosFET source. 12 GATE Gate Drive 13 VCC Input Supply 14 ZCD Zero Crossing Detector Demagnetization Sense Input: Connect a 100kΩ resistor to transformer/inductor winding to detect when all energy has been transferred. 15 HOLD Dynamic Hold Open Drain Dynamic Hold Input: Connect to holding resistor which is connected to source of passFET. 16 BIAS Pre-regulator Gate Bias Pre-regulator Gate Bias Output: Connect to gate of passFET and through resistor to rectified AC (drain of passFET) to aid with startup. Input Current Sense Non-Inverting Input: Connect to diode bridge return and resistor to GND to sense input current for dynamic hold. Connect a 0.1µF capacitor and Schottky diode to GND, and a 0.22µF capacitor to HOLD. Gate Drive Output: Connect to gate of main power MosFET for PFC. Power Supply Input: Connect to primary bias supply. Connect a 0.1µF bypass capacitor to ground. 3 www.national.com LM3450 LM3450A Pin Descriptions LM3450 LM3450A Continuous Power Dissipation Maximum Junction Temperature Storage Temperature Range Maximum Lead Temperature (Solder and Reflow) (Note 2) ESD Susceptibility (Note 3) HBM MM FICDM Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. VCC, HOLD, DIM, BIAS HOLD Power BIAS Current ZCD Current COMP, FB, VAC, FLT1, FLT2, VREF, CS, VADJ ISEN GATE -0.3V to 25.0V 250 mW Continuous 5.0mA Continuous +/- 10mA -0.3V to 7.0V -7.0V to 7.0V -0.3V to 18V Continuous -2.5V for 100ns 20.5V for 100ns -1mA to +1mA Continuous Internally Limited Internally Limited -65°C to +150°C 260°C 2kV 200V 750V Operating Conditions (Note 1) VCC Range Junction Temperature Range 8.5V to 20V -40°C to +125°C Electrical Characteristics (Note 1) Unless otherwise specified VCC = 14V. Specifications in standard type face are for TJ = 25°C and those with boldface type apply over the full Operating Temperature Range ( TJ = −40°C to +125°C). Typical values represent the most likely parametric norm at TA = TJ = +25°C, and are provided for reference purposes only. Symbol Parameter Conditions Min (Note 4) Typ (Note 5) Max (Note 4) Units SUPPLY VOLTAGE INPUT (VCC) VCC-RISE Controller Enable Threshold VCC Rising 12.2 13.0 13.6 VCC-FALL Controller Disable Threshold VCC Falling 7.4 7.9 8.5 Glitch Filter Delay 9 Turn-on Delay 40 V µs IQ VCC Quiescent Current No Switching 1.6 IQ-SD VCC Shutdown Current VFB = 0V 515 625 µA 2.50 2.57 V mA ERROR AMPLIFIER & COMPENSATION (FB, COMP) VFB GM FB Reference (Normal Operation) 2.43 Input Bias Current VFB = 2.5V Transconductance VFB = 2.5V 100 Output Source / Sink Capability FB Pull-up Current Source VFB < 1.8V 115 161 60 85 110 43 51 59 COMP Pull-up Resistor VCMP-B COMP Low Threshold (Burst) VCMP Falling COMP Low Hysteresis VFB-SD Low Threshold (Shutdown) FB Mid Threshold (EA Disabled) VFB Falling 150 VFB Falling 328 5 kΩ V 168 186 346 mV 368 20 FB High Threshold (Over-voltage) COMP Pre-bias Source Current VTHM µA VTHM -0.08 20 FB Mid Hysteresis VFB-OV µS 20 FB Low Hysteresis VFB-EAD nA 69 1.20 x VFB VCMP = 0.5V Minimum COMP Voltage (Normal) 1.22 x VFB V 415 µA 1.47 V ANGLE DEMODULATION & MULTIPLIER (COMP, VAC) VAC-DET VAC Angle Detection Threshold Angle Demodulation Delay Time 334 Both edges 8 VAC Dynamic Input Voltage Range 378 mV µs 0 to 5.5 COMP Dynamic Input Voltage Range V VTHM to VTHM +2 VAC Input Impedance www.national.com 356 500 4 kΩ KM Parameter Multiplier Gain (Includes Internal Resistor Divider) Conditions Min (Note 4) VAC = 3V, VCMP = VTHM+1.5V Typ (Note 5) Max (Note 4) 0.5 Units 1/V ZERO CURRENT DETECTOR (ZCD) VZCD-RIS ZCD Input Threshold VZCD Rising Hysteresis 1.45 1.5 1.55 V 150 200 250 mV Delay to Output 135 VZCD-H Positive Clamp Voltage IZCD = 1mA 6.0 VZCD-L Negative Clamp Voltage IZCD = -50µA 0.61 ns V PWM COMPARATOR (CS) VOS VLIM PWM Comparator Input Offset Voltage 30 mV PWM Comparator Input Bias Current 20 nA CS Current Limit Threshold 1.40 CS Delay to Output CS Blanking Sinking Impedance tLEB Leading Edge Blanking (LEB) Time 1.50 1.60 V 100 ns 1 kΩ 140 ns ANALOG ADJUST INPUT (VADJ) VADJ-LP VADJ Low Threshold (Low Power Mode) VADJ Falling 56 VADJ Low Hysteresis mV 50 VADJ Pull-up Current Source VADJ Open Voltage 75 VADJ Open 1 µA 3 V DYNAMIC HOLD CIRCUIT (HOLD, ISEN) RDSON-HD HOLD MosFET On-Resistance VSEN-REF ISEN Reference Voltage ISEN Short to GND 22 30 42 Ω 162 200 232 mV ISEN Bias Current 5 µA PRE-REGULATOR GATE DRIVE OUTPUT (BIAS) VBIAS BIAS High Voltage @ 100µA VCC < VCC-FALL 18.8 21 22.6 BIAS Low Voltage @ 100µA VCC > VCC-RISE 13.5 14 14.5 V GATE DRIVER OUTPUT (GATE) VGATE-H GATE Voltage High IGATE = 20mA 11.5 IGATE = 200mA 10.5 (Note 6) ±1.5 GATE Pull Down Resistance GATE Peak Current 2 V 8 Ω A REFERENCE VOLTAGE OUTPUT (VREF) VREF Reference Voltage No Load Current Limit 2.85 3 3.15 V 1.5 2.0 3.0 mA DIMMING OUTPUT (DIM, FLT1, FLT2) FLT1 Output Impedance Standby Mode 500 Transition Mode 1.6 Triangle Waveform Compared to FLT2 High Low fDIM DIM Frequency 180 kΩ 1.49 V 15 mV 460 700 Hz OFF-TIMERS tOFF-MAX Maximum Off-Time (Normal Operation) 340 tOFF-LP Off-Time (Low Power Mode) 42 5 µs www.national.com LM3450 LM3450A Symbol LM3450 LM3450A Symbol Parameter Conditions Min (Note 4) Typ (Note 5) Max (Note 4) Units THERMAL SHUTDOWN Thermal Limit Threshold (Note 6) 160 Thermal Limit Hysteresis 20 °C THERMAL RESISTANCE θJA Junction to Ambient θJC Junction to Case TSSOP-16 (Note 6, Note 7) 38.0 10.0 °C/W Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under which operation of the device is guaranteed and do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions, see the Electrical Characteristics table. All voltages are with respect to the potential at the GND pin, unless otherwise specified. Note 2: Refer to National’s packaging website for more detailed information and mounting techniques. http://www.national.com/analog/packaging/ Note 3: Human Body Model, applicable std. JESD22-A114-C. Machine Model, applicable std. JESD22-A115-A. Field Induced Charge Device Model, applicable std. JESD22-C101-C. Note 4: All limits guaranteed at room temperature (standard typeface) and at temperature extremes (bold typeface). All room temperature limits are 100% production tested. All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods. All limits are used to calculate Average Outgoing Quality Level (AOQL). Note 5: Typical numbers are at 25°C and represent the most likely norm. Note 6: These electrical parameters are guaranteed by design, and are not verified by test. Note 7: Junction-to-ambient thermal resistance is highly board-layout dependent. In applications where high maximum power dissipation exists, namely driving a large MOSFET at high switching frequency from a high input voltage, special care must be paid to thermal dissipation issues during board design. In high-power dissipation applications, the maximum ambient temperature may have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP = 125°C for Q1, or 150°C for Q0), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to ambient thermal resistance of the package in the application (θJA), as given by the following equation: TA-MAX = TJ-MAX-OP – (θJA × PD-MAX). www.national.com 6 TA=+25°C and VCC = 14V unless otherwise specified HOLD RDSON vs. Junction Temperature Leading Edge Blanking vs. Junction Temperature 30127415 30127404 Current Limit Threshold vs. Junction Temperature VAC = 3V; VCMP = VTHM + 1.5V Multiplier Gain vs. Junction Temperature VAC = 3V; VCMP = VTHM + 1.5V 30127405 30127406 Transconductance VFB = 2.5V; ΔVFB = 50mV BIAS Voltage vs. Junction Temperature High @ VCC < VCCFALL; Low @ VCC > VCCRISE 30127408 30127407 7 www.national.com LM3450 LM3450A Typical Performance Characteristics LM3450 LM3450A VCC UVLO Threshold vs. Junction Temperature Shutdown Current vs. Junction Temperature 30127410 30127409 VREF Reference vs. Junction Temperature FB Reference vs. Junction Temperature 30127412 30127411 ISEN Reference vs. Junction Temperature VAC Detection Threshold vs. Junction Temperature 30127413 www.national.com 30127414 8 Current Sense Threshold vs. VCOMP and VAC 30127416 30127417 Decoder Mapping from VAC to DIM 1.0 DIM PIN DUTY CYCLE 0.8 0.5V 0.6 0.4 1V 1.5V 0.2 0.0 VADJ=3V 2V 2.5V -0.2 0.0 0.2 0.4 0.6 0.8 1.0 DEMODULATED VAC PIN DUTY CYCLE 30127419 9 www.national.com LM3450 LM3450A Transconductance vs. VFB LM3450 LM3450A Block Diagram 30127421 www.national.com 10 LM3450 LM3450A 30127422 FIGURE 1. Typical Flyback Application PWM output. The PWM output can then be sent directly, or through optical isolation, to the dimming input of a second stage LED driver. To ensure the decoder properly interprets the dimming angle, dynamic hold is provided which prevents the phase dimmer from misfiring. The input current is sensed and when the current drops below a preset minimum, the system adds more current. Both the dynamic hold and the decoder are sampled synchronously in the LM3450 to reduce the overall efficiency drop due to the additional hold current. When a decoding sample period occurs, the dynamic hold is activated to ensure a proper angle is decoded. Because of this sampling method, nonsampled cycles will potentially cause the phase dimmer to misfire but should not affect the output LED current regulation. For higher power applications, where the dynamic hold provides much less current on average, the LM3450A can be used. The LM3450A has continuous dynamic hold which prevents the dimmer from ever misfiring. This is extremely helpful when designing for single stage solutions, where there is no second stage to provide good line rejection. The continuous dynamic hold is also helpful for the higher power two stage applications where the input capacitance is larger. One last feature of the phase decoder is a dynamic filter that, combined with the variable sampling rate, provides fast, smooth dimming transitions. Theory of Operation The LM3450/50A is a single device with both power factor control (PFC) and phase dimming decoder functions. This device is designed to control isolated flyback converters and provide active power factor correction. In addition to being a PFC, the LM3450/50A can interpret a phase dimming (frequently called triac dimming) input and provide a corresponding PWM output to properly dim an LED load. This combination of features provides an excellent method to convert a standard AC mains input to a dimmable LED output of 10-100W. It should be noted that the LM3450/50A can control a boost converter in a similar manner. However, this datasheet will focus mostly on the flyback topology due to the high demand for isolated LED driver applications. Discussion of the LM3450/50A functionality will refer to Figure 1 component designators. The PFC control operates in critical conduction mode (CRM) using zero crossing detection (ZCD) to terminate the off-time. The PFC portion of this device includes an error amplifier, multiplier, current sense circuit, zero crossing detector, and gate driver. The internal error amplifier is used for feedback of the output voltage in non-isolated designs. However, it can be disabled for isolated designs where the error amplifier needs to be on the secondary side. The phase dimmer decoder detects the dimming angle of the rectified AC line, decodes, filters and remaps it to a 500Hz 11 www.national.com LM3450 LM3450A 30127423 FIGURE 2. PFC System Architecture quency content is removed with large energy storage capacitance at the output. Using this control architecture, the converter is able to provide two important functions at the same time: • Shape the input current • Regulate the output voltage The PFC control approach requires two separate control loops to achieve both functions: a fast loop which shapes the input current, and a slow loop that regulates the output voltage. The fast control loop shapes the input current to have the same sinusoidal shape as the AC input voltage. Assuming both are perfect sinusoids with zero distortion or phase shift, the power factor will be perfect (unity). Unfortunately, distortion is always present in switching converters. An input filter, which is required to comply with EMI standards, helps to attenuate the switching content, thereby reducing distortion. However, the added filter capacitance will increase the phase shift at the same time. Though perfect PF is not achievable within real applications, extremely high PF (>.99) is possible using most active PFCs. The output voltage has to be regulated slowly to ensure the converter ignores the twice line frequency ripple present on the output. Therefore, the voltage loop containing the error amplifier should have a bandwidth at least an order of magnitude slower (<20Hz is common). Sometimes the bandwidth is increased to improve transient response, which is the case with off-line dimmable LED drivers. Though PF decreases with the increase in bandwidth, high PF (>.95) is still possible. PFC BACKGROUND Power factor (PF) is a number between 0 and 1 that indicates how well energy is transmitted from input to output of a system. It can be described by average power (PAVG), RMS voltage (VRMS), and RMS current (IRMS): Or by distortion factor (KDIST) and displacement factor (KDISP): With a purely resistive system, PF = 1. The addition of reactive elements necessary in any converter, such as EMI filters and energy storage, will induce some amount of displacement (phase shift between the input voltage and input current). The addition of switching devices will also create distortion (energy present in the harmonics relative to the switching frequencies). These non-idealities decrease the PF towards zero. Active power factor correction attempts to make the input impedance look as resistive as possible to the power source. Since the output of the converter is usually a regulated voltage or current, there is a need for large energy storage elements to remove the twice line frequency (100Hz or 120Hz) ripple. A power factor control architecture, as shown in Figure 2, has very little capacitance at the input. Instead, the twice line fre- www.national.com 12 LM3450 LM3450A 30127424 FIGURE 3. Basic CRM Inductor Current Waveform peak current envelope (IS-pk) will simply be a scaled version of the primary according to the turns ratio of the transformer. Assuming good attenuation of the switching ripple via the EMI filter, the average input current (IIN), represented by the red line in Figure 4, can also be approximated as a sinusoid proportional to the duty cycle (D(t)): CRM BACKGROUND During critical conduction mode (CRM), a converter operates at the boundary of continuous conduction mode (CCM) and discontinuous conduction mode (DCM). This is usually implemented as follows. The main switching MosFET (QSW) is turned on and the inductor current rises to a peak threshold. QSW is then turned off and the current falls until it reaches zero. At this point, QSW is turned on and the cycle repeats. Near zero voltage switching, enabled by the inductor current return to zero, gives CRM topologies an efficiency improvement compared to CCM topologies. Figure 3 shows the resulting inductor current waveform, where the average inductor current (IL) is half of the peak current (IL-MAX). In a CRM flyback PFC application, the rectified AC input is fed forward to the control loop, creating a sinusoidal primary peak current envelope (IP-pk) as shown in Figure 4. The secondary Since CRM operation is hysteretic and the input voltage is fedforward, the input current shaping loop is as fast as possible. Only the output voltage needs to be regulated with a narrow bandwidth error amplifier, which greatly simplifies the system dynamics. 30127425 FIGURE 4. CRM Flyback Current Waveforms 13 www.national.com LM3450 LM3450A 30127426 FIGURE 5. PFC Control Circuit Once QSW is turned off, the LM3450/50A waits until the inductor (boost) or transformer (flyback) is demagnetized to turn QSW on again. Demagnetization, sensed at ZCD, occurs when the current through the magnetic component falls to zero. Since the output voltage is regulated, the slope of the current remains relatively constant and, coupled with the variable peak detect, creates a variable off-time. The sinusoidal peak detection envelope creates an input current that is sinusoidal and in phase with the input voltage providing excellent PF. The PWM comparator 30mV input offset voltage ensures current is drawn at the zero-crossings of the AC line, reducing distortion and further improving PF. POWER FACTOR CONTROLLER The LM3450/50A uses CRM control to regulate the output voltage and provide power factor correction. In a non-isolated boost topology, an external voltage divider (RFB1, RFB2) is used to sense the output voltage, as shown in Figure 5. The divider is connected to the inverting input (FB) of the internal error amplifier. The LM3450/50A regulates the feedback voltage (VFB) to 2.5V in a closed loop fashion. The FB pin has a shutdown mode to protect against a feedback short and an OVP mode which terminates switching when output over-voltage is sensed. With the FB shutdown mode, it is necessary to have a preliminary biasing method for the output of the error amplifier (COMP). Otherwise, the converter would never start. COMP is pre-biased with a 415µA current until the voltage at COMP (VCMP) exceeds the minimum operational voltage (VTHM). For an isolated flyback topology, where the error amplifier is on the secondary, the LM3450/50A internal error amplifier can be bypassed using a single 5.11kΩ resistor (RFB1) from FB to GND. This engages an internal 5kΩ pull-up resistor at COMP. COMP can then be connected directly to the optical isolation as shown in Figure 5. COMP and the sensed rectified AC input voltage (VAC), provided via a resistor divider (RAC1, RAC2), are inputs to the multiplier. The current through the sense resistor (RCS) produces a voltage (VCS) that is compared to the multiplier output. When VCS exceeds the multiplier output, QSW is turned off. The peak detect threshold and the current slope during an on-time are proportionally changing which yields a nearly constant on-time, shown in Figure 4: CURRENT SENSE The LM3450/50A senses current through QSW via a sense resistor (RCS) between the source of QSW and GND. When VCS exceeds the output of the multiplier (VMLT), QSW is turned off. VMLT is variable over the line cycle and is a function of the scaled rectified AC voltage (VAC), the COMP voltage referenced from its operational minimum (VCOMP-VTHM), the multiplier gain (KM) and the PWM comparator offset (VOS): The LM3450/50A has a leading edge blanking (LEB) circuit that pulls the current sense input to the PWM comparator low for 140µs at the beginning of each on-time. The LEB blanks the current spike and associated ringing due to the turn-on transient of QSW, limiting the minimum achievable duty cycle. OVER CURRENT PROTECTION The LM3450/50A has a current limit threshold (VLIM = 1.5V) at CS to protect the system from over-current conditions. If VCS exceeds VLIM, QSW is immediately turned off until ZCD triggers a new on-time. www.national.com 14 30127427 FIGURE 6. ZCD Waveforms for Flyback Design SECONDARY ERROR AMPLIFIER For isolated designs, the error amplifier on the secondary should take the form of a proportional integral (PI) compensator. The amplifier is frequently implemented with an LMV431. The output voltage resistor divider (RFB1, RFB2) provides the sensed output voltage to the LMV431 inverting input. The PI compensation is achieved by connecting RSC and CSC in between the LMV431 input and output, shown in Figure 7. In addition, CCMP is placed from COMP to GND on the primary for higher frequency noise attenuation. In addition to the basic error amplifier, a soft-start circuit can be implemented using a capacitor, two diodes and a Zener diode as shown in Figure 7. This secondary softstart circuit has no restart mechanism, therefore a primary side softstart is recommended as described in the SOFTSTART section of this document. ZERO CURRENT DETECTION ZCD is implemented with a 100kΩ resistor from the ZCD pin to a coupled winding on the transformer or inductor as shown in Figure 5. This winding is also used to bootstrap VCC after start-up. When QSW turns off, the voltage at the ZCD pin (VZCD) increases as energy is transferred through the auxiliary winding. The circuit arms when VZCD exceeds 1.5V. Then, when the energy is fully transferred, VZCD decreases towards zero. When VZCD falls below 1.3V, the transformer is assumed to be demagnetized, the circuit disarms, and QSW is turned back on as shown in Figure 6. The ZCD pin voltage will remain low until QSW is turned off via peak detection and the cycle repeats. SWITCHING FREQUENCY With a constant on-time and variable off-time, there is a variable switching frequency: Figure 4 shows that the minimum switching frequency occurs at the peak of the rectified AC waveform, while the maximum switching frequency occurs at the valley. ERROR AMPLIFIER The LM3450/50A internal error amplifier is used for non-isolated designs (boost) where the output voltage can be directly sensed, via a resistor divider, at the FB pin. The FB pin is the inverting input of the trans-conductance amplifier which is regulated to 2.5V. The COMP pin is the output of the amplifier and external compensation is placed from COMP to GND in the form of a single capacitor (CCMP) as shown in Figure 5, a series resistor and capacitor, or both. The output of the amplifier sources or sinks current as necessary to force the inputs of the amplifier to be equal. The compensation method depends upon the transient performance desired and requires a loop gain analysis. This analysis can be somewhat complex and cumbersome. A detailed analysis can be found Application Notes AN-2098 and/or AN-2150. 30127428 FIGURE 7. Secondary Error Amplifier 15 www.national.com LM3450 LM3450A If the COMP pin voltage (VCMP) falls below 1.4V at any time, the device enters burst mode where the GATE is off for 340µs then is turned on. If VCMP is still below 1.4V at the end of the on-time then another 340µs off-time occurs. However, if VCMP has risen above 1.4V, the converter continues switching until it falls below the threshold again. This feature is necessary to prevent the output of the converter from rising arbitrarily high because the minimum on-time of the device prevents less energy transfer. The LM3450/50A also implements both feedback short circuit protection and output over-voltage protection (OVP) functions at the FB pin. If VFB exceeds 3V, then OVP is engaged and the part stops switching until VFB falls below 3V. In the same manner, if VFB falls below 168mV, then shutdown is engaged and switching stops until VFB exceeds 188mV. The flyback topology is frequently used to provide isolation from input to output. Since, the current transfer ratio (CTR) of standard optical isolation varies over temperature, proper regulation using primary error amplifiers is difficult. An error amplifier is usually placed in the secondary to regulate the output voltage accurately. To accommodate isolated designs, the LM3450/50A internal error amplifier can be bypassed by placing a 5.11kΩ resistor from FB to GND. This engages a 5kΩ pull-up resistor from COMP to an internal 5V rail. LM3450 LM3450A PHASE DIMMER OPERATION A simplified schematic of a phase dimmer is shown in Figure 9. An RC network consisting of R1, R2, and C1 delay the turnon of the triac until the voltage on C1 reaches the trigger voltage of the diac. Increasing the resistance of the potentiometer (wiper moving downward) increases the turn-on delay which decreases the on-time or “conduction angle” of the triac (θ). This reduces the average power delivered to the load. PRECISION VOLTAGE REFERENCE The LM3450/50A provides a 3V voltage reference (VREF) for biasing the VADJ pin as well as any external circuitry. VREF is regulated once VCC exceeds 3V. There is a 2mA current limit for the reference. A 10nF ceramic bypass capacitor should be placed from VREF to GND. LOW POWER SHUTDOWN The LM3450/50A can be placed into a low power shutdown by grounding the VADJ pin (any voltage below 75mV). During low power shutdown, the device will turn on the GATE for one cycle followed by a fixed off-time of 42µs and the cycle repeats. During shutdown, the DIM output will be high (zero light output) since the buffer rail at FLT1 will be at or near zero. This feature is designed to hold up the PFC output voltage while removing the load (turning the LEDs off). THERMAL SHUTDOWN Internal thermal shutdown circuitry is provided to protect the IC in the event that the maximum junction temperature is exceeded. The threshold for thermal shutdown is 160°C with a 20°C hysteresis. During thermal shutdown GATE is disabled. 30127429 FIGURE 9. Basic Forward Phase Dimmer Phase dimmer voltage waveforms are shown in Figure 8. Figure 8a shows the full sinusoid of the input voltage. Even when set to full brightness; few dimmers will provide 100% conduction angle. Figure 8b shows a waveform from a forward phase dimmer. The off-time can be referred to as the firing angle and is simply 180° – θ. Figure 8c shows the waveform of a reverse phase dimmer (also called an electronic dimmer in the lighting industry). These typically or more expensive, microcontroller based dimmers that use switching devices other than triacs. Note that the conduction angle starts from the zero-crossing, and terminates some time later. This method of control reduces the noise spike at the transition. Any form of phase dimming modulates the incoming AC waveform by chopping part of the sinusoid, reducing the average power to the load. These dimmers work very well with standard incandescent bulbs, but not with power converters. A converter attempts to regulate the load in with presence of any input, effectively ignoring the phase angle. To implement a dimmable converter, the angle must be sensed at the input, decoded and used to properly control the LED current regulator. 30127430 FIGURE 8. Phase Dimming Waveforms www.national.com 16 LM3450 LM3450A 30127431 FIGURE 10. Dimming Decoder Circuit of low dimming levels to the human eye. A minimum duty cycle limits the maximum achievable contrast ratio to approximately 70:1. The remapped PWM signal is buffered and output at FLT1 with amplitude equal to VADJ as shown in Figure 12. PHASE DIMMING DECODER The LM3450/50A uses the rectified AC line voltage to interpret the conduction angle. Figure 10 shows the LM3450/50A decoder circuit with associated external circuitry. The rectified AC line voltage is scaled via a resistor divider (RAC1, RAC2) and connected to the VAC pin. VAC is compared to a 356mV reference to generate a twice line frequency PWM signal with corresponding duty cycle as shown in Figure 11. 30127433 FIGURE 12. FLT1 to FLT2 Mapping The FLT1 signal is routed through a 2 pole low pass filter (RF1, CF1, RF2, CF2), as shown in Figure 10, to remove the twice line frequency ripple. The resulting analog signal at FLT2 is compared to a 500Hz Triangle wave to create the inverted PWM signal at the DIM pin as shown in Figure 13: 30127432 FIGURE 11. Phase Angle Demodulation For best results, RAC1 and RAC2 are suggested to be sized so that the VAC voltage crosses the 356mV threshold when the rectified AC line is as follows: • 120V systems: 25V to 45V • 230V systems: 40V to 70V The demodulated duty cycle is sampled and logarithmically remapped to a 300Hz PWM signal improving the resolution 30127434 FIGURE 13. FLT2 to DIM Mapping 17 www.national.com www.national.com 1.2 DIM PIN DUTY CYCLE (INVERTED) LM3450 LM3450A This PWM signal at the DIM pin can be used as the dim input to a secondary LED driver. DIM is an open drain output designed for isolated solutions. Optical isolation is used to transmit signals across the isolation boundary. With most optoisolators, the edge rate is dependent on the amount of drive current through the photodiode. The open-drain configuration allows the primary bias supply (VCC) to provide the current as shown in Figure 10. The choice of resistor (RPB) between VCC and the photodiode anode will set the drive current. This enables the user to trade-off PWM accuracy with system efficiency. The open drain configuration also ensures that the secondary has a resistor from the phototransistor’s emitter to secondary ground (not from collector to secondary bias). During system turn-off, this prevents an undesired LED blink because the secondary stage LED driver is forced off. A variable sample rate and dynamic filter ensure fast, smooth dimming transitions (movement of the dimmer) while maintaining robust flicker-free behavior when the dimmer is static. The sample rate depends on past and present angle information. The dynamic filter is a dual mode filter. During standby mode, when a transition has not been made and the dimmer is static, a 500kΩ series resistor is connected between the buffered output and FLT1 as shown in Figure 10. The 500kΩ resistor is shorted when the LM3450/50A senses a large transition of the dimmer. This increases the filter speed while the dimmer is transitioning between levels to improve response time. The FLT1 and FLT2 poles created by each RC pair (RF1 and CF1, RF2 and CF2) should be set as follows: • CF1 and CF2 can be 1µF ceramic capacitors for all designs. • RF1 and RF2 should be set between 15kΩ (~10Hz) and 75kΩ (~2Hz). 2 Hz poles provide a “smooth fade” while 10Hz poles create a “snappy” response. These component values ensure that the static filter condition in standby mode has 1 pole approximately a decade lower than the nominal in order to provide good noise immunity to the system. 1.0 VADJ=3V 2.5V 0.8 0.6 0.4 2V 1.5V 1V 0.2 0.0 0.5V 0.0 0.2 0.4 0.6 0.8 1.0 LM3450/A DEMODULATED VAC PIN DUTY CYCLE 30127418 FIGURE 14. Complete Decoder Mapping Since the buffered decoder output has amplitude equal to VADJ and the resulting PWM signal is filtered into an analog voltage at FLT2, the VADJ pin can be used to change the mapping as shown in Figure 14. The maximum LED current (DIM = 0) when VADJ = 3V corresponds to decoded angles of 70% or greater. Some dimmers have a maximum angle greater than this. If VADJ is reduced to 2.5V, the maximum LED current will correspond to an angle of 80% and at VADJ = 2V the maximum will occur at a decoded angle of 95%. The VADJ pin can also be used to implement a standard analog adjust function. If the demodulated phase angle at VAC is above 85%, then the fast filter is always enabled (500kΩ shorted) and the VADJ pin can solely be used to scale the DIM pin duty cycle. When VADJ is pulled below 75mV the part enters low power shutdown so the maximum attainable contrast ratio using VADJ only is approximately 40:1. Both FLT1 and FLT2 have pull-down MosFETs that are turned on when VCC UVLO falling threshold is triggered. This provides a quick discharge path for the capacitors and eliminates the possibility of an undesired light level at the next startup. 18 LM3450 LM3450A 30127435 FIGURE 15. Dynamic Hold Circuit adds holding current via the HOLD circuitry to maintain 200mV across RSEN. The hold current is added by linearly adjusting the gate voltage of QHLD as shown in Figure 15. As the gate voltage of QHLD is increased, the HOLD pin voltage decreases, forcing a voltage across the resistance (RHLD) from the source of QPS to HOLD. This extra current is drawn from the input through the triac, but is not processed by the converter. Figure 17 shows a typical dynamic hold waveform of the LM3450 where interval 1 is a non-sampled conduction angle, 2 is the firing angle, and 3 is a sampled conduction angle. It should be noted that using the LM3450A will ensure every conduction angle looks like interval 3 in Figure 17. DYNAMIC HOLD A forward phase “triac” dimmer requires a minimum amount of current to be flowing through it during the entire conduction angle. This is referred to as hold current. If the minimum hold current requirement is not met, the triac will shut off (misfire). During normal operation, the converter will demand some amount of input current. However, at any point during the cycle, the input current can be low enough to cause a misfire. During an LM3450/50A sampling period, the triac should not misfire or the decoded angle will be inaccurate as shown in Figure 16. Since the triac is asymmetrical phase-to-phase, misfires can occur at different points in the waveform. After the triac misfires, the voltage returns to zero exponentially. This can create a large difference between decoded angles which can be observed as a “fluttering” of the light. 30127437 FIGURE 17. Dynamic Hold Waveform 30127436 The dynamic hold function is also necessary for reverse phase dimmers, but for a different reason. Reverse phase dimmers do not use triacs, therefore they do not require a minimum “holding” current. Instead, they need what is commonly called bleeder current. When a reverse phase dimmer turns off, the AC voltage is at a high value. There is an RC time constant associated with discharging the total effective input capacitance (EMI capacitors, PFC capacitor, damper FIGURE 16. Forward Phase Waveform To ensure the triac does not misfire during a sampling period and the angle is correctly decoded, a dynamic hold function is enabled. The input current is sensed with a resistor (RSEN) from GND to ISEN (the return of the full bridge rectifier). If the voltage across this resistor is less than 200mV, the device 19 www.national.com LM3450 LM3450A cuit to well below the switching frequency. However, if too large a capacitor is used, the bandwidth will be too low to respond to line transients. A maximum of 0.47µF should ensure good performance. Finally, a small Schottky diode should be placed from GND to ISEN to absorb the large current spikes associated with the triac firing edge. This diode should have a forward voltage above 200mV at the worst-case operating temperature so that it won’t interfere with dynamic hold regulation. capacitance). The decoder does not record the angle until the voltage reaches the 356mV threshold. This can cause the decoded angle to be much larger than it actually is and dependent on the RC time constant as shown in Figure 18. THERMAL PROTECTION With the LM3450A, QPS has to dissipate more power than with the LM3450. During worst case conditions such as open LED load, the converter will be demanding very little current regardless of the triac position. If the phase dimmer conduction angle is large and the load is not present, QPS has to dissipate many watts since the dynamic hold is attempting to regulate the current to ten's of mA. Using the LM3450, this is nominally not a problem since it is sampling the dynamic hold infrequently. However, the LM3450A is drawing the hold current every cycle which becomes a problem very quickly. It should be noted that If the input AC line is very noisy, the VAC input to the decoder could have enough variation in steady state to cause the decoder to think the dimmer is transitioning all of the time. This would increase the sampling rate dramatically, putting much more thermal strain on the passFET in LM3450 applications as well. To mitigate these problems, a thermal protection circuit should be implemented on the LM3450A designs (and can be on the LM3450 designs as well) as shown in red in Figure 15. The NTC thermistor should be placed on the opposite side of the PCB directly under the drain of QPS. This will provide the best thermal coupling while maintaining the necessary high voltage spacing constraints. At startup the NTC is at a high resistance value, turning the PNP fully on which provides the dynamic hold path. As the NTC heats up the resistance decreases and the base voltage increases. Eventually, the PNP will transition into linear mode and the effective resistance from collector to emitter will increase. This will decrease the maximum holding current, thereby decreasing the thermal stress on QPS. Given enough headroom, the circuit should reach thermal equilibrium in a safe controlled manner. Since this method of thermal protection linearly reduces the maximum hold current with increasing temperature, the foldback will not be perceptible to the consumer. Instead, the result of the foldback will simply be a reduction of contrast ratio, meaning the minimum achievable LED current will increase as the temperature increases beyond the foldback level. 30127438 FIGURE 18. Reverse Phase Waveforms The dynamic hold will quickly bleed off the excess charge in an attempt to regulate the voltage across RSEN. This will preserve the accuracy of the decoded phase angle. During the conduction angle (θ), dynamic hold is enabled only during a sample period for the LM3450. However, during the firing angle (delay time), dynamic hold is always enabled with the LM3450. This will ensure the rectified line voltage does not begin to rise due to leakage currents through the phase dimmer. Again, with the LM3450A the dynamic hold is continuously active during all conduction and firing angles. The minimum regulated input current can be calculated: The maximum possible additional holding current (which can occur when HOLD is still transitioning usually at the rising edge of the triac firing) can be approximated: It is recommended that the maximum hold current is set 10-15% higher than the minimum regulated input current. A minimum of 0.1µF capacitance should be placed between ISEN and HOLD to limit the bandwidth of the dynamic hold cir- www.national.com 20 LM3450 LM3450A 30127439 FIGURE 19. Primary Bias Circuitry PRIMARY BIAS SUPPLY The LM3450/50A requires a supply voltage at VCC, not to exceed 25V. The device has VCC under-voltage lockout (UVLO) with rising and falling thresholds of 12.9V and 7.9V respectively. A 24V Zener diode should be placed from the VCC pin to GND to protect the device from substantial spikes that could cause damage. Figure 19 shows how the LM3450/50A provides a quick way to generate the necessary primary bias supply at start-up. Since the AC line peak voltage is always higher than the rating of the controller, all designs require an N-channel MosFET (passFET). The passFET (QPS) is connected with its drain attached to the rectified AC. The gate of QPS is connected to the BIAS pin which has a stack of 2 Zener diodes internal to the device. These diodes are then biased from the rectified AC line through series resistance (RBS). The source of QPS is held at a VGS below the Zener voltage and current flows through QPS to charge up whatever capacitance is present. If the capacitance is large enough, the source voltage will remain relatively constant over the line cycle and this becomes the input bias supply at VCC. This bias circuit enables instant turn-on. However, once the circuit is operational it is desirable to bootstrap VCC to an auxiliary winding of the inductor or transformer (also used for ZCD). The two bias paths are each connected to VCC through a diode to ensure the higher of the two is providing VCC current. This bootstrapping greatly improves efficiency when quick start-up is necessary. To ensure that the auxiliary winding is powering VCC at all times except start-up, the LM3450/50A has a dual BIAS mode. The BIAS voltage at startup is 20V through two Zener diodes. When the VCC UVLO rising threshold is exceeded and the device turns on, the BIAS pin voltage is reduced to 14V (bottom 6V Zener is shorted). Once the VCC UVLO falling threshold is reached again, the BIAS pin will return to 20V to attempt to restart the device. It should be noted that the large hysteresis of VCC UVLO and the dual BIAS mode allow for a large variation of the auxiliary bias circuitry easing the design of the magnetics. SOFTSTART As in any off-line system, softstart is an important part of the design. Since the LM3450/50A are used with phase dimming applications, the typical startup problems are magnified since a phase dimmer is frequently turned on and off rapidly. This requires a softstart mechanism that quickly resets when the LM3450/50A turns off. Since the LM3450/50A has two distinct functional parts (PFC and phase decoder), ideally both should be softstarted simultaneously. This will ensure the most controlled start-up possible. The circuit in Figure 20 provides this exact functionality. Both VADJ and COMP are diode or'ed into an RC charging circuit fed from VCC. The reset mechanism is accomplished using an 18V Zener from BIAS, a current limiting resistor and an NPN transistor. The reset is activated when VCC uvlo falling is triggered and BIAS transitions to 20V. This discharges the RC to zero and as soon as VCC uvlo rising is passed BIAS transitions to 14V again, releasing the clamp on the RC softstart circuit. The RC will charge up to the 3.9V Zener clamp (which is above the dynamic range of COMP and VADJ and become effectively out of the circuit until the next turn-off. 30127450 FIGURE 20. Dual Softstart Circuit 21 www.national.com LM3450 LM3450A The designer must pay close attention to the power loss of the passFET when using the LM3450A. Designers must consider worst case possibilities with any power conversion designs. Worst case operating conditions with the LM3450A are usually found with the largest triac holding current requirements. Many phase dimmers require 25mA-40mA of holding current, and frequently designers are choosing 50mA as their minimum holding current requirement. The passFET package for common LM3450/50A designs should be capable of dissipating between 1W and 1.5W. The pass-FET can always be increased in size and/or the hold current can be reduced. Power calculations for the dynamic hold circuit as well as effective thermal protection are both described in the DYNAMIC HOLD section. The LM3450 and LM3450A is best differentiated in terms of the appropriate applications for each device. The Device Selection Guide can be used as a general guide for when to use each part. Design Information HOW TO SELECT THE CORRECT DEVICE (LM3450 or LM3450A) What application(s) are suitable for the LM3450, and when is the LM3450A appropriate? The difference centers on the power dissipation in the passFET. The passFET stands off the high AC voltage from the LM3450/50A, and provides a path for the hold current. The passFET operates in the linear region and dissipates power equal to the product of the voltage across it and the current through it. The LM3450 was designed to minimize the power dissipation in the passFET by applying holding current in a sampled form. The standby sampling rate (when the dimmer is not moving) is infrequent, allowing minimal impact on the thermal considerations of the passFET. Sampling of the dynamic hold is not desired for some applications although. An example where the sampled hold current may cause undesirable effects is the single stage flyback topology where the output of the flyback is directly connected to the LEDs. If the phase dimmer is allowed to misfire or create erratic differences in the input voltage and current waveforms, this behavior will appear as a "fluttering" of the LED light output at the sampling rate when the single stage topology is used. The light flutter is most observable at low input currents (dimming). A small perturbation in the input voltage due to phase dimmer misfire can create a visible difference in the output light. Using a secondary LED driver stage eliminates this problem. Cost sensitive applications may drive the design to a single stage solution, and the LM3450A was developed to address this market. The LM3450A provides continuous dynamic hold current on every AC cycle preventing the phase dimmer from misfire, and the sampling frequency from appearing at the output. Another design consideration where continuous dynamic hold may be advantageous is the reduced stresses on input EMI R/C snubber networks. www.national.com Device Selection Guide Product AC Input 120V High End Downlight 230V Low Cost Downlight or Large High End Bulb 22 120V 230V Output Power Device POUT < 15W LM3450 POUT > 15W LM3450A POUT < 25W LM3450 POUT > 25W LM3450A Topology Two Stage Design POUT > 15W POUT > 25W LM3450A Single Stage Design LM3450 LM3450A Applications Information See AN-2098 and/or AN-2150 for detailed design and application information. TWO STAGE LED DRIVER – LM3450 PRIMARY AND LM3409HV SECONDARY 30127440 23 www.national.com LM3450 LM3450A 15W TWO STAGE DESIGN SPECIFICATIONS AC Input Voltage: 120VAC nominal (90VAC - 135VAC) or 230VAC nominal (180VAC - 265VAC) Regulated Flyback Output Voltage: 50V Regulated LED Current: 350mA LED Stack Voltage Maximum: 45V Bill of Materials *Components are used in both versions unless otherwise noted Reference Designator Description Manufacturer Part Number LM3450 IC PFC CONT 16-TSSOP NSC LM3450MT LM3409HV IC LED DRIVR 10-eMSOP NSC LM3409HVMY LMV431 IC SHUNT REG SOT-23 NSC LMV431AIM5 120V CAP CER 0.22µF 250V 1210 MURATA GRM32DR72E224KW01L 230V C1a, C1b, C5a, C5b CAP CER 68nF 250V 1210 MURATA GRM32QR72E683KW01L C2 CAP MPY 33nF 250VAC X1 RAD EPCOS B32912A3333M C3 CAP CER 47µF 6.3V 0805 TAIYO YUDEN JMK212BJ476MG-T 120V CAP MPY 0.1µF 400V RAD EPCOS B32612A4104J008 230V C4 CAP MPY 33nF 1000V RAD WIMA MKP10 - .033/1000/10 C6 CAP CER 4.7nF 500VAC Y1 RAD EPCOS VY1472M63Y5UQ63V0 C7a CAP ELEC 470µF 63V RAD NICHICON UPW1J471MHD3 C7b, C8b, C9b, C11, C15 CAP CER 0.1µF 50V 1206 MURATA GRM188R71H104KA93D C8a, C9a CAP ELEC 100µF 50V RAD NICHICON UHE1H101MPD C10 CAP CER 10nF 25V 0603 MURATA GRM188R71E103KA01D C12, C13 C14, C21 CAP CER 1µF 16V 0603 MURATA GRM188R71C105KA12D C16 CAP CER 0.22µF 16V 0603 TDK C1608X7R1C224K C17 CAP CER 10µF 16V 1206 MURATA GRM31CR71C106KAC7L C18, C20 CAP CER 1µF 100V 1206 TDK C3216X7R2A105M C19 CAP CER 2.2µF 6.3V 0603 TDK C1608X5R0J225M C22 CAP CER 470pF 100V 0603 TDK C1608C0G2A471J 120V DIODE ULTRAFAST 200V 1A SMA FAIRCHILD ES1D 230V D1 DIODE FAST 400V 1A DO-214AC FAIRCHILD ES1G D2 DIODE ULTRAFAST 200V 1A SMA FAIRCHILD ES1D D3, D5 DIODE ULTRAFAST 100V 0.2A SOT-23 FAIRCHILD MMBD914 D4 DIODE DUAL SCHOTTKY 20V 0.5A SOT-23 NXP SEMI PMEG3005CT,215 120V DIODE TVS 150V 600W UNI SMB LITTLEFUSE SMBJ150A 230V DIODE TVS 220V 600W UNI SMB LITTLEFUSE SMBJ220A D7 DIODE ULTRAFAST 600V 1A SMA FAIRCHILD ES1J D8 DIODE ZENER 24V 1.5W SMA MICRO-SEMI SMAJ5934B-TP D9 DIODE SCHOTTKY 20V 3A SMA FAIRCHILD ES2AA-13-F D10 DIODE RECT 600V 0.5A Minidip COMCHIP HD06 D11, D12 DIODE ZENER 10V 500mW SOD-123 FAIRCHILD MMSZ5240B D13 DIODE ULTRAFAST 70V 0.2A SOT-23 FAIRCHILD BAV99 D14 DIODE ZENER 3.3V 500mW SOD-123 ON-SEMI MMSZ3V3T1G D15 DIODE ZENER 1.8V 500MW SOD-123 ON-SEMI MMSZ4678T1G D16 DIODE SCHOTTKY 60V 2A SMB ON-SEMI SS26T3G D17 DIODE ZENER 3.9V 500MW SOD-123 ON-SEMI MMSZ4686T1G D18 DIODE ZENER 18V 500MW SOD-123 ON-SEMI MMSZ5248T1G L1, L2, L3 IND SHIELD 1mH 0.46A SMT COILCRAFT MSS1038-105KL L4 IND SHIELD 470µH 1.06A SMT COILCRAFT MSS1278-474KLB Q1 MOSFET N-CH 800V 3A DPAK ST MICRO STD4NK80ZT4 D6 www.national.com 24 Description Manufacturer Part Number Q2 120V MOSFET N-CH 600V 4.4A DPAK INFINEON IPD60R950C6 230V MOSFET N-CH 800V 3A DPAK ST MICRO STD4NK80ZT4 Q3, Q4 TRANS NPN 40V 0.6A SOT-23 FAIRCHILD MMBT4401 Q5 MOSFET P-CH 70V 5.7A DPAK ZETEX ZXMP7A17K Q6 TRANS PNP 40V 0.2A SOT-23 FAIRCHILD MMBT3904 120V RES 330Ω 5% 1W 2512 VISHAY CRCW2512330RJNEG 230V R1 R2 RES 510Ω 5% 1W 2512 VISHAY CRCW2512510RJNEG 120V RES 430Ω 5% 1W 2512 VISHAY CRCW2512430RJNEG 230V RES 1.6kΩ 5% 1W 2512 VISHAY CRCW25121K60JNEG 120V RES 402kΩ 1% 0.25W 1206 VISHAY CRCW1206402KFKEA 230V RES 953kΩ 1% 0.25W 1206 VISHAY CRCW1206953KFKEA R4 RES 100Ω 1% 1W 2512 VISHAY WSL2512100RFKEA R5 RES 100kΩ 1% 0.1W 0603 VISHAY CRCW0603100KFKEA R6 RES 6.04kΩ 1% 0.1W 0603 VISHAY CRCW06036K04FKEA R7 RES 499kΩ 1% 0.1W 0603 VISHAY CRCW0603499KFKEA R8, R9 RES 75.0kΩ 1% 0.1W 0603 VISHAY CRCW060375K0FKEA RES 20.0kΩ 1% 0.1W 0603 VISHAY CRCW060320K0FKEA RES 1.00MΩ 1% 0.25W 1206 VISHAY CRCW12061M00FKEA RES 2.00MΩ 1% 0.25W 1206 VISHAY CRCW12062M00FKEA R3 R10 R11 120V 230V R12 RES 15.0kΩ 1% 0.1W 0603 VISHAY CRCW060315K0FKEA R13 RES 5.11kΩ 1% 0.1W 0603 VISHAY CRCW06035K11FKEA R14a RES 10Ω 1% 0.25W 1206 VISHAY CRCW120610R0FKEA R14b RES 1.00Ω 1% 0.33W 1210 VISHAY CRCW12101R00FNEA R15a, R15b RES 5.62Ω 1% 0.25W 1206 VISHAY CRCW12065R62FNEA R16 R17 RES 2.00kΩ 1% 0.125W 0805 VISHAY CRCW08052K00FKEA 120V RES 20.0kΩ 1% 0.1W 0603 VISHAY CRCW060320K0FKEA 230V RES 10.0kΩ 1% 0.1W 0603 VISHAY CRCW060310K0FKEA R18 RES 105kΩ 1% 0.125W 0805 VISHAY CRCW0805105KFKEA R19 RES 2.67kΩ 1% 0.1W 0603 VISHAY CRCW06032K67FKEA R20 RES 6.04kΩ 1% 0.125W 0805 VISHAY CRCW08056K04FKEA R21 RES 10.0kΩ 1% 0.125W 0805 VISHAY CRCW080510K0FKEA R22 RES 80.6kΩ 1% 0.1W 0603 VISHAY CRCW060380K6FKEA R23 RES .62Ω 1% 0.5 2010 SMD ROHM MCR50JZHFLR620 R24, R25 R27, R28 RES 10kΩ 1% 0.1W 0603 VISHAY CRCW060310K0FKEA 120V RES 10Ω 10% 2W FILM WELWYN EMC2-10R0 230V RES 22Ω 10% 2W FILM WELWYN EMC2-22R0 OPTO-ISOLATOR SMD LITE ON CNY17F-3S 120V XFORMER 120V 15W OUTPUT 50V WURTH 750813550 230V XFORMER 230V 15W OUTPUT 50V WURTH 750817550 OPTO1, OPTO2 T1 25 LM3450 LM3450A Reference Designator www.national.com LM3450 LM3450A SINGLE STAGE LED DRIVER – LM3450A FLYBACK 30127441 www.national.com 26 LM3450 LM3450A 30W SINGLE STAGE DESIGN SPECIFICATIONS AC Input Voltage: 120VAC nominal (90VAC - 135VAC) or 230VAC nominal (180VAC - 265VAC) Flyback Output Voltage Maximum: 60V Regulated LED Current: 700mA Bill of Materials *Components are used in both versions unless otherwise noted Reference Designator Description Manufacturer Part Number LM3450A IC PFC CONT 16-TSSOP NSC LM3450AMT LMV431 IC SHUNT REG SOT-23 NSC LMV431AIM5 U1 IC DUAL OP-AMP NSC LM2904 120V CAP CER 0.22µF 250V 1210 MURATA GRM32DR72E224KW01L 230V C1a, C1b, C1c, C5a, C5b, C5c CAP CER 68nF 250V 1210 MURATA GRM32QR72E683KW01L C2 CAP MPY 33nF 250VAC X1 RAD EPCOS B32912A3333M C3 CAP CER 47µF 6.3V 0805 TAIYO YUDEN JMK212BJ476MG-T 120V CAP MPY 0.22µF 400V RAD WIMA MKP10-.22/400/20 230V C4 CAP MPY 62nF 1000V RAD VISHAY BFC238330623 C6 CAP CER 4.7nF 500VAC Y1 RAD EPCOS VY1472M63Y5UQ63V0 C7a CAP ELEC 1mF 63V RAD NICHICON UPW1J102MHD C7b, C8b, C9b, C11, C15 CAP CER 0.1µF 50V 1206 MURATA GRM188R71H104KA93D C8a, C9a CAP ELEC 220µF 50V RAD NICHICON UHE1H221MPD C10 CAP CER 10nF 25V 0603 MURATA GRM188R71E103KA01D C12, C13, C14, C18, C19 CAP CER 1µF 16V 0603 MURATA GRM188R71C105KA12D C16 CAP CER 0.22µF 16V 0603 TDK C1608X7R1C224K C17 CAP CER 10µF 16V 1206 MURATA GRM31CR71C106KAC7L 120V DIODE ULTRAFAST 200V 1A SMA FAIRCHILD ES1D 230V DIODE FAST 400V 1A DO-214AC FAIRCHILD ES1G D2 DIODE ULTRAFAST 200V 1A SMA FAIRCHILD ES1D D3, D5 DIODE ULTRAFAST 100V 0.2A SOT-23 FAIRCHILD MMBD914 D1a, D1b D4 DIODE DUAL SCHOTTKY 20V 0.5A SOT-23 NXP SEMI PMEG3005CT,215 120V DIODE TVS 150V 600W UNI SMB LITTLEFUSE SMBJ150A 230V DIODE TVS 220V 600W UNI SMB LITTLEFUSE SMBJ220A D7 DIODE ULTRAFAST 600V 1A SMA FAIRCHILD ES1J D8 DIODE ZENER 24V 1.5W SMA MICRO-SEMI SMAJ5934B-TP D9 DIODE SCHOTTKY 20V 3A SMA FAIRCHILD ES2AA-13-F D10 DIODE RECT 600V 0.5A Minidip COMCHIP HD06 D11, D12 DIODE ZENER 10V 500mW SOD-123 FAIRCHILD MMSZ5240B D13 DIODE ZENER 1.8V 500MW SOD-123 ON-SEMI MMSZ4678T1G D17 DIODE ZENER 3.9V 500MW SOD-123 ON-SEMI MMSZ4686T1G D18 DIODE ZENER 18V 500MW SOD-123 ON-SEMI MMSZ5248T1G D19 DIODE SCHOTTKY 30V 200mA SOT-23 FAIRCHILD BAT54 L1 IND LINE FILTER 6mH 0.3A 11M PANASONIC ELF-11M030E L1, L2, L3 IND SHIELD 1mH 1.18A SMT COILCRAFT MSS1278-105KL L4 IND SHIELD 270µH 2.34A SMT COILCRAFT MSS1278-274KLB Q1 MOSFET N-CH 800V 3A DPAK ST MICRO STD4NK80ZT4 120V MOSFET N-CH 500V 9A DPAK ST MICRO STD11NM50N 230V MOSFET N-CH 800V 6A DPAK INFINEON SPD06N80C3 Q3, Q4 TRANS NPN 40V 0.6A SOT-23 FAIRCHILD MMBT4401 Q6 TRANS NPN 40V 0.2A SOT-23 FAIRCHILD MMBT3904 D6 Q2 27 www.national.com LM3450 LM3450A Reference Designator Description Manufacturer Part Number R1 R2 120V RES 330Ω 5% 1W 2512 VISHAY CRCW2512330RJNEG 230V RES 510Ω 5% 1W 2512 VISHAY CRCW2512510RJNEG 120V RES 430Ω 5% 1W 2512 VISHAY CRCW2512430RJNEG 230V RES 1.6kΩ 5% 1W 2512 VISHAY CRCW25121K60JNEG 120V RES 402kΩ 1% 0.25W 1206 VISHAY CRCW1206402KFKEA RES 953kΩ 1% 0.25W 1206 VISHAY CRCW1206953KFKEA R4 RES 100Ω 1% 1W 2512 VISHAY WSL2512100RFKEA R5 RES 100kΩ 1% 0.1W 0603 VISHAY CRCW0603100KFKEA R6 RES 6.04kΩ 1% 0.1W 0603 VISHAY CRCW06036K04FKEA R7 RES 499kΩ 1% 0.1W 0603 VISHAY CRCW0603499KFKEA R8, R9 RES 49.9kΩ 1% 0.1W 0603 VISHAY CRCW060349K9FKEA R3 230V R10 R11 RES 20kΩ 1% 0.1W 0603 VISHAY CRCW060320K0FKEA 120V RES 1.00MΩ 1% 0.25W 1206 VISHAY CRCW12061M00FKEA 230V RES 2.00MΩ 1% 0.25W 1206 VISHAY CRCW12062M00FKEA R12 RES 15.0kΩ 1% 0.1W 0603 VISHAY CRCW060315K0FKEA R13 RES 5.11kΩ 1% 0.1W 0603 VISHAY CRCW06035K11FKEA R14a, R14b, R23a, R23b, RES 1.00Ω 1% 0.33W 1206 R23c VISHAY CRCW12061R00FKEA R15a, R15b RES 5.62Ω 1% 0.25W 1206 VISHAY CRCW12065R62FKEA R16 RES 1.00kΩ 1% 0.125W 0805 VISHAY CRCW08051K00FKEA RES 30.1kΩ 1% 0.1W 0603 VISHAY CRCW060330K1FKEA RES 15.0kΩ 1% 0.1W 0603 VISHAY CRCW060315K0FKEA R17 120V 230V R18 RES 105kΩ 1% 0.125W 0805 VISHAY CRCW0805105KFKEA R19 RES 2.49kΩ 1% 0.1W 0603 VISHAY CRCW06035K49FKEA R20 RES 6.04kΩ 1% 0.125W 0805 VISHAY CRCW08056K04FKEA R21 RES 10.0kΩ 1% 0.125W 0805 VISHAY CRCW080510K0FKEA R22 RES 1.4kΩ 1% 0.125W 0805 VISHAY CRCW08051K40FKEA R24, R25 R26 R27, R28 RES 10kΩ 1% 0.1W 0603 VISHAY CRCW060310K0FKEA 120V RES 2.49kΩ 1% 0.125W 0805 VISHAY CRCW08052K49FKEA 230V RES 4.99kΩ 1% 0.125W 0805 VISHAY CRCW08054K99FKEA 120V RES 5Ω 10% 3W WIREWOUND VISHAY PAC300005008FAC000 230V RES 10Ω 10% 3W WIREWOUND VISHAY PAC300001009FAC000 R29, R30 RES 4.99kΩ 1% 0.1W 0603 VISHAY CRCW06034K99FKEA R32 RES 909Ω 1% 0.1W 0603 VISHAY CRCW0603909RFKEA OPTO1, OPTO2 OPTO-ISOLATOR SMD LITE ON CNY17F-3S 120V XFORMER 120V 30W OUTPUT 50V WURTH 750813651 230V XFORMER 230V 30W OUTPUT 50V WURTH 750817651 T1 Thermal Protect www.national.com see Dynamic Hold section 28 LM3450 LM3450A Physical Dimensions inches (millimeters) unless otherwise noted TSSOP-16 Pin Package (MTC) For Ordering, Refer to Ordering Information Table NS Package Number MTC16 29 www.national.com LM3450 LM3450A LED Drivers with Active Power Factor Correction and Phase Dimming Decoder Notes For more National Semiconductor product information and proven design tools, visit the following Web sites at: www.national.com Products Design Support Amplifiers www.national.com/amplifiers WEBENCH® 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Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Applications Audio www.ti.com/audio Communications and Telecom www.ti.com/communications Amplifiers amplifier.ti.com Computers and Peripherals www.ti.com/computers Data Converters dataconverter.ti.com Consumer Electronics www.ti.com/consumer-apps DLP® Products www.dlp.com Energy and Lighting www.ti.com/energy DSP dsp.ti.com Industrial www.ti.com/industrial Clocks and Timers www.ti.com/clocks Medical www.ti.com/medical Interface interface.ti.com Security www.ti.com/security Logic logic.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense Power Mgmt power.ti.com Transportation and Automotive www.ti.com/automotive Microcontrollers microcontroller.ti.com Video and Imaging RFID www.ti-rfid.com OMAP Mobile Processors www.ti.com/omap Wireless Connectivity www.ti.com/wirelessconnectivity TI E2E Community Home Page www.ti.com/video e2e.ti.com Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2011, Texas Instruments Incorporated LM3409HV,LM3450,LMV431 Application Note 2150 LM3450A Evaluation Board Literature Number: SNVA485A National Semiconductor Application Note 2150 James Patterson June 21, 2011 Introduction Specifications The LM3450A evaluation board is designed to provide an AC to LED solution for a 30W LED load. Specifically, it takes an AC mains input and converts it to a constant current output of 700mA for a series string of 1 to 13 LEDs (maximum LED stack voltage of 45V). There are two assembly versions designed to operate from two different nominal AC input voltages, 120VAC or 230VAC. The board employs a two stage design with an LM3450A flyback primary stage and an LM3409HV secondary stage. The LM3450A provides an isolated 50V regulated output voltage and a power factor corrected input current. The LM3409HV uses the 50V flyback output as its input and provides a constant current of 700mA to the LED load. This two stage design provides excellent line and load regulation as well as isolation. The board is comprised of two copper layers with components on both sides and an FR4 dielelctric. The two stage design has several key advantages over a single stage design including: • No 120Hz LED current ripple. • Better dimming performance at low dimming levels. • Better line disturbance rejection. • Better efficiency using small LED stack voltages. LM3450A Evaluation Board LM3450A Evaluation Board 120VAC 30W Version • Input Voltage Range: VIN = 90VAC – 135VAC • Regulated Flyback Output Voltage: VOUT = 50V • Maximum LED Stack Voltage: VLED < 45V • Regulated LED Current: ILED = 700mA 230VAC 30W Version • Input Voltage Range: VIN = 180VAC – 265VAC • Regulated Flyback Output Voltage: VOUT = 50V • Maximum LED Stack Voltage: VLED < 45V • Regulated LED Current: ILED = 700mA 30163101 AN-2150 © 2011 National Semiconductor Corporation 301631 www.national.com AN-2150 Typical Performance 120V 30W Version Efficiency vs. Output Power 230V 30W Version Efficiency vs. Output Power 301631a0 301631a1 120V 30W Version Power Factor vs. Output Power 230V 30W Version Power Factor vs. Output Power 301631a2 www.national.com 301631a3 2 AN-2150 Conducted EMI Performance 120V 30W Conducted EMI Peak Scan Line and Neutral - CISPR/FCC Class B Quasi Peak and Average Limits 301631a5 230V 30W Conducted EMI Peak Scan Line and Neutral - CISPR/FCC Class B Quasi Peak and Average Limits 301631a6 3 www.national.com AN-2150 THD / Harmonic Performance 120V 30W THD Measurements EN 61000-3 Class C Limits THD = 6.27% ; Fundamental = 316mA 301631a7 230V 30W THD Measurements EN 61000-3 Class C Limits THD = 8.96% ; Fundamental = 167mA 301631a8 www.national.com 4 AN-2150 LM3450A Pin Descriptions 30163103 Pin Name Description Application Information 1 VREF 3V Reference Reference Output: Connect directly to VADJ or to resistor divider feeding VADJ and to necessary external circuits. 2 VADJ Analog Adjust Analog Dim and Phase Dimming Range Input: Connect directly to VREF to force standard 70% phase dimming range. Connect to resistor divider from VREF to extend usable range of some phase dimmers or for analog dimming. Connect to GND for low power mode. 3 FLT2 Filter 2 Ramp Comparator Input: Connect a series resistor from FLT1 capacitor and a capacitor to GND to establish second filter pole. 4 FLT1 Filter 1 Angle Decoder Output: Connect a series resistor to a capacitor to ground to establish first filter pole. 5 DIM 500 Hz PWM Output Open Drain PWM Dim Output: Connect to dimming input of output stage LED driver (directly or with isolation) to provide decoded dimming command. 6 VAC Sampled Rectified Line Multiplier and Angle Decoder Input: Connect to resistor divider from rectified AC line. 7 COMP Compensation Error Amplifier Output and PWM Comparator Input: Connect a capacitor to GND to set the compensation. 8 FB Feedback Error Amplifier Inverting Input: Connect to output voltage via resistor divider to control PFC voltage loop for non-isolated designs. Connect to a 5.11kΩ resistor to GND for isolated designs (bypasses error amplifier). Also includes over-voltage protection and shutdown modes. 9 ISEN Input Current Sense Input Current Sense Non-Inverting Input: Connect to diode bridge return and resistor to GND to sense input current for dynamic hold. Connect a 0.1µF capacitor and Schottky diode to GND, and a 0.22µF capacitor to HOLD. 10 GND Power Ground System Ground 11 CS Current Sense MosFET Current Sense Input: Connect to positive terminal of sense resistor in PFC MosFET source. 12 GATE Gate Drive Gate Drive Output: Connect to gate of main power MosFET for PFC.Gate Drive Output: Connect to gate of main power MosFET for PFC. 13 VCC Input Supply Power Supply Input: Connect to primary bias supply. Connect a 0.1µF bypass capacitor to ground. 14 ZCD Zero Crossing Detector 15 HOLD Dynamic Hold 16 BIAS Pre-regulator Gate Bias Demagnetization Sense Input: Connect a resistor to transformer/inductor winding to detect when all energy has been transferred. Open Drain Dynamic Hold Input: Connect to holding resistor which is connected to source of passFET. Pre-regulator Gate Bias Output: Connect to gate of passFET and to resistor to rectified AC (drain of passFET) to aid with startup. 5 www.national.com AN-2150 LM3409HV Pin Descriptions 30163104 Pin Name Description Application Information 1 UVLO Input Under Voltage Lock-out Connect to a resistor divider from VIN. UVLO threshold is 1.24V and hysteresis is provided by a 22µA current source. 2 IADJ Analog LED Current Adjust Apply a voltage between 0 - 1.24V, or connect a resistor from this pin to GND, to set the current sense threshold voltage. 3 EN Logic Level Enable 4 COFF Off-time programming 5 GND Power Ground 6 PGATE Gate Drive 7 CSN Negative Current Sense Connect to the negative side of the sense resistor. 8 CSP Positive Current Sense Connect to the positive side of the sense resistor (also connected to VIN). 9 VCC 10 VIN Input Voltage DAP DAP Thermal PAD on bottom of IC www.national.com Apply a voltage >1.6V to enable device, a PWM signal to dim, or a voltage <0.6V for low power shutdown. Connect an external resistor from VO to this pin, and a capacitor from this pin to GND to set the off-time. Connect to the system ground. Connect to the gate of the external PFET. VIN-referenced Linear Regulator Connect at least a 1 µF ceramic capacitor from this pin to CSN. The regulator provides power for P-FET drive. Output Connect to the input voltage. Connect to pin 5 (GND). Place 4-6 vias from DAP to bottom layer GND plane. 6 AN-2150 Simplified Evaluation Board Schematic 30163102 7 www.national.com AN-2150 plified Evaluation Board Schematic. Note that parallel and series resistances are combined in one schematic symbol for simplification. To improve readability of this design document, each sub-section is followed by a list of Definitions for new terms used in the calculations. A Complete Evaluation Board Schematic, showing all components and connectors, is found at the end of this document as well as a Bill of Materials for each assembly version. Design Information The following section explains how to design using the LM3450A power factor controller and phase dimming decoder. Refer to AN-1953 for a detailed design procedure of the LM3409HV secondary stage and to the LM3450/50A Datasheet for specific details regarding the function of the LM3450A device. All reference designators refer to the Sim- 30163107 FIGURE 1. Two-Stage PFC LED Driver The input current shaping happens instantly in CRM due to the feed-forward mechanism; however, the converter must also regulate the flyback output voltage with a traditional feedback loop. This is accomplished with a narrow bandwidth error amplifier coupled with energy storage capacitance at the output to limit the twice line frequency ripple. The output of the error amplifier is multiplied with the scaled rectified AC voltage to achieve both input current shaping and output voltage regulation. Refer to the datasheet for a more detailed explanation of the power factor controller. The LM3450A also has a phase decoder that interprets the phase dimming angle and maps it to a 500Hz PWM opendrain output at the DIM pin. This signal is directly connected to an opto-isolator to send across the isolation boundary to the second stage LED driver. In addition, the LM3450A provides a dynamic hold circuit to ensure that the holding current requirement is satisfied in forward phase dimmers. Refer to the datasheet for a more detailed explanation of the phase dimmer decoder. 1ST STAGE - CRM FLYBACK The first stage of the evaluation board shown in Figure 1 is a critical conduction mode (CRM) flyback converter controlled with the LM3450A. CRM converters operate at the boundary of continuous conduction mode (CCM) and discontinuous conduction mode (DCM). CRM is implemented by turning on the main switching FET (Q3) until the primary current rises to a peak threshold. Q3 is then turned off and the current falls until a zero crossing is detected. At this point, Q3 is turned on and the cycle repeats. In the CRM flyback PFC application, the rectified AC input is fed forward to the control loop, yielding a sinusoidal peak current threshold. This peak threshold creates a sinusoidal primary peak current envelope IP-pk as shown in Figure 2. The secondary peak current envelope IS-pk will simply be a scaled version of the primary according to the turns ratio of the transformer. Assuming good attenuation of the switching ripple via the EMI filter, the average input current IIN(t), shown in red, can also be approximated as a sinusoid. Since the input current has the same shape and phase as the input voltage, high power factor (PF) can easily be achieved. 2ND STAGE - BUCK LED DRIVER The second stage of the evaluation board is a buck LED driver controlled with the LM3409HV. The input to this stage is the flyback output voltage and the output is a regulated constant current of 700mA to a stack of <45V of LEDs. The LM3409HV is a hysteretic PFET controller using peak current detection and a constant off-timer to provide regulated LED current with a constant switching frequency ripple. Coupled with the flyback energy storage capacitance, the LM3409HV is able to remove all 120HZ ripple content from the LED output. The 500Hz PWM signal from the first stage is used as the dimming input to the LM3409HV. The output of the opto-isolator is connected directly to the EN pin of the LM3409HV to provide a PWM dimmed LED current according to the detected phase angle at the primary. The LM3409HV design is not included in this document. Refer to AN-1953 for a detialed design procedure. The specifications for the second stage are: • Nominal Input Voltage = 50V • Regulated LED Current = 700mA • Nominal LED Stack Voltage = 45V • Switching Frequency at Nominal Input = 100kHz • Inductor/LED Current Ripple = 115mA 30163108 FIGURE 2. CRM Flyback Current Waveforms www.national.com 8 Switching MosFET The main switching MosFET (Q3) can be sized as desired; to block the maximum drain-to-source voltage, operate at the maximum RMS current, and dissipate the maximum power: The controller and the transformer are also assumed to be ideal. These assumptions yield a sinusoidal peak primary current envelope IP-pk(t) and peak secondary current envelope IS-pk(t) as shown in Figure 2. Both are defined in terms of the peak primary current: The peak current limit should be at least 25% higher than the maximum peak input current: The parallel sense resistor combination (R30||R31) has to dissipate the maximum power: The output voltage reflected to the primary is defined: Switching Diode The main switching diode (D10) should be sized to block the maximum reverse voltage , operate at the maximum average current, and dissipate the maximum power: CRM control yields a variable duty cycle over a single line cycle with a minimum occurring at the peak input voltage: The resulting sinusoidal average input current Iin(t), shown in Figure 2, is approximated as the average of each triangular current pulse during a switching period. The peak input current occurs at the peak primary current: Definitions n – Primary to Secondary Turns Ratio VOUT – Regulated Output Voltage VIN – Nominal AC Input Voltage VIN-PK – Peak Input Voltage VIN-PK-MAX – Maximum Peak Input Voltage IP-PK – Peak Primary Current IS-PK – Peak Secondary Current IIN-PK – Peak Input Current ILIM – Peak Current Limit DMIN – Minimum Duty Cycle over Line Cycle VR – Output Voltage Reflected to Primary VR-MAX – Maximum Tolerable Reflected Voltage VT-DES-MAX – Maximum Tolerable MosFET Voltage VT-MAX – Maximum MosFET Blocking Voltage IT-RMS-MAX – Maximum MosFET RMS Current IT-PK-MAX – Maximum MosFET Peak Current PT-MAX – Maximum MosFET Power Dissipation VRD-MAX – Maximum Diode Blocking Voltage ID-MAX – Maximum Diode Average Current ID-PK-MAX – Maximum Diode Peak Current PD-MAX – Maximum Diode Power Dissipation Turns Ratio The first thing to decide with an isolated design is the desired transformer turns ratio. This should be based on the specified output voltage and the maximum peak input voltage. Frequently the MosFET is already chosen for a design, given its cost and availability. With a desired MosFET voltage, the maximum reflected voltage at the primary is calculated: Generally, an integer turns ratio is selected to achieve a reflected voltage at or below the defined maximum: 9 www.national.com AN-2150 CRM FLYBACK CONVERTER Operating Points The AC mains voltage, at the line frequency fL, is assumed to be perfectly sinusoidal and the diode bridge ideal. This yields a perfect rectified sinusoid at the input to the flyback. The input voltage Vin(t) is defined in terms of the peak input voltage: AN-2150 Given the switching frequency range and the maximum output power, a core size can be chosen using the vendor’s specifications and recommendations. This choice can then be validated by calculating the maximum operating flux density given the core cross-sectional area of the chosen core. TRANSFORMER Primary Inductance The maximum peak input current, occuring at the minimum AC voltage peak, determines the necessary flyback transformer energy storage. As a general rule of thumb, the desired duty cycle at this worst-case operating point should be specified near 0.5 to limit large conduction losses associated with high voltage diodes. The maximum input current can be approximated by the maximum output power, expected converter efficiency, and minimum input voltage. Note that there is also a 0.85 multiplier to account for the fact that maximum power with a triac dimmer in-line is demanded at approximately 85% of the full sinusoidal voltage waveform. Given the desired duty cycle, the maximum peak input current and corresponding maximum peak primary current can be approximated: With most common core materials, the maximum operating flux density should be set between 300mT and 3400mT. If the calculation is below this range, then AL should be increased to the next standard value and the turns and maximum flux density calculations iterated. If the calculation is above this range, then AL should be decreased to the next standard value and the turns and maximum flux density calculations iterated. With the flux density appropriately set, the core material for the chosen core size can be determined using the vendor’s specifications and recommendations. Note that there are core materials that can tolerate higher flux densities; however, they are usually more expensive and not always practical for these designs. The rest of the transformer design should be done with the aid of the manufacturer. There are calculated trade-offs between the different loss mechanisms and safety constraints that determine how well a transformer performs. This is an iterative process and can ultimately result in the choice of a new core or switching frequency range. The previous steps should reduce the number of iterations significantly but a good transformer manufacturer is invaluable for completion of the process. Definitions Using the calculated turns ratio and the desired minimum switching frequency, the minimum necessary primary inductance is calculated: Switching Frequency Range Given a primary inductance that meets the above constraint, the variable switching frequency has the following limits: η – Expected converter efficiency POUT-MAX – Maximum Output Power VIN-MIN – Minimum RMS AC Line Voltage VIN-PK-MIN – Minimum Peak Input Voltage IIN-PK-MAX – Maximum Peak Input Current IP-PK-MAX – Maximum Peak Primary Current D@IIN-PK-MAX – Duty Cycle at Maximum Peak Input Current LP-MIN – Minimum Necessary Primary Inductance LP – Chosen Primary Inductance fSW-MIN-DES– Desired Minimum Switching Frequency fSW-MIN – Minimum Switching Frequency fSW-MAX – Maximum Switching Frequency NP – Number of Primary Turns NS – Number of Secondary Turns AE-MAX – Core Cross-Sectional Area BMAX – Maximum Operating Flux Density AL – Transformer Core Figure of Merit Transformer Geometries and Materials The length of the gap necessary for energy storage in the flyback transformer can be determined numerically; however, this can lead to non-standard designs. Instead, an appropriate AL core value (160nH/turns2 is a good standard value to start with) can be chosen that will imply the gap size. AL is an industry standard used to define how much inductance, per turns squared, that a given core can provide. With the initial chosen AL value, the number of turns on the primary and secondary are calculated: www.national.com 10 AN-2150 30163133 FIGURE 3. Bias Circuitry BIAS SUPPLIES & CAPACITANCES Bias Supplies The primary bias supply shown in Figure 3 enables instant turn-on through Q1 while providing an auxiliary winding for high efficiency steady state operation. The two bias paths are each connected to VCC through a diode (D8, D9) to ensure the higher of the two is providing VCC current. The LM3450A BIAS pin helps to ensure that the auxiliary winding is always providing VCC during normal operation. Since there is optical isolation, a secondary bias supply is also desirable. This is accomplished with another auxiliary winding, diode (D4), and capacitance (C4, C5) which creates another flyback output that scales with the regulated output (similar to the auxiliary primary bias winding). To ensure secondary bias regulation is closely coupled to the regulated flyback output, the output winding is tapped to provide the secondary bias output. It is also advantageous to linear regulate down to approximately 9V, from the 12V bias supplies, for every opto-isolator supply rail (VPOP1, VOP1, VOP2) . This will stabilize the optoisolator rail over the entire operating range, preventing noise coupling into COMP and the dimming input of the LM3409. The primary and secondary bias outputs for both versions of the board are set to 12.5V at the nominal input voltage. The turns calculations (referred to the output) for the primary auxiliary winding and the tap point for the secondary winding are: Input Capacitance The input capacitor of the flyback (C1), also called the PFC capacitor, has to be able to provide energy during the worstcase switching period at the peak of the AC input. C1 should be a high frequency, high stability capacitor (usually a metallized film capacitor, either polypropylene or polyester) with an AC rating equal to the maximum input voltage. C1 should also have a DC voltage rating exceeding the maximum peak input voltage + half of the peak to peak input voltage ripple specification. The minimum required input capacitance is calculated given the same ripple specification: Output Capacitance Since the LM3450A is a power factor controller, C1 is minimized and the output capacitor (C11) serves as the main energy storage device. C11 should be a high quality electrolytic capacitor that can tolerate the large current pulses associated with CRM operation. The voltage rating should be at least 25% greater than the regulated output voltage and, given the desired voltage ripple, the minimum output capacitance is calculated: Definitions ΔvIN-PK – Peak Input Voltage Switching Ripple ΔvOUT – Nominal Output Voltage Ripple ΔvCC – Nominal Primary Bias Ripple VCC – Primary Bias Capacitance nAUX – Output to Auxiliary Turns Ratio NA – Number of Auxiliary Turns f2L – Twice Line Frequency The minimum primary bias supply capacitance is calculated, given a minimum VCC ripple specification, to keep VCC above UVLO at the worst-case current: 11 www.national.com AN-2150 30163140 FIGURE 4. Dynamic Hold Circuit with Thermal Protection ure 5 can be used to find the maximum IIN-MIN-REG for the desired minimum output power level. The minimum output power is defined as the output power that causes the dynamic hold to force approximately 1W of power dissipation in Q1 (causing approximately 100°C rise in a DPAK). Below the minimum output power level, Q1 can reach temperatures exceeding 125°C, depending on the conduction angle, causing potential catastrophic failure. Figure 5 is only a general guideline based on experimental testing of this evaluation board. Each application will have a different passFET thermal characteristic, which suggests thermal protection of the passFET is usually necessary. HOLD CURRENT Dynamic Hold The LM3450A regulates the minimum input current with a dynamic hold circuit to ensure the triac holding current requirement is satisfied. The regulated minimum current is set by choosing the sense resistor (R34||R36): The maximum possible holding current (usually occurs during transients when triac fires) is set by choosing the hold resistor (R12||R14||R15) between the source of the Q1 and HOLD: MIN OUTPUT POWER (W) 36 PassFET The passFET (Q1) is used in its linear region to stand-off the line voltage from the LM3450A controller. Both the VCC startup current and the triac holding current are conducted through the device. Since the holding current is far larger than the startup current and is dynamically adjusted every cycle, it will dominate the calculations. Given this, Q1 is chosen to block the maximum peak input voltage and conduct the maximum holding current. The surge handling capability of Q1 is also important and is evaluated by looking at the safe operating area (SOA) of the device. Finally, Q1 needs to be able to dissipate the maximum power. Looking at an absolute worst-case condition for the Q1 (during open load where the converter draws near-zero power), extremely large power dissipation is required (many Watts). Designing for this case is unrealistic and costly. Instead, Fig- www.national.com 30 230VAC 24 18 12 6 120VAC 0 40 45 50 55 60 65 70 REGULATED MIN INPUT CURRENT (mA) 301631b4 FIGURE 5. Output Power Restrictions (without thermal protection) 12 13 www.national.com AN-2150 effectively reducing the maximum attainable holding current. Placement of R44 is critical to ensure the best possible thermal coupling to Q1. The drain of Q1 will have the highest temperature rise but it is at a much higher voltage than the source where R44 is electrically connected. Because of this, the best placement for R44 is on the other side of the PCB, directly under the drain of Q1. The dielectric of the PCB provides adequate electrical insulation while yielding the best thermal coupling. Obviously, R44 placement in potted solutions is much more forgiving. A 10kΩ NTC is suggested for R44 and Q11 can be a basic PNP (i.e. MMBT3906). R45 has to be sized experimentally since the thermal coupling will vary with each PCB layout. A good starting point for R45 is 15kΩ. Definitions IIN-MIN-REG – Regulated Minimum Input Current IHOLD-MAX – Maximum Hold Current Thermal Protection Using the previously mentioned design methodology, thermal protection is indeed necessary for the open load condition and for power levels below the specified operating range shown in Figure 5. The thermal protection circuit shown in Figure 4 will reduce the maximum holding current when the temperature rises too high, thus preventing catastrophic failure of Q1. Keep in mind that the thermal foldback does not prevent the circuit from operating, it simply reduces the amplitude of the dynamic hold. The only negative effect of the thermal protection is a possible reduction in contrast ratio, meaning the minimum attainable output current potentially increases as the dynamic hold level decreases. The thermal protection is accomplished using a PNP transistor (Q11) and a resistor divider comprised of a fixed resistor (R45) and an NTC thermistor (R44). As Q1 heats up, R44 decreases causing the collector voltage of Q11 to decrease, AN-2150 301631b3 FIGURE 6. Dimming Decoder Circuit DIMMING DECODER Angle Sense VAC is a dual input for both the PFC multiplier and the angle decoder. The resistor divider (R26+R29, R32) should be sized according to the desired angle detect voltage VDET. A general rule of thumb is to set VDET = VIN-PK/x where x is a value between 4 and 7. R26+R29 should be chosen to be between 1MΩ and 2MΩ to limit power dissipation. LM3409HV EN PIN DUTY CYCLE 1.2 VADJ=3V 2.5V 0.8 0.6 0.4 2V 1.5V 1V 0.2 0.0 Decoder Mapping The mapping from the demodulated input (VAC pin of the LM3450A) to output (EN pin of the LM3409HV) is shown in Figure 7. Varying VADJ will adjust the mapping as desired for the target dimmers. Keep in mind that the demodulated input angle is a function of the resistor divider at the VAC pin. This means that the input duty cycle can be shifted by changing VDET within the previously suggested range. Filters The filters (FLT1, FLT2) are chosen to provide the desired dimming transition response (how the light changes during dimmer movement). The filter frequency should be set between 2Hz and 10Hz for best operation (2Hz has a fade feeling, 10Hz is very snappy). The capacitors (C17, C18) can both be set to 1µF for all designs and given the filter frequencies, the resistors (R24, R25) are calculated: www.national.com 1.0 0.5V 0.0 0.2 0.4 0.6 0.8 1.0 LM3450A DEMODULATED VAC PIN DUTY CYCLE 301631b2 FIGURE 7. Dimming Decoder Mapping Opto-Isolator A standard low cost opto-isolator (same type used for feedback of the output) is used to transfer the dimming command from DIM to the secondary. It needs to be driven with at least 1-2mA of current to obtain full 70:1 contrast ratio (more current creates faster edges). With VPOP2 = 9V and R16 = 6.04kΩ, there is > 1mA of drive current. The output of the opto-isolator should be clamped to just above the dimming input threshold of the secondary driver. This is accomplished with a 1.8V Zener clamp (D22) at the EN pin of the LM3409HV on the evaluation boards. R71 needs to be large enough that the Zener clamp is activated whenever the LM3409HV EN pin should be high. Definitions VDET – Rectified AC Angle Detect Voltage fFLT1 – FLT1 frequency fFLT2 – FLT2 frequency 14 AN-2150 30163131 FIGURE 8. Control Loop Block Diagram A standard PI compensator is used on the secondary to stabilize the system. The error amplifier is implemented with an LMV431 and a series resistor (R77) and capacitor (C35) in the feedback path as shown in Figure 9. The output of the LMV431 is tied to the cathode of the opto photo-diode. A resistor (R70 = 2kΩ) from the anode of the photodiode to the bias rail provides the current path and ultimately the output voltage swing of the secondary error amplifier. The primary side of the opto is connected directly to COMP. With the 5kΩ internal pull-up resistor, the maximum current through the primary side of the opto will be 1mA. A higher frequency roll-off pole is placed on the primary in the form of a capacitor (C24) from COMP to GND. The resistor divided flyback output voltage is regulated to the 1.24V LMV431 internal reference. Note the additional soft-start circuit using C34, D13, and D14. VOLTAGE CONTROL LOOP The CRM topology requires a narrow bandwidth voltage control loop to regulate the output voltage. This loop needs to be compensated to maintain stability over the desired operating range. The flyback topology is isolated, therefore the LM3450A internal error amplifier is bypassed and an external secondary side error amplifier is used instead. The control loop shown in Figure 8 is comprised of the converter controlto-output transfer function, the compensator transfer function, and all of the other gains in the loop. The output voltage is sensed with a resistor divider (R81, R72) and regulated to 1.24V using an LMV431: The converter control-to-output transfer function can be approximated as a single pole system: The feedback gain (HFB) is unity due to the control implementation and the LM3450A device and external gains are defined: 30163132 FIGURE 9. Secondary Error Amplifier Circuit 15 www.national.com AN-2150 compensator calculated in the Design Calculations section is sized to be stable and have a bandwidth of around 50-60Hz. This is a fairly high bandwidth for a PFC converter which will cause there to be some 120Hz ripple on COMP. This will decrease PF but improve transient response which is very helpful in phase dimmable applications. Since it is usually desirable to maximize bandwidth (within the PFC limitation), there is a simple method to adjust the R77 value. Measure the twice-line frequency ripple on COMP. If the ripple is less than 200-300mV, increase R77 until it is within that range. If the ripple is larger, then decrease R77 until it is within that range. This will result in a very small PFC degradation, while maximizing bandwidth of the control loop. The compensator transfer function is defined: Where the secondary compensator pole is defined: STARTUP When using the LM3450A with a phase dimmer, startup can be very disruptive. Any time the dimmer is turned on (via a separate switch or some state where the dimmer has been previously disconnected from its load), the LM3450A will attempt to bring the system to regulation. Because phase dimmers can be turned on and off quickly, the system capacitances may or may not be fully discharged, this can lead to a large variance in startup conditions. The best way to control startup transients is to softstart the dimming command and the PFC control simultaneously. This can be accomplished with the circuit shown in Figure 10. D20 is a dual common cathode schottky with very low forward voltage to allow COMP and VADJ to be pulled as close to zero as possible. The softstart time constant is set by C12 and R20. Q4, R21, and D21 form a reset circuit for C12. Since BIAS transitions to 20V whenever VCC hits the falling UVLO threshold and D21 is an 18V Zener, the base of Q4 will go high turning on Q4 and immediately resetting the capacitor to 0V. Then when VCC reaches the UVLO rising threshold and BIAS transitions to 14V, Q4 turns off and softstart is active again. And the compensator zero is defined: And the primary roll-off pole is defined: The resulting control loop gain is The compensator design for this system can be complicated; however with some useful assumptions, it can be simplified. Looking at the total DC gain (G3450xGC0xHFB), the following can be made relatively constant over all designs: • R70 = 2kΩ, the 5kΩ internal pull-up, and the 0.55 multiplier gain. • The opto CTR, though variable over temperature, given a fixed supply rail and a fixed R70 value. In several cases, the product of two DC gain terms can also be identified as relatively constant over all designs if all of the previous LM3450A design methodology is observed: • VINPK and KV are almost exactly inversely proportional (given x remains constant when solving VDET = VIN/x). • IP-PK and R30||R31 are closely inversely proportional (given current limit is a constant percentage above IP-PK ). Given these relationships and following the complete LM3450A design method, the DC gain should only vary largely with change in output voltage (directly proportional). The output pole of the converter on the other hand follows these basic relationships: • POUT-MAX and C11 are exactly directly proportional given a constant output ripple specification, therefore there is no relative change to ωP1. • VOUT is exactly inversely proportional to ωP1 given a constant output ripple specification. With the opposing conditions of the output pole moving inversely proportional to VOUT and the DC gain moving proportional to VOUT, the net result gives a very consistent uncompensated loop gain. Because of this, the exact compensator on this evaluation board can be a starting point for any LM3450A design. During prototyping, If stability becomes a concern, the R77 value can be changed to improve stability. In general the www.national.com 30163139 FIGURE 10. Primary Soft-start Circuit Relevant Definitions GVC(s) – Converter Control-to-Output Transfer Function GC0 – Converter Control-to-Output DC Gain G3450 – LM3450A and External Gains GCOMP(s) – Compensator Transfer Function HFB – Feedback Gain ωP1 – Converter Output Pole ωP2 – Compensator Secondary Integrator Pole ωZ1 – Compensator Secondary Zero ωP3 – Compensator Primary HF Pole T(s) – Total Loop Gain 16 AN-2150 30163137 FIGURE 11. Input EMI Filter sure. C26 will greatly help reduce radiated EMI; however, reduction of dV/dt on switching edges and PCB layout iterations are frequently necessary as well. Consult available literature and/or an EMI specialist for help with this. It can be a daunting task. Interaction with Dimmers In general, input filters and forward phase dimmers do not work well together. The triac needs a minimum amount of holding current to function. The converter itself is demanding a certain amount of current from the input to provide to its output. With no filter, the difference of the necessary hold current and the converter current is provided by the LM3450A dynamic hold circuit. Unfortunately, the actual dimmer current is not being monitored; instead a filtered version is being measured. In reality, the input filter is providing or taking current depending upon the dV/dt of the capacitors. The discrepancy between the measured input current at ISEN and the actual input current through the triac is the worst at the highest dV/dt of the input filter capacitors. The best way to deal with this problem is to minimize filter capacitance and increase the regulated hold current until there is enough current to satisfy the dimmer and filter simultaneously. Figure 11 shows one effective way to improve the dynamic hold functionality when using an EMI filter. The hold current path through the passFET is derived between the two filter stages. In this configuration, the measured input current has only one stage of filtering capacitance to contribute to the descrepancy between measured and actual input current. In addition, the damping network for the C7 capacitor is directly connected to the dynamic hold point of the rectified AC (passFET drain). This, combined with the filter stage between the passFET and the transformer, help attenuate any unwanted switching frequency coupling into the dynamic hold circuit. This configuration also provides some extra filtering of the feedforward VAC signal, which is now derived at the same point as the dynamic hold. One important addition to this EMI filter is a back-to-back TVS clamp across L2. During transient conditions, if the L2 filter rings too much, the current will try to change directions. There is no continuous path for current at the passFET drain, therefore the voltage can rise uncontrolled and damage the passFET. A 20V back-to-back TVS is sufficient to provide this protection. INPUT FILTER Background Since the LM3450A is used for AC to DC systems, electromagnetic interference (EMI) filtering is critical to pass the necessary standards for both conducted and radiated EMI. This filter will vary depending on the output power, the switching frequencies, and the layout of the PCB. There are two major components to EMI: differential noise and commonmode noise. Differential noise is typically represented in the EMI spectrum below approximately 500kHz while commonmode noise shows up at higher frequencies. Conducted Figure 11 shows a typical filter used with an LM3450A design. To conform to conducted standards, a fourth order filter (two second order stages) is implemented using shielded inductors (L1, L2, L4), an EMI suppression X1/X2 film capacitor (C7), and a pulse-rated film capacitor (C1) which is also the primary PFC capacitor sized previously. In addition to the basic filter components, damping is used to prevent excitation of the resonant frequencies of the filter itself. The best practice for damping an EMI filter is to use an RC damper network across each filter capacitor. The C of the damper should be set to be 3 times the filter capacitor value. This EMI filter, if sized properly, can provide ample attenuation of the switching frequency and lower order harmonics contributing to differential noise. The filter can be described as follows: • Stage 1 pole: L1+L4 and C7 gives 40db/decade roll-off Stage 1 damping: C8||C9||C30 and R8||R9||R56 • Stage 2 pole: L2 and C1 gives 40db/decade roll-off Stage 2 damping: C2||C3||C66 and R2||R3||R47 Since L1 and L4 are symmetrically placed in both the line and neutral legs of the AC line, they help to reduce common-mode noise also. It is sometimes necessary to place a high value resistance (R48, R51, R62) across each inductor to prevent excitation of the SRF of the inductor which is usually at higher frequencies. A Y1/Y2 film capacitor (C26) from the primary ground to the secondary ground is also commonly used for reduction of common mode noise. Radiated Conforming to radiated EMI standards is much more difficult and is dependent on the entire system including the enclo- 17 www.national.com AN-2150 INRUSH LIMITING, DAMPING & CLAMPING Clamp In any flyback converter there exists large ringing (VRING) on the Q3 drain, as shown in Figure 13. This is due to the rising edge of the Q3 drain after turn-off, which excites the resonance created by the leakage inductance of the transformer and output capacitance of Q3. A clamp circuit is necessary to prevent damage to Q3 from excessive voltage. The evaluation boards use a transil (TVS) clamp, shown in Figure 12 30163134 FIGURE 13. Switch Node Ringing Inrush With a forward phase dimmer, a very steep rising edge causes a large inrush current every cycle as shown in Figure 14. Series resistance (R39, R57) can be placed between the filter and the triac to limit the effect of this current on the converter. This will, of course, degrade efficiency but some inrush protection is also necessary in any AC system due to startup. The size of R39 and R57 are best found experimentally as they provide attenuation for the whole system. The inrush spike excites resonance(s) of the input filter, which can cause the current to ring negative, as shown in Figure 14, thereby shutting off the triac. The RC damper of the first stage of the input filter should be increased to dampen the worst-case ringing energy due to this edge. This can require a significant increase in capacitance depending upon the dimmer tested (more than 10x the filter capacitance). The resistance is then experimentally changed to create a ringing waveform that is most contained. The objective is to prevent the input current ringing from crossing the minimum regulated holding current thereby preventing misfires. 30163135 FIGURE 12. Transil Clamp When Q3 is on and the drain voltage is low, the blocking diode (D5) is reverse biased and the clamp is inactive. When the MosFET is turned off, the drain voltage rises past the nominal voltage (reflected voltage plus the input voltage). If it reaches the TVS clamp voltage + the input voltage, the clamp prevents any further rise. The TVS diode (D1) voltage is set to prevent the MosFET from exceeding its maximum rating: This clamp method is fairly efficient and very simple compared to other commonly used methods. Note that if the the ringing is large enough that the clamp activates, the ringing energy is radiated at higher frequencies. Depending on PCB layout, EMI filtering method, and other application specific items, the transil clamp can present problems conforming to radiated EMI standards. If the transil clamp becomes problematic at higher frequencies, an RCD clamp can be used to dampen the ringing. Looking at the EMI Performance section, it is obvious that the evaluation board fails near 30MHz. This would indicate an RCD clamp is indeed necessary for this design. C29 and R49, shown on the Complete Evaluation Board Schematic can be populated as desired to improve the EMI signature. This will degrade efficiency some. 30163138 FIGURE 14. Inrush Current Spike www.national.com 18 AN-2150 MAIN SWITCHING MOSFET Maximum drain-to-source voltage: Design Calculations - 120V, 30W The following is a step-by-step procedure with calculations for the 120V 30W Evaluation Board. The 230V calculations can be done in the same manner. Many components are identical between both boards for simplicity, therefore some components on the 120V board are over-sized. Maximum peak MosFET current: SPECIFICATIONS fL – 60Hz fSW-MIN– 45kHz VIN – 120VAC VIN-MIN – 90VAC VIN-MAX – 135VAC ILED – 700mA Maximum RMS MosFET current: Maximum power dissipation: ΔvOUT = 2V ΔvIN-PK = 60V IP-PK-LIM = 3A VT-DES-MAX = 400V POUT-MAX = 30W D@IIN-MAX-PK = 0.5 VOUT = 50V Resulting component choice: η=0.9 RE-CIRCULATING DIODE Maximum reverse blocking voltage: PRELIMINARY CALCULATIONS Maximum peak input voltage: Minimum peak input voltage: Maximum peak diode current: Maximum average input current: Maximum average diode current: Maximum power dissipation: Maximum peak input current: Resulting component choice: Maximum peak primary current: 19 www.national.com AN-2150 CURRENT SENSE Sense resistor: TRANSFORMER Maximum acceptable reflected voltage: Power dissipation: Primary to secondary turns ratio: Resulting component choice: Actual reflected voltage: INPUT CAPACITANCE Minimum capacitance: Primary to auxiliary turns ratio: Transformer primary inductance: Voltage rating: Resulting component choice: Number of primary turns: OUTPUT CAPACITANCE Minimum capacitance: Number of secondary turns: Voltage rating: Number of auxiliary turns: Resulting component choice: Maximum flux density: Resulting component choice: www.national.com 20 OUTPUT VOLTAGE SENSE Resistance: Resulting component choice: Resulting component choice: DYNAMIC HOLD ISEN sense resistance: AN-2150 TRANSIL CLAMP TVS clamp voltage: LOOP COMPENSATION Converter output pole: HOLD resistance: Converter DC gain: Resulting component choice: LM3450A and external sensing DC gain: DECODER INPUT Resistor divider: Secondary compensator dominant pole: Resulting component choice: Secondary compensator zero: Primary roll-off pole: Resulting component choice: 21 www.national.com AN-2150 Complete Evaluation Board Schematic 30163199 www.national.com 22 AN-2150 120V Bill of Materials Reference Designator Part Value Manufacturer Part Number C1 CAP MPY 0.22µF 400V RAD WIMA MKP10-.22/400/20 C2, C3, C8, C9, C30, C66 CAP CER 0.22µF 250V RAD TDK FK20X7R2E224K C4, C44 CAP ELEC 220µF 35V RAD NICHICON UHE1V221MPD C5, C23, C42, C46 CAP CER 0.10µF 25V 0603 MURATA GRM188R71E104KA01D C7 CAP MPY 33nF 330VAC X1 RAD EPCOS B32912A3333M C11 CAP ELEC 1000µF 63V RAD NICHICON UPW1J102MHD6 C12 CAP CER 47µF 6.3V 1206 MURATA GRM31CR60J476ME19L C13, C34, C47 CAP CER 1µF 100V 1206 TDK C3216X7R2A105M C17, C18, C24, C36 CAP CER 1µF 16V 0603 MURATA GRM188R71C105KA12D C21, C43 CAP CER 10nF 25V 0603 MURATA GRM188R71E103KA01D C22 CAP CER 0.22µF 16V 0603 TDK C1608X7R1C224K C26 CAP CER 4.7nF 500VAC Y1 RAD EPCOS VY1472M63Y5UQ63V0 C35 CAP CER 10µF 16V 1206 MURATA GRM31CR71C106KAC7L C37 CAP CER 0.10µF 50V 0603 MURATA GRM188R71H104KA93D C38 CAP CER 2.2µF 6.3V 0603 TDK C1608X5R0J225M C39 CAP CER 470pF 100V 0603 TDK C1608C0G2A471J D1 DIODE TVS 150V 600W UNI SMB LITTLEFUSE SMBJ150A D2, D3, D6, D7 DIODE GEN PURPOSE 1000V 1A SMA COMCHIP CGRA4007-G D4, D9 DIODE ULTRAFAST 100V 0.2A SOT-23 FAIRCHILD MMBD914 D5 DIODE ULTRAFAST 600V 1A SMA FAIRCHILD ES1J D8, D10, D23 DIODE ULTRAFAST 200V 1A SMA FAIRCHILD ES1D D11, D12, D18 DIODE ZENER 10V 500mW SOD-123 FAIRCHILD MMSZ5240B D13 DIODE ULTRAFAST 70V 0.2A SOT-23 FAIRCHILD BAV99 D14 DIODE ZENER 3.3V 500mW SOD-123 ON-SEMI MMSZ3V3T1G D15 DIODE SCHOTTKY 60V 2A SMB ON-SEMI SS26T3G D16 DIODE ZENER 24V 1.5W SMA MICRO-SEMI SMAJ5934B-TP D17 DIODE SCHOTTKY 50V 3A SMA FAIRCHILD ES2AA-13-F D20 DIODE SCHOTTKY (DUAL) 30V 0.5A SOT-23 DIODES INC PMEG3005CT,215 D21 DIODE ZENER 18V 500MW SOD-123 FAIRCHILD MMSZ5248B D22 DIODE ZENER 1.8V 500MW SOD-123 ON-SEMI MMSZ4678T1G D24 DIODE ZENER 3.9V 500MW SOD-123 ON-SEMI MMSZ4686T1G D25 DIODE TVS 20V 400W BIDIR SMA LITTLEFUSE SMAJ20CA F1 FUSE 500mA T-LAG RST BEL FUSE RST 500 J1, J2 CONN HEADER 2x1 VERT AMP 1-1318301-2 L1, L2, L4 IND SHIELD 1mH 1.14A SMT COILCRAFT MSS1278-105KL L3 IND SHIELD 270µH 2.18A SMT COILCRAFT MSS1278-274KL Q1 MOSFET N-CH 800V 3A DPAK ST MICRO STD4NK80ZT4 Q2, Q6, Q8 TRANS NPN 40V 0.6A SOT-23 FAIRCHILD MMBT4401 Q3 MOSFET N-CH 500V 9A DPAK ST MICRO STD11NM50N Q4 TRANS NPN 40V 0.2A SOT-23 FAIRCHILD MMBT3904 Q7 MOSFET P-CH 70V 5.7A DPAK ZETEX ZXMP7A17K Q11 TRANS PNP 40V 0.2A SOT-23 FAIRCHILD MMBT3906 R1, R18, R32, R58 RES 10kΩ 1% 0.1W 0603 VISHAY CRCW060310K0FKEA R2, R3, R8, R9, R47, R56 RES 820Ω 5% 1W 2512 VISHAY CRCW2512820RJNEG R5, R7 RES 200kΩ 1% 0.25W 1206 VISHAY CRCW1206200KFKEA R6, R11 RES 10Ω 1% 0.25W 1206 VISHAY CRCW120610R0FKEA R10 RES 40.2Ω 1% 0.25W 1206 VISHAY CRCW120640R2FKEA R12, R14, R15 RES 301Ω 1% 0.25W 1206 VISHAY CRCW1206301RFKEA 23 www.national.com AN-2150 R16 RES 6.04kΩ 1% 0.125W 0805 VISHAY CRCW08056K04FKEA R17 RES 100kΩ 1% 0.1W 0603 VISHAY CRCW0603100KFKEA R19, R41, R43, R61, R73 RES 0Ω 5% 0.1W 0603 VISHAY CRCW06030000Z0EA R20 RES 499kΩ 1% 0.1W 0603 VISHAY CRCW0603499KFKEA R21, R69 RES 20.0kΩ 1% 0.1W 0603 VISHAY CRCW060320K0FKEA R23 RES 6.04kΩ 1% 0.1W 0603 VISHAY CRCW06036K04FKEA R24, R25 RES 75.0kΩ 1% 0.1W 0603 VISHAY CRCW060375K0FKEA R26, R29 RES 499kΩ 1% 0.25W 1206 VISHAY CRCW1206499KFKEA R28 RES 10Ω 1% 0.125W 0805 VISHAY CRCW080510R0FKEA R30, R31, R65, R66, R83 RES 1.00Ω 1% 0.25W 1206 VISHAY CRCW12061R00FKEA R34, R36 RES 5.62Ω 1% 0.25W 1206 VISHAY CRCW12065R62FKEA R38 RES 5.11kΩ 1% 0.1W 0603 VISHAY CRCW06035K11FKEA R39, R57 RES 5Ω 1% 3W WIREWOUND VISHAY PAC300005008FAC000 R44 THERM 10kΩ NTC 0603 MURATA NTCG163JF103F R45 RES 15.0kΩ 1% 0.1W 0603 VISHAY CRCW060315K0FKEA R46 RES 5.11kΩ 1% 0.125W 0805 VISHAY CRCW08055K11FKEA R48, R51, R62 RES 20.0kΩ 1% 0.25W 1206 VISHAY CRCW120620K0FKEA R55 RES 51.1kΩ 1% 0.25W 1206 VISHAY CRCW120651K1FKEA R70 RES 2.00kΩ 1% 0.125W 0805 VISHAY CRCW08052K00FKEA R71 RES 10.0kΩ 1% 0.125W 0805 VISHAY CRCW080510K0FKEA R72 RES 105kΩ 1% 0.125W 0805 VISHAY CRCW0805105KFKEA R77 RES 30.1kΩ 1% 0.1W 0603 VISHAY CRCW060330K1FKEA R81 RES 2.67kΩ 1% 0.1W 0603 VISHAY CRCW06032K67FKEA R84 RES 49.9kΩ 1% 0.1W 0603 VISHAY CRCW060349K9FKEA T1 XFORMER 120V 30W OUTPUT 50V WURTH 750813651 U1 IC PFC CONT 16-TSSOP NSC LM3450AMT U8, U9 OPTO-ISOLATOR SMD LITE ON CNY17F-3S U10 IC SHUNT REG SOT-23 NSC LMV431AIM5 U11 IC LED DRIVR 10-eMSOP NSC LM3409HVMY C10, C14, C20, C25, C28, Did not populate C29, C31, C40, Q20, R4, R13, R22, R27, R33, R40, R42, R49, R54, R59, R60, R63, R64, R75, R78, VR1 www.national.com 24 AN-2150 230V Bill of Materials Reference Designator Part Value Manufacturer Part Number C1 CAP MPY 0.062µF 1000V RAD VISHAY BFC238330623 C2, C3, C8, C9, C30, C66 CAP CER 0.1µF 630V RAD TDK FK22X7R2J104K C4, C44 CAP ELEC 220µF 35V RAD NICHICON UHE1V221MPD C5, C23, C42, C46 CAP CER 0.10µF 25V 0603 MURATA GRM188R71E104KA01D C7 CAP MPY 68nF 275VAC X1 RAD PANASONIC ECQU2A683ML C11 CAP ELEC 1000µF 63V RAD NICHICON UPW1J102MHD6 C12 CAP CER 47µF 6.3V 1206 MURATA GRM31CR60J476ME19L C13, C34, C47 CAP CER 1µF 100V 1206 TDK C3216X7R2A105M C17, C18, C24, C36 CAP CER 1µF 16V 0603 MURATA GRM188R71C105KA12D C21, C43 CAP CER 10nF 25V 0603 MURATA GRM188R71E103KA01D C22 CAP CER 0.22µF 16V 0603 TDK C1608X7R1C224K C26 CAP CER 4.7nF 500VAC Y1 RAD EPCOS VY1472M63Y5UQ63V0 C35 CAP CER 10µF 16V 1206 MURATA GRM31CR71C106KAC7L C37 CAP CER 0.10µF 50V 0603 MURATA GRM188R71H104KA93D C38 CAP CER 2.2µF 6.3V 0603 TDK C1608X5R0J225M C39 CAP CER 470pF 100V 0603 TDK C1608C0G2A471J D1 DIODE TVS 220V 600W UNI SMB LITTLEFUSE SMBJ220A D2, D3, D6, D7 DIODE GEN PURPOSE 1000V 1A SMA COMCHIP CGRA4007-G D4, D9 DIODE ULTRAFAST 100V 0.2A SOT-23 FAIRCHILD MMBD914 D5 DIODE ULTRAFAST 600V 1A SMA FAIRCHILD ES1J D8 DIODE ULTRAFAST 200V 1A SMA FAIRCHILD ES1D D10, D23 DIODE ULTRAFAST 400V 1A SMA FAIRCHILD ES1G D11, D12, D18 DIODE ZENER 10V 500mW SOD-123 FAIRCHILD MMSZ5240B D13 DIODE ULTRAFAST 70V 0.2A SOT-23 FAIRCHILD BAV99 D14 DIODE ZENER 3.3V 500mW SOD-123 ON-SEMI MMSZ3V3T1G D15 DIODE SCHOTTKY 60V 2A SMB ON-SEMI SS26T3G D16 DIODE ZENER 24V 1.5W SMA MICRO-SEMI SMAJ5934B-TP D17 DIODE SCHOTTKY 50V 3A SMA FAIRCHILD ES2AA-13-F D20 DIODE SCHOTTKY (DUAL) 30V 0.5A SOT-23 DIODES INC PMEG3005CT,215 D21 DIODE ZENER 18V 500MW SOD-123 FAIRCHILD MMSZ5248B D22 DIODE ZENER 1.8V 500MW SOD-123 ON-SEMI MMSZ4678T1G D24 DIODE ZENER 3.9V 500MW SOD-123 ON-SEMI MMSZ4686T1G D25 DIODE TVS 20V 400W BIDIR SMA LITTLEFUSE SMAJ20CA F1 FUSE 500mA T-LAG RST BEL FUSE RST 500 J1, J2 CONN HEADER 2x1 VERT AMP 1-1318301-2 L1, L2, L4 IND SHIELD 1mH 1.14A SMT COILCRAFT MSS1278-105KL L3 IND SHIELD 270µH 2.18A SMT COILCRAFT MSS1278-274KL Q1 MOSFET N-CH 800V 3A DPAK ST MICRO STD4NK80ZT4 Q2, Q6, Q8 TRANS NPN 40V 0.6A SOT-23 FAIRCHILD MMBT4401 Q3 MOSFET N-CH 800V 6A DPAK INFINEON SPD06N80C3 Q4 TRANS NPN 40V 0.2A SOT-23 FAIRCHILD MMBT3904 Q7 MOSFET P-CH 70V 5.7A DPAK ZETEX ZXMP7A17K Q11 TRANS PNP 40V 0.2A SOT-23 FAIRCHILD MMBT3906 R1, R18, R58 RES 10kΩ 1% 0.1W 0603 VISHAY CRCW060310K0FKEA R2, R3, R47 RES 820Ω 5% 1W 2512 VISHAY CRCW2512820RJNEG R5, R7 RES 475kΩ 1% 0.25W 1206 VISHAY CRCW1206475KFKEA R6, R11 RES 10Ω 1% 0.25W 1206 VISHAY CRCW120610R0FKEA RES 2.4kΩ 5% 1W 2512 VISHAY CRCW25122K40JNEG R8, R9, R56 25 www.national.com AN-2150 R10 RES 40.2Ω 1% 0.25W 1206 VISHAY CRCW120640R2FKEA R12, R14, R15 RES 301Ω 1% 0.25W 1206 VISHAY CRCW1206301RFKEA R16 RES 6.04kΩ 1% 0.125W 0805 VISHAY CRCW08056K04FKEA R17 RES 100kΩ 1% 0.1W 0603 VISHAY CRCW0603100KFKEA R19, R41, R43, R61, R73 RES 0Ω 5% 0.1W 0603 VISHAY CRCW06030000Z0EA R20 RES 499kΩ 1% 0.1W 0603 VISHAY CRCW0603499KFKEA R21, R69 RES 20.0kΩ 1% 0.1W 0603 VISHAY CRCW060320K0FKEA R23 RES 6.04kΩ 1% 0.1W 0603 VISHAY CRCW06036K04FKEA R24, R25 RES 75.0kΩ 1% 0.1W 0603 VISHAY CRCW060375K0FKEA R26, R29 RES 1MΩ 1% 0.25W 1206 VISHAY CRCW12061M00FKEA R28 RES 10Ω 1% 0.125W 0805 VISHAY CRCW080510R0FKEA R30, R31, R65, R66, R83 RES 1.00Ω 1% 0.25W 1206 VISHAY CRCW12061R00FKEA R32, R45, R77 RES 15.0kΩ 1% 0.1W 0603 VISHAY CRCW060315K0FKEA R34, R36 RES 5.62Ω 1% 0.25W 1206 VISHAY CRCW12065R62FKEA R38 RES 5.11kΩ 1% 0.1W 0603 VISHAY CRCW06035K11FKEA R39, R57 RES 10Ω 1% 3W WIREWOUND VISHAY PAC300001009FAC000 R44 THERM 10kΩ NTC 0603 MURATA NTCG163JF103F R46 RES 5.11kΩ 1% 0.125W 0805 VISHAY CRCW08055K11FKEA R48, R51, R62 RES 20.0kΩ 1% 0.25W 1206 VISHAY CRCW120620K0FKEA R55 RES 51.1kΩ 1% 0.25W 1206 VISHAY CRCW120651K1FKEA R70 RES 2.00kΩ 1% 0.125W 0805 VISHAY CRCW08052K00FKEA R71 RES 10.0kΩ 1% 0.125W 0805 VISHAY CRCW080510K0FKEA R72 RES 105kΩ 1% 0.125W 0805 VISHAY CRCW0805105KFKEA R81 RES 2.67kΩ 1% 0.1W 0603 VISHAY CRCW06032K67FKEA R84 RES 49.9kΩ 1% 0.1W 0603 VISHAY CRCW060349K9FKEA T1 XFORMER 230V 30W OUTPUT 50V WURTH 750817651 U1 IC PFC CONT 16-TSSOP NSC LM3450AMT U8, U9 OPTO-ISOLATOR SMD LITE ON CNY17F-3S U10 IC SHUNT REG SOT-23 NSC LMV431AIM5 U11 IC LED DRIVR 10-eMSOP NSC LM3409HVMY C10, C14, C20, C25, C28, Did not populate C29, C31, C40, Q20, R4, R13, R22, R27, R33, R40, R42, R49, R54, R59, R60, R63, R64, R75, R78, VR1 www.national.com 26 AN-2150 PCB Layout 30163197 Top Copper and Silkscreen 30163198 Bottom Copper and Silkscreen 27 www.national.com LM3450A Evaluation Board For more National Semiconductor product information and proven design tools, visit the following Web sites at: www.national.com Products Design Support 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