ETC FAN7530

FAN7530
Critical Conduction Mode PFC Controller
Features
Description
„ Low Total Harmonic Distortion (THD)
The FAN7530 is an active power factor correction (PFC)
controller for boost PFC applications that operates in critical conduction mode (CRM). It uses the voltage mode
PWM that compares an internal ramp signal with the
error amplifier output to generate MOSFET turn-off signal. Since the voltage mode CRM PFC controller does
not need rectified AC line voltage information, it saves
the power loss of the input voltage sensing network necessary for the current mode CRM PFC controller.
„ Precise Adjustable Output Over-Voltage Protection
„ Open-Feedback Protection and Disable Function
„ Zero Current Detector
„ 150µs Internal Start-up Timer
„ MOSFET Over-Current Protection
„ Under-Voltage Lockout with 3.5V Hysteresis
„ Low Start-up (40µA) and Operating Current (1.5mA)
„ Totem Pole Output with High State Clamp
FAN7530 provides many protection functions, such as
over voltage protection, open-feedback protection, overcurrent protection, and under-voltage lockout protection.
The FAN7530 can be disabled if the INV pin voltage is
lower than 0.45V and the operating current decreases to
65µA. Using a new variable on-time control method,
THD is lower than the conventional CRM boost PFC ICs.
„ +500/-800mA Peak Gate Drive Current
„ 8-Pin DIP or 8-Pin SOP
Applications
„ Adapter
„ Ballast
„ LCD TV, CRT TV
„ SMPS
Related Application Notes
„ AN-6027 - Design of Power Factor Correction Circuit
Using FAN7530
Ordering Information
Part Number
Operating Temp.
Range
Pb-Free
Package
Packing Method
Marking
Code
FAN7530N
-40°C to +125°C
Yes
8-DIP
Rail
FAN7530
FAN7530M
-40°C to +125°C
Yes
8-SOP
Rail
FAN7530
FAN7530MX
-40°C to +125°C
Yes
8-SOP
Tape & Reel
FAN7530
© 2006 Fairchild Semiconductor Corporation
FAN7530 Rev. 1.0.0
www.fairchildsemi.com
FAN7530 Critical Conduction Mode PFC Controller
October 2006
FAN7530 Critical Conduction Mode PFC Controller
Typical Application Diagrams
L
D
VO
AC
IN
VAUX
I2
NAUX
RZCD
R2 ZCD
CO
VCC
FAN7530
INV
MOT
I1
CS
COMP
R1
GND
FAN7530 Rev. 00
Figure 1. Typical Boost PFC Application
Internal Block Diagram
2.5V
Ref
VCC 8
UVLO
12V
8.5V
VCC
Internal
Bias
Disable
Drive
Output
150ms
Timer
ZCD 5
Q
1.4V 1.5V
R
Zero Current
Detector
OVP
4
Disable
40k
8pF
0.8V
MOT 2
7 OUT
13V
S
6.5V
CS
Vref
Ramp
Signal
Sawtooth
Generator
2.675V
2.5V
0.45V 0.35V
Current Protection
Comparator
1V Offset
Error
Amplifier
1V~5V
Range
6
GND
Gm
Vref
1 INV
3
COMP
FAN7530 Rev. 00
Figure 2. Functional Block Diagram of FAN7530
© 2006 Fairchild Semiconductor Corporation
FAN7530 Rev. 1.0.0
www.fairchildsemi.com
2
VCC
OUT
GND
ZCD
8
7
6
5
YWW
FAN7530
1
2
3
4
INV
MOT
COMP
CS
FAN7530 Rev. 00
Figure 3. Pin Configuration (Top View)
Pin Definitions
Pin #
Name
Description
1
INV
This pin is the inverting input of the error amplifier. The output voltage of the boost PFC
converter should resistively divided to 2.5V.
2
MOT
This pin is used to set the slope of the internal ramp. The voltage of this pin is maintained at 2.9V. If a resistor is connected between this pin and GND, current flows out of
the pin and the slope of the internal ramp is proportional to this current.
3
COMP
This pin is the output of the transconductance error amplifier. Components for the output voltage compensation should be connected between this pin and GND.
4
CS
This pin is the input of the over-current protection comparator. The MOSFET current is
sensed using a sensing resistor and the resulting voltage is applied to this pin. An
internal RC filter is included to filter switching noise.
5
ZCD
This pin is the input of the zero current detection block. If the voltage of this pin goes
higher than 1.5V, then goes lower than 1.4V, the MOSFET is turned on.
6
GND
This pin is used for the ground potential of all the pins. For proper operation, the signal
ground and the power ground should be separated.
7
OUT
This pin is the gate drive output. The peak sourcing and sinking current levels are
+500mA and -800mA respectively. For proper operation, the stray inductance in the
gate driving path must be minimized.
8
Vcc
This pin is the IC supply pin. IC current and MOSFET drive current are supplied using
this pin.
© 2006 Fairchild Semiconductor Corporation
FAN7530 Rev. 1.0.0
www.fairchildsemi.com
3
FAN7530 Critical Conduction Mode PFC Controller
Pin Assignments
The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The
device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables
are not guaranteed at the absolute maximum ratings. TA=25°C, unless otherwise specified.
Symbol
VCC
IOH, IOL
Iclamp
Parameter
Supply Voltage
Peak Drive Output Current
Driver Output Clamping Diodes VO>VCC or VO<-0.3V
Value
Unit
VZ
V
+500/-800
mA
±10
mA
±10
mA
-0.3 to 6
V
150
°C
Operating Temperature Range
-40 to 125
°C
Storage Temperature Range
Idet
Detector Clamping Diodes
VIN
Error Amplifier, MOT, CS Input Voltages
TJ
Operating Junction Temperature
TA
-65 to 150
°C
VESD_HBM
ESD Capability, Human Body Model
2.0
kV
VESD_MM
ESD Capability, Machine Model
300
V
VESD_CDM
ESD Capability, Charged Device Model
500
V
TSTG
Thermal Impedance(1)
Symbol
θJA
Parameter
Thermal Resistance, Junction-to-Ambient
Value
Unit
8-DIP
110
°C/W
8-SOP
150
°C/W
Note:
1. Regarding the test environment and PCB type, please refer to JESD51-2 and JESD51-10.
© 2006 Fairchild Semiconductor Corporation
FAN7530 Rev. 1.0.0
www.fairchildsemi.com
4
FAN7530 Critical Conduction Mode PFC Controller
Absolute Maximum Ratings
VCC = 14V and TA = -40°C~125°C unless otherwise specified.
Symbol
Parameter
Condition
Min.
Typ.
Max.
Unit
11
12
13
V
UNDER-VOLTAGE LOCKOUT SECTION
Vth(start)
Start Threshold Voltage
VCC increasing
Vth(stop)
Stop Threshold Voltage
VCC decreasing
HY(uvlo)
UVLO Hysteresis
VZ
Zener Voltage
7.5
8.5
9.5
V
3.0
3.5
4.0
V
ICC = 20mA
22
V
SUPPLY CURRENT SECTION
Ist
Start-up Supply Current
VCC = Vth(start) - 0.2V
40
70
µA
ICC
Operating Supply Current
Output no switching
1.5
3.0
mA
Idcc
Dynamic Operating Supply Current
50kHz, CL=1nF
2.5
4.0
mA
Operating Current at Disable
Vinv = 0V
20
65
95
µA
Voltage Feedback Input Threshold1
TA = 25°C
2.465
2.500
2.535
V
Line Regulation
VCC = 14V ~ 20V
0.1
10.0
mV
ICC(dis)
ERROR AMPLIFIER SECTION
Vref1
ΔVref1
Vref1(2)
ΔVref2
Temperature Stability of
Ib(ea)
Input Bias Current
Vinv = 1V ~ 4V
Isource
Output Source Current
Vinv = Vref1 - 0.1V
-12
µA
Output Sink Current
Vinv = Vref1 + 0.1V
12
µA
Veao(H)
Output Upper Clamp Voltage
Vinv = Vref1 - 0.1V
Veao(Z)
Zero Duty Cycle Output Voltage
0.9
1.0
1.1
V
Transconductance(2)
90
115
140
µmho
2.784
2.900
3.016
V
19
24
29
µsec
0.7
0.8
0.9
V
-1.0
-0.1
1.0
µA
350
500
nsec
Isink
gm
20
-0.5
5.4
mV
0.5
6.0
6.6
µA
V
MAXIMUM ON-TIME SECTION
Vmot
ton(max)
Maximum On-Time Voltage
Rmot = 40.5kΩ
Maximum On-Time Programming
Rmot = 40.5kΩ, TA = 25°C
CURRENT SENSE SECTION
VCS(limit)
Ib(cs)
td(cs)
Current Sense Input Threshold
Voltage Limit
Input Bias Current
Current Sense Delay to
VCS = 0V ~ 1V
Output(2)
dV/dt = 1V/100ns,
from 0V to 5V
Note:
2. These parameters, although guaranteed by design, are not tested in production.
© 2006 Fairchild Semiconductor Corporation
FAN7530 Rev. 1.0.0
www.fairchildsemi.com
5
FAN7530 Critical Conduction Mode PFC Controller
Electrical Characteristics
VCC = 14V and TA = -40°C~125°C unless otherwise specified.
Symbol
Parameter
Condition
Min.
Typ.
Max.
Unit
1.35
1.50
1.65
V
ZERO CURRENT DETECT SECTION
Vth(ZCD)
Input Voltage Threshold(3)
(3)
HY(ZCD)
Detect Hysteresis
0.05
0.10
0.15
V
Vclamp(H)
Input High Clamp Voltage
Idet = 3mA
6.0
6.7
7.4
V
Vclamp(L)
Input Low Clamp Voltage
Idet = -3mA
0
0.65
1.00
V
-1.0
-0.1
1.0
µA
Ib(ZCD)
Input Bias Current
VZCD = 1V ~ 5V
(3)
Isource(zcd)
Source Current Capability
TA = 25°C
-10
mA
Isink(zcd)
Sink Current Capability(3)
TA = 25°C
10
mA
200
nsec
11.0
12.8
V
tdead
Maximum Delay from ZCD to Output dV/dt = -1V/100ns,
Turn-on(3)
from 5V to 0V
100
OUTPUT SECTION
VOH
Output Voltage High
IO = -100mA, TA = 25°C
VOL
Output Voltage Low
IO = 200mA, TA = 25°C
1.0
2.5
V
tr
Rising
Time(3)
Cl = 1nF
50
100
nsec
Falling
Time(3)
Cl = 1nF
50
100
nsec
13.0
14.5
V
1
V
tf
VO(max)
VO(UVLO)
Maximum Output Voltage
VCC = 20V, IO = 100μA
Output Voltage with UVLO Activated
VCC = 5V, IO = 100μA
9.2
11.5
RESTART TIMER SECTION
td(rst)
Restart Timer Delay
50
150
300
µsec
OVER-VOLTAGE PROTECTION SECTION
Vovp
HY(ovp)
OVP Threshold Voltage
TA = 25°C
2.620
2.675
2.730
V
OVP Hysteresis
TA = 25°C
0.120
0.175
0.230
V
ENABLE SECTION
Vth(en)
Enable Threshold Voltage
0.40
0.45
0.50
V
HY(en)
Enable Hysteresis
0.05
0.10
0.15
V
Note:
3. These parameters, although guaranteed by design, are not tested in production.
© 2006 Fairchild Semiconductor Corporation
FAN7530 Rev. 1.0.0
www.fairchildsemi.com
6
FAN7530 Critical Conduction Mode PFC Controller
Electrical Characteristics (Continued)
9.5
12.5
9.0
Vth(stop) [V]
Vth(start) [V]
13.0
12.0
8.5
8.0
11.5
7.5
11.0
-60 -40 -20
0
20
40
60
80
-60 -40 -20
100 120 140
0
40
60
80
100 120 140
Figure 5. Stop Threshold Voltage vs. Temp.
4.00
23.0
3.75
22.5
VZ [V]
HY(UVLO) [V]
Figure 4. Start Threshold Voltage vs. Temp.
3.50
22.0
21.5
3.25
21.0
3.00
-60 -40 -20
0
20
40
60
80
-60 -40 -20
100 120 140
0
20
40
60
80
100 120 140
Temperature [°C]
Temperature [°C]
Figure 6. UVLO Hysteresis vs. Temp.
Figure 7. Zener Voltage vs. Temp.
60
2.4
ICC [mA]
45
Ist [μA]
20
Temperature [°C]
Temperature [°C]
30
1.6
0.8
15
0.0
-60 -40 -20
0
20
40
60
80
-60 -40 -20
100 120 140
Figure 8. Start-up Supply Current vs. Temp.
20
40
60
80
100 120 140
Figure 9. Operating Supply Current vs. Temp.
© 2006 Fairchild Semiconductor Corporation
FAN7530 Rev. 1.0.0
0
Temperature [°C]
Temperature [°C]
www.fairchildsemi.com
7
FAN7530 Critical Conduction Mode PFC Controller
Typical Characteristics
90
3
72
ICC(dis) [μA]
Idcc [mA]
4
2
1
54
36
0
-60 -40 -20
0
20
40
60
80
100 120 140
-60 -40 -20
0
Temperature [°C]
20
40
60
80
100 120 140
Temperature [°C]
Figure 10. Dynamic Operating Supply Current vs.
Temp.
Figure 11. Operating Current at Disable vs. Temp.
10.0
7.5
ΔVref1 [mV]
Vref1 [V]
2.52
2.50
5.0
2.5
2.48
0.0
-60 -40 -20
0
20
40
60
80
-60 -40 -20
100 120 140
0
20
40
60
80
100 120 140
Temperature [°C]
Temperature [°C]
Figure 13. ΔVref1 vs. Temp.
Figure 12. Vref1 vs. Temp.
0.50
-9
Isource [μA]
Ib(ea) [μA]
0.25
0.00
-12
-15
-0.25
-0.50
-18
-60 -40 -20
0
20
40
60
80
100 120 140
-60 -40 -20
Temperature [°C]
20
40
60
80
100 120 140
Temperature [°C]
Figure 14. Input Bias Current vs. Temp.
Figure 15. Output Source Current vs. Temp.
© 2006 Fairchild Semiconductor Corporation
FAN7530 Rev. 1.0.0
0
www.fairchildsemi.com
8
FAN7530 Critical Conduction Mode PFC Controller
Typical Characteristics (Continued)
6.6
15
6.3
Veao(H) [V]
Isink [μA]
18
12
9
6.0
5.7
6
5.4
-60 -40 -20
0
20
40
60
80
100 120 140
-60 -40 -20
0
Temperature [°C]
20
40
60
80
100 120 140
Temperature [°C]
Figure 16. Output Sink Current vs. Temp.
Figure 17. Output Upper Clamp Voltage vs. Temp.
1.10
3.00
2.95
Vmot [V]
Veao(Z) [V]
1.05
1.00
2.90
2.85
0.95
2.80
0.90
-60 -40 -20
0
20
40
60
80
100 120 140
-60 -40 -20
0
Temperature [°C]
20
40
60
80
100 120 140
Temperature [°C]
Figure 18. Zero Duty Cycle Output Voltage vs. Temp.
Figure 19. Maximum On-Time Voltage vs. Temp.
0.90
0.85
Vcs(limit) [V]
Ton(max) [μs]
27
24
0.80
0.75
21
0.70
-60 -40 -20
0
20
40
60
80
100 120 140
-60 -40 -20
Temperature [°C]
20
40
60
80
100 120 140
Temperature [°C]
Figure 20. Maximum On-Time vs. Temp.
Figure 21. Current Sense Input Threshold Voltage vs.
Temp.
© 2006 Fairchild Semiconductor Corporation
FAN7530 Rev. 1.0.0
0
www.fairchildsemi.com
9
FAN7530 Critical Conduction Mode PFC Controller
Typical Characteristics (Continued)
1.0
7.2
6.8
Vclamp(H) [V]
Ib(cs) [μA]
0.5
0.0
6.4
-0.5
6.0
-1.0
-60 -40 -20
0
20
40
60
80
100 120 140
-60 -40 -20
0
Temperature [°C]
Figure 22. Input Bias Current vs. Temp.
40
60
80
100 120 140
Figure 23. Input High Clamp Voltage vs. Temp.
1.00
1.0
0.75
0.5
Ib(zcd) [μA]
Vclamp(L) [V]
20
Temperature [°C]
0.50
0.25
0.0
-0.5
0.00
-1.0
-60 -40 -20
0
20
40
60
80
100 120 140
-60 -40 -20
0
Temperature [°C]
20
40
60
80
100 120 140
Temperature [°C]
Figure 24. Input Low Clamp Voltage vs. Temp.
Figure 25. Input Bias Current vs. Temp.
0.9
14
VO(uvlo) [V]
VO(max) [V]
0.6
13
12
0.3
0.0
-0.3
-60 -40 -20
0
20
40
60
80
100 120 140
-60 -40 -20
Temperature [°C]
20
40
60
80
100 120 140
Temperature [°C]
Figure 26. Maximum Output Voltage vs. Temp.
Figure 27. Output Voltage with UVLO Activated vs.
Temp.
© 2006 Fairchild Semiconductor Corporation
FAN7530 Rev. 1.0.0
0
www.fairchildsemi.com
10
FAN7530 Critical Conduction Mode PFC Controller
Typical Characteristics (Continued)
2.73
300
2.70
200
Vovp [V]
td(rst) [μs]
250
150
100
2.67
2.64
50
-60 -40 -20
0
20
40
60
80
-60 -40 -20
100 120 140
0
20
40
60
80
100 120 140
Temperature [°C]
Temperature [°C]
Figure 28. Restart Delay Time vs. Temp.
Figure 29. OVP Threshold Voltage vs. Temp.
0.500
0.475
0.18
Vth(en) [V]
HY(OVP) [V]
0.21
0.450
0.15
0.425
0.400
0.12
-60 -40 -20
0
20
40
60
80
-60 -40 -20
100 120 140
0
20
40
60
80
100 120 140
Temperature [°C]
Temperature [°C]
Figure 30. OVP Hysteresis vs. Temp.
Figure 31. Enable Threshold Voltage vs. Temp.
0.150
HY(en) [V]
0.125
0.100
0.075
0.050
-60 -40 -20
0
20
40
60
80
100 120 140
Temperature [°C]
Figure 32. Enable Hysteresis vs. Temp.
© 2006 Fairchild Semiconductor Corporation
FAN7530 Rev. 1.0.0
www.fairchildsemi.com
11
FAN7530 Critical Conduction Mode PFC Controller
Typical Characteristics (Continued)
1. Error Amplifier Block
rent detector turns on the MOSFET. The ZCD pin is protected internally by two clamps, 6.7V-high clamp and
0.65V-low clamp. The 150µs timer generates a MOSFET
turn-on signal if the drive output has been low for more
than 150µs from the falling edge of the drive output.
The error amplifier block consists of a transconductance
amplifier, output OVP comparator, and disable comparator. For the output voltage control, a transconductance
amplifier is used instead of the conventional voltage
amplifier. The transconductance amplifier (voltage controlled current source) aids the implementation of OVP
and disable function. The output current of the amplifier
changes according to the voltage difference of the inverting and non-inverting input of the amplifier. The output
voltage of the amplifier is compared with the internal
ramp signal to generate the switch turn-off signal. The
OVP comparator shuts down the output drive block when
the voltage of the INV pin is higher than 2.675V and
there is 0.175V hysteresis. The disable comparator disables the operation of the FAN7530 when the voltage of
the inverting input is lower than 0.45V and there is
100mV hysteresis. An external small signal MOSFET
can be used to disable the IC, as shown in Figure 33.
The IC operating current decreases below 65µA to
reduce power consumption if the IC is disabled.
2.675V
OVP
Disable
0.45V
RZCD
S
6.7V
Q
1.4V
Zero Current
Detector
R
FAN7530 Rev. 00
Figure 34. Zero Current Detector Block
3. Sawtooth Generator Block
The output of the error amplifier and the output of the
sawtooth generator are compared to determine the
MOSFET turn-off instance. The slope of the sawtooth is
determined by an external resistor connected to the
MOT pin. The voltage of the MOT pin is 2.9V and the
slope is proportional to the current flowing out of the
MOT pin. The internal ramp signal has a 1V offset; therefore, the drive output is shut down if the voltage of the
COMP pin is lower than 1V. The MOSFET on-time is
maximum when the COMP pin voltage is 5V. According
to the slope of the internal ramp, the maximum on-time
can be programmed. The necessary maximum on-time
depends on the boost inductor, lowest AC line voltage,
and maximum output power. The resistor value should
be designed properly.
Vout
Error Amp
3
5
1.5V
0.35V
Gm
Turn-on
Signal
ZCD
2.5V
Vref1 (2.5V)
150μs
Timer
Vin
INV
1
Disable
Signal
COMP
Off Signal
FAN7530 Rev. 00
1V Offset
MOT
Sawtooth
Generator
3
Figure 33. Error Amplifier Block
2.9V
2. Zero Current Detection Block
Error Amp
Output
The zero current detector (ZCD) generates the turn-on
signal of the MOSFET when the boost inductor current
reaches zero using an auxiliary winding coupled with the
inductor. If the voltage of the ZCD pin goes higher than
1.5V, the ZCD comparator waits until the voltage goes
below 1.4V. If the voltage goes below 1.4V, the zero cur-
FAN7530 Rev. 00
Figure 35. Sawtooth Generator Block
© 2006 Fairchild Semiconductor Corporation
FAN7530 Rev. 1.0.0
www.fairchildsemi.com
12
FAN7530 Critical Conduction Mode PFC Controller
Applications Information
5. Switch Drive Block
The MOSFET current is sensed using an external sensing resistor for the over-current protection. If the CS pin
voltage is higher than 0.8V, the over-current protection
comparator generates a protection signal. An internal RC
filter is included to filter switching noise.
The FAN7530 contains a single totem-pole output stage
designed for direct drive of the power MOSFET. The
drive output is capable of up to +500/-800mA peak current with a typical rise and fall time of 50ns with 1nF load.
The output voltage is clamped to 13V to protect the
MOSFET gate if the VCC voltage is higher than 13V.
OCP
Signal
40k
CS
4
6. Under-Voltage Lockout Block
If the VCC voltage reaches 12V, the IC’s internal blocks
are enabled and start operation. If the VCC voltage drops
below 8.5V, most of the internal blocks are disabled to
reduce the operating current. VCC voltage should be
higher than 8.5V under normal conditions.
8pF
0.8V
Over-Current Protection
Comparator
FAN7530 Rev. 00
Figure 36. Over-Current Protection Block
© 2006 Fairchild Semiconductor Corporation
FAN7530 Rev. 1.0.0
www.fairchildsemi.com
13
FAN7530 Critical Conduction Mode PFC Controller
4. Over-Current Protection Block
Application
Output Power
Input Voltage
Output Voltage
Ballast
100W
Universal input
(85~265VAC)
400V
Features
„ High efficiency (>90% at 85VAC input)
„ Low total harmonic distortion (THD) (<10% at 265VAC input, 25W load)
Key Design Notes
„ R1, R2, R5, C11 should be optimized for best THD characteristic.
1. Schematic
T1
PFC OUTPUT
VAUX
BD
D2
C5
R4
R3
R5
NTC
Q1
ZD1
D1
C3
C4
8
7
VCC
R6
C11
6
C9
5
OUT GND
ZCD
C2
LF1
R10
D3
C10
R9
FAN7530
R2
C1
V1
INV
MOT COMP CS
1
2
R1
F1
3
R8
C7
C6
R11
4
R7
C8
FAN7530 Rev. 00
AC INPUT
Figure 37. Schematic
© 2006 Fairchild Semiconductor Corporation
FAN7530 Rev. 1.0.0
www.fairchildsemi.com
14
FAN7530 Critical Conduction Mode PFC Controller
Typical Application Circuit
FAN7530 Critical Conduction Mode PFC Controller
2. Inductor Schematic Diagram
1
NVcc
2
3
Np
5
FAN7530 Rev. 00
Figure 38. Inductor Schematic Diagram
3. Winding Specification
No
Pin (s→f)
2→1
NVcc
Wire
0.2φ
×1
Turns
Winding Method
8
Solenoid Winding
58
Solenoid Winding
Insulation: Polyester Tape t = 0.050mm, 4 Layers
5→3
Np
0.2φ × 10
Outer Insulation: Polyester Tape t = 0.050mm, 4 Layers
Air Gap: 0.6mm for each leg
4. Electrical Characteristics
Inductance
Pin
Specification
Remarks
3-5
600µH ± 10%
100kHz, 1V
5. Core & Bobbin
„ Core: EI 3026
„ Bobbin: EI3026
„ Ae(mm2): 111
© 2006 Fairchild Semiconductor Corporation
FAN7530 Rev. 1.0.0
www.fairchildsemi.com
15
Part
Value
Note
Part
Value
Fuse
F1
3A/250V
NTC
10D-9
Note
Inductor
T1
600µH
EI3026
NTC
MOSFET
Resistor
Q1
FQPF13N50C
Fairchild
R1
56kΩ
1/4W
R2
820kΩ
1/4W
R3
330kΩ
1/2W
D1
1N4148
Fairchild
R4
150Ω
1/2W
D2
BYV26C
600V, 1A
R5
20kΩ
1/4W
D3
SB140
Fairchild
R6
10Ω
1/4W
ZD1
1N4746
18V
R7
0.2Ω
1/2W
R8
10kΩ
1/4W
R9
10kΩ
1/4W
R10
2MΩ
1/4W
R11
12.9kΩ
1/4W
Diode
Bridge Diode
BD
KBL06
600V/4A
Line Filter
Capacitor
LF1
C1
150nF/275VAC
Box Capacitor
C2
470nF/275VAC
Box Capacitor
C3
2.2nF/3kV
Ceramic Capacitor
C4
2.2nF/3kV
Ceramic Capacitor
C6
47µF/25V
Electrolytic Capacitor
C7
47nF/50V
Ceramic Capacitor
220nF/50V
Multilayer Ceramic
Capacitor
C9
100µF/450V
Electrolytic Capacitor
C10
12nF/100V
Film Capacitor
C11
56pF/50V
Ceramic Capacitor
40mH
IC
IC1
FAN7530
V1
471
C5
C8
Fairchild
TNR
© 2006 Fairchild Semiconductor Corporation
FAN7530 Rev. 1.0.0
Wire 0.4mm
470V
www.fairchildsemi.com
16
FAN7530 Critical Conduction Mode PFC Controller
6. Demo Circuit Part List
FAN7530 Critical Conduction Mode PFC Controller
7. Layout
Power Ground
Signal Ground
Separate the power ground
and the signal ground
Place the output voltage
sensing resistors close to IC
Figure 39. PCB Layout Considerations for FAN7530
8. Performance Data
POUT
100W
75W
50W
25W
85VAC
115VAC
230VAC
265VAC
PF
0.998
0.998
0.991
0.984
THD
5.1%
3.6%
5.2%
6.2%
Efficiency
90.9%
93.7%
95.6%
96%
PF
0.999
0.998
0.986
0.975
THD
4.1%
3.6%
5.0%
5.7%
Efficiency
91.6%
93.3%
94.6%
95.3%
PF
0.998
0.997
0.974
0.956
THD
4.4%
5.0%
5.7%
6.2%
Efficiency
91.3%
91.9%
92.7%
93.4%
PF
0.995
0.991
0.923
0.876
THD
7.9%
8.6%
8.3%
8.7%
Efficiency
86.4%
87.1%
87.3%
88.1%
© 2006 Fairchild Semiconductor Corporation
FAN7530 Rev. 1.0.0
www.fairchildsemi.com
17
8-DIP
0.060 ±0.004
#5
1.524 ±0.10
#4
0.018 ±0.004
#8
2.54
0.100
9.60
MAX
0.378
#1
9.20 ±0.20
0.362 ±0.008
(
6.40 ±0.20
0.252 ±0.008
0.46 ±0.10
0.79
)
0.031
Dimensions are in millimeters (inches) unless otherwise noted..
5.08
MAX
0.200
7.62
0.300
3.40 ±0.20
0.134 ±0.008
3.30 ±0.30
0.130 ±0.012
0.33
0.013 MIN
+0.10
0.25 –0.05
+0.004
0~15°
0.010 –0.002
September 1999, Rev B
8dip_dim.pdf
© 2006 Fairchild Semiconductor Corporation
FAN7530 Rev. 1.0.0
www.fairchildsemi.com
18
FAN7530 Critical Conduction Mode PFC Controller
Mechanical Dimensions
8-SOP
Dimensions are in millimeters (inches) unless otherwise noted.
MIN
#5
6.00 ±0.30
0.236 ±0.012
0.41 ±0.10
0.016 ±0.004
#4
1.27
0.050
#8
5.13
MAX
0.202
#1
4.92 ±0.20
0.194 ±0.008
(
0.56
)
0.022
1.55 ±0.20
0.061 ±0.008
0.1~0.25
0.004~0.001
3.95 ±0.20
0.156 ±0.008
°
+0.10
0.15 -0.05
+0.004
0.006 -0.002
MAX0.10
MAX0.004
1.80
MAX
0.071
0~
8
5.72
0.225
0.50 ±0.20
0.020 ±0.008
September 2001, Rev B1
sop8_dim.pdf
© 2006 Fairchild Semiconductor Corporation
FAN7530 Rev. 1.0.0
www.fairchildsemi.com
19
FAN7530 Critical Conduction Mode PFC Controller
Mechanical Dimensions (Continued)
ACEx¥
ActiveArray¥
Bottomless¥
Build it Now¥
CoolFET¥
CROSSVOLT¥
DOME¥
EcoSPARK¥
2
E CMOS¥
EnSigna¥
FACT¥
FACT Quiet Series¥
®
FAST
FASTr¥
FPS¥
FRFET¥
GlobalOptoisolator¥
GTO¥
HiSeC¥
2
I C¥
i-Lo¥
ImpliedDisconnect¥
IntelliMAX¥
ISOPLANAR¥
LittleFET¥
MICROCOUPLER¥
MicroFET¥
MicroPak¥
MICROWIRE¥
MSX¥
MSXPro¥
OCX¥
OCXPro¥
®
OPTOLOGIC
OPTOPLANAR¥
PACMAN¥
POP¥
Power247¥
PowerEdge¥
PowerSaver¥
®
PowerTrench
®
QFET
QS¥
QT Optoelectronics¥
Quiet Series¥
RapidConfigure¥
RapidConnect¥
ScalarPump¥
PSerDes¥
®
SILENT SWITCHER
SMART START¥
SPM¥
Stealth¥
SuperFET¥
SuperSOT¥-3
SuperSOT¥-6
SuperSOT¥-8
SyncFET¥
TCM¥
TinyBoost¥
TinyBuck¥
®
TinyLogic
TINYOPTO¥
TinyPower¥
TinyPWM¥
TruTranslation¥
UHC¥
®
UltraFET
UniFET¥
VCX¥
Wire¥
Across the board. Around the world.¥
Programmable Active Droop¥
®
The Power Franchise
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS
HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE
APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER
ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S
WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR
SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1.
Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body or
(b) support or sustain life, and (c) whose failure to perform
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to
result in a significant injury of the user.
2.
A critical component in any component of a life support,
device, or system whose failure to perform can be
reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Advance Information
Formative or In
Design
This datasheet contains the design specifications for product
development. Specifications may change in any manner without
notice.
Definition
Preliminary
First Production
This datasheet contains preliminary data; supplementary data will
be published at a later date. Fairchild Semiconductor reserves the
right to make changes at any time without notice to improve design.
No Identification Needed
Full Production
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at any time
without notice to improve design.
Obsolete
Not In Production
This datasheet contains specifications on a product that has been
discontinued by Fairchild Semiconductor. The datasheet is printed
for reference information only.
Rev. I20
© 2006 Fairchild Semiconductor Corporation
FAN7530 Rev. 1.0.0
www.fairchildsemi.com
20
FAN7530 Critical Conduction Mode PFC Controller
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an
exhaustive list of all such trademarks.
www.fairchildsemi.com
Application Note AN-6027
Design of Power Factor Correction Circuit Using FAN7530
1. Introduction
The FAN7530 is an active power factor correction (PFC)
controller for the boost PFC application that operates in the
critical conduction mode (CRM). The critical conduction
mode boost power factor converter operates at the boundary
of continuous conduction mode and discontinuous conduction mode. The CRM PFC controllers are of two kinds: the
current-mode CRM PFC controller and the voltage-mode
CRM PFC controller. For the current mode, a boost switch is
turned on when the inductor current reaches zero and turned
off when the inductor current meets the desired current reference. In this case, the rectified AC line voltage should be
sensed to generate the current reference, as in the
FAN7527B; however, the sensing network can cause addi-
tional power loss. In the voltage mode, the switch turn-on is
the same as that of the current mode, but the switch turn-off
is determined by an internal ramp signal. The ramp signal is
compared with an error amplifier output and the switch turnon time is controlled to be constant, as shown in Figure 1. If
the turn-on time is constant, the peak inductor current is proportional to the rectified AC line voltage, as shown in Figure
2. In this way, the input current waveform follows the waveform of the input voltage, thereby obtaining a good power
factor. The FAN7530 is a voltage-mode CRM PFC controller. Because the voltage-mode CRM PFC controller does not
need the rectified AC line voltage information, it can save
the power loss of the sensing network.
L
D
VOUT
VOUT
AC
AC
IN
Turn-On
Turn-On
S
R
Turn-Off
Turn-Off
Q
OCP
RSENSE
SENSE
Feedback
Feedback
OVP
Disable
Ramp
Error Amp
Figure 1. Voltage Mode CRM Boost PFC Circuit
Inductor
Current
MOSFET
Conduction
Diode
Conduction
Peak Inductor
Current
Average
Input
Current
Gating
Signal
Constant On-time & Variable Off-time
Figure 2. CRM Boost PFC Inductor Current Waveform
© 2006 Fairchild Semiconductor Corporation
Rev. 1.0.3 • 1/11/07
www.fairchildsemi.com
AN6027
APPLICATION NOTE
Figure 3 shows the block diagram of the FAN7530. The only
difference between the FAN7529 and the FAN7530 is the pin
configuration of pin 2 and pin 3. For the FAN7529, the INV
pin and the COMP pin are adjacent, but because the voltage
of pin 1 is 2.5V and the operating range of pin 2 is from 1V
to 5V, the PFC output voltage can increase at light load if
pins 1 and 2 are shorted. For the FAN7530, however, the INV
pin and the MOT pin are adjacent. Because the voltage of the
MOT pin is 2.9V, the over-voltage protection works if pin 1
and pin 2 are shorted.
Block Diagram
2.5V
Ref
VCC 8
UVLO
Vref
VCC
Internal
Bias
12V
8.5V
Drive
Output
Disable
150μs
Timer
ZCD 5
S
6.5V
Q
1.4V 1.5V
R
Zero Current
Detector
CS
OVP
4
Disable
40k
8pF
0.8V
Ramp
Signal
MOT 2
7 OUT
13V
2.675V
2.5V
0.45V 0.35V
Current Protection
Comparator
Vref
1V Offset
Error
Amplifier
Sawtooth
Generator
Gm
1V~5V
Range
6
3
GND
COMP
1
INV
Figure 3. Block Diagram of the FAN7530 Showing Error Amplifier Block, Zero Current Detector Block, Sawtooth
Generator Block, Over-Current Protection Block, and Switch Drive Block
© 2006 Fairchild Semiconductor Corporation
Rev. 1.0.3 • 1/11/07
www.fairchildsemi.com
2
AN6027
APPLICATION NOTE
2. Device Block Description
the junction capacitor of the MOSFET resonates with the
boost inductor and the auxiliary winding voltage decreases
resonantly. If it reaches 1.4V, the zero current detector turns
on the MOSFET. The ZCD pin is protected internally by two
clamps: the 6.5V HIGH clamp and the 0.65V LOW clamp,
as shown in Figure 5.
2.1 Error Amplifier Block
The error amplifier block consists of a transconductance
amplifier, output OVP comparator, and disable comparator.
For the output voltage control, a transconductance amplifier
is used instead of the conventional voltage amplifier. The
transconductance amplifier (voltage controlled current
source) aids the implementation of OVP and disable function. The output current of the amplifier changes according
to the voltage difference of the inverting input and the noninverting input of the amplifier. The output voltage of the
amplifier is compared with the internal ramp signal to generate the switch turn-off signal. The OVP comparator shuts
down the output drive block when the voltage of the INV pin
is higher than 2.675V and there is 0.175V hysteresis. The
disable comparator disables the operation of the FAN7530
when the voltage of the inverting input is lower than 0.45V
and there is 100mV hysteresis. An external, small-signal
MOSFET can be used to disable the IC, as shown in Figure
4. The IC operating current decreases to under 65µA to
reduce power consumption if the IC is disabled.
Turn-on
Signal
Timer
S
Q
R
VIN
ZCD
5
6.5V
1.4V 1.5V
Zero Current
Detector
Figure 5. Zero Current Detector Block
2.675V
OVP
Disable
0.45V
2.5V
Gm
2
IPEAK
0.35V
tzero
Inductor
Current
V OUT
V ref (2.5V)
Error
Amp
Figure 6 shows typical ZCD-related waveforms. Because the
ZCD pin has some capacitance, there can be some delay
caused by Rzcd and the turn-on time can be delayed.
0A
ton
tdis
INV
toff
1
COMP
INEG
Disable
Signal
n·(V OUT-V IN)
V AUX
0V
-n·V IN
Delay Time
V clamp
Figure 4. Error Amplifier Block
ZCD
Voltage
V th
R ZCD Delay
2.2 Zero Current Detection Block
OUT
The zero current detector (ZCD) generates the turn-on signal
of the MOSFET when the boost inductor current reaches
zero using an auxiliary winding coupled with the inductor.
Because the polarity of the auxiliary winding is opposite the
inductor winding, the auxiliary winding voltage is negative
and proportional to the rectified AC line voltage when the
MOSFET is turned on. If the MOSFET is turned off, the
voltage becomes positive and proportional to the difference
between VOUT and VIN. If the inductor current reaches zero,
© 2006 Fairchild Semiconductor Corporation
Rev. 1.0.3 • 1/11/07
0V
V OUT
V DS
Minimum
Voltage Turn-on
0V
Figure 6. Zero Current Detector Waveform
www.fairchildsemi.com
3
AN6027
APPLICATION NOTE
Ideally, the switch must be turned on when the inductor current reaches zero; but because of the structure of the ZCD
block and Rzcd delay, it is turned on after some delay time.
During this delay time, the stored charge of the COSS (MOSFET output capacitor) is discharged through the path indicated in Figure 7. This charge is transferred into a small filter
capacitor, Cin1, which is connected to the bridge diode.
Therefore, there is no current flow from the input side,
meaning the input current Iin is zero during this period. For
better total harmonic distortion (THD), it is important to
make tzero / TS as small as possible. As shown in Figure 6,
tzero is proportional to L ⋅ C oss but ton and tdis are proportional to L. Therefore tzero / TS is approximately inversely
proportional to L . Therefore THD increases as the inductance decreases. Reducing the inductance can decrease the
inductor size and cost but the switching loss increases
because of the increased switching frequency. In real case,
boost diode’s junction capacitance and boost inductor’s parasitic capacitance should be added to COSS when calculating
tzero. That means it is important to minimize the parasitic
capacitance of the boost inductor and diode junction capacitance for better THD.
iin
L
AC
IN
D
Off Signal
1V Offset
MOT
Sawtooth
Generator
3
2.9V
Error Amp
Output
Figure 8. Sawtooth Generator Block
2.4 Over-Current Protection Block
The MOSFET current is sensed using an external sense
resistor for over-current protection. If the CS pin voltage is
higher than 0.8V, the over-current protection comparator
generates a protection signal to turn off the MOSFET. An
internal R/C filter has been included to filter switching noise.
CS 4
OCP
S ig n a l
40k
8pF
0 .8 V
V OUT
O v e r-C u rre n t
P ro te c tio n
C o m p a ra to r
iL
C IN1
CO
Q
Figure 9. Over-Current Protection Block
C OSS
2.5 Switch Drive Block
The FAN7530 contains a single totem-pole output stage
designed specifically for a direct drive of a power MOSFET.
The drive output is capable of up to 500mA peak sourcing
current and 800mA peak sinking current with a typical rise
and fall time of 50ns with a 1.0nF load. Additional circuitry
has been added to keep the drive output in a sinking mode
whenever the UVLO is active. The output voltage is
clamped at 13V to protect the MOSFET gate even when the
VCC voltage is higher than 13V.
Figure 7. Current Flow During tzero
In the ZCD block, there is an internal timer to provide a
means to start or restart the switching if the drive output has
been low for more than 150µs from the falling edge of the
drive output. Without this timer, the PFC converter does not
work because the inductor current is always zero when the
IC initially starts operation and the ZCD winding voltage
does not become positive without any switching.
2.3 Sawtooth Generator Block
The output of the error amplifier and the output of the sawtooth generator are compared to determine the MOSFET
turn-off instant. The slope of the sawtooth is determined by
an external resistor connected at the maximum on time
(MOT) pin. The voltage of the MOT pin is 2.9V and the
slope is proportional to the current flowing output of the
MOT pin. The maximum on time is determined when the
output of the error amplifier is 5V. When a 40.5kΩ resistor is
connected, the maximum on time is 24µs. As the resistance
increases, the maximum on time increases, because the slope
decreases. The MOSFET on time is zero when the output of
the error amplifier is lower than 1V.
© 2006 Fairchild Semiconductor Corporation
Rev. 1.0.3 • 1/11/07
www.fairchildsemi.com
4
AN6027
APPLICATION NOTE
3.Circuit Components Design
3.1 Power Stage Design
4 ⋅ fsw (min)
1) Boost Inductor Design
The boost inductor value is determined by the output power
and the minimum switching frequency. The minimum
switching frequency must be above the audio frequency
(20kHz) to prevent audible noise. The maximum switching
period, TS(max), is a function of Vin(peak) and Vo, the output
voltage. It can have a maximum value at the highest input
voltage or at the lowest input voltage according to Vo. Compare TS(max) at Vin(peak_min) and Vin(peak_max), then select the
higher value for the maximum switching period. The boost
inductor value can be obtained by Equation 6.
ton = L ⋅
IL( peak ) (t )
Vin( peak ) sin(ωt )
= L⋅
= L⋅
toff = L ⋅
= L⋅
2 ⋅ Iin( peak ) sin(ωt )
Vin( peak ) sin(ωt )
⎞
⎟
⎟
⎠
(6)
The auxiliary winding voltage is lowest at the highest line.
So the turn number of the auxiliary winding can be obtained
by Equation 7. The voltage should be higher than the ZCD
threshold voltage of 1.5V.
1.5V ⋅ NP
Naux >
(1)
(7)
(Vo − 2Vin( peak _ max) )
3) Input Capacitor Design
The voltage ripple of the input capacitor is maximum when
the line is lowest and the load is heaviest. If fsw(min) >> fac,
the input current can be assumed to be constant during a
switching period.
Vin( peak )
Inductor
Current
2 ⋅ I in
(2)
Vo − Vin( peak ) sin(ωt )
2 ⋅ Iin( peak ) sin(ωt )
Input
Current
Vo − Vin( peak ) sin(ωt )
2 ⋅ Vo ⋅ Io
η ⋅ Vin( peak )
I in
t on / 2
(3)
t on
t off
Figure 10. Input Current and Inductor Current Waveform
During a Switch Cycle
TS = ton + toff
⎛
⎞
1
sin(ωt )
= 2 ⋅ L ⋅ Iin( peak ) ⎜
+
⎟ (4)
⎜ Vin( peak ) Vo − Vin( peak ) sin(ωt ) ⎟
⎝
⎠
Vin( peak ) ⋅ sin(ωt ) ⎞
4 ⋅ L ⋅ Vo ⋅ Io ⎛
=
⎜1+
⎟
2 ⎜
η ⋅ Vin( peak ) ⎝ Vo − Vin( peak ) sin(ωt ) ⎟⎠
4 ⋅ L ⋅ Vo ⋅ Io (max) ⎛
Vin ( peak )
=
⎜1 +
2
⎜
Vo − Vin ( peak )
η ⋅ Vin ( peak )
⎝
⎛
Vin ( peak )
⋅ Vo ⋅ Io (max) ⎜ 1 +
⎜
V
o − Vin ( peak )
⎝
2) Auxiliary Winding Design
2 ⋅ Iin( peak )
IL( peak ) (t )
Iin( peak ) =
TS (max)
η ⋅ Vin ( peak )2
L=
⎞
⎟
⎟
⎠
Cin ≥
≥
≥
(5)
2
ton
2
0
ΔVin(max) ∫
Iin ( peak _ max)
⎛
⎜⎜ Iin( peak _ max) − 2
ton
⎝
ton ⋅ Iin( peak _ max)
2 ⋅ ΔVin(max)
⎞
t ⎟⎟ dt
⎠
(8)
L ⋅ Io2(max) ⋅ Vo2
ΔVin(max) ⋅ Vin3( peak _ min)
The input capacitor must be larger than the value calculated
by Equation 8 and the maximum input capacitance is limited
by the input displacement factor (IDF), defined as IDF≡cosθ.
As shown in Figure 11, the input capacitor generates 90°
© 2006 Fairchild Semiconductor Corporation
Rev. 1.0.3 • 1/11/07
www.fairchildsemi.com
5
AN6027
APPLICATION NOTE
4) Output Capacitor Design
leading current, which causes phase difference between the
line current and the line voltage. The phase difference
increases as the capacitance of the input capacitor increases.
Therefore, the input capacitor must be smaller than Cin(max)
calculated by Equation 12. Cin(max) is the sum of all the
capacitors connected at the input side.
Va = VA = Vin( peak ) cos(ωt )
The output capacitor is selected by the relationship between
the input and output power. As shown in Figure 13, the minimum output capacitance is determined by Equation 14.
IIN
(9)
ID
+
+
i A = i a + ic = Ia cos(ωt ) − ω ⋅ Cin ⋅ Vin( peak ) sin(ωt )
LOAD
CO
VIN
i a = Ia cos(ωt )
IO
PFC
−
(10)
VO
−
Figure 12. PFC Configuration
⎛ ω ⋅ Cin ⋅ Vin( peak ) ⎞
⎟⎟
Ia
⎝
⎠
Ia
=
tan cos−1(IDF )
ω ⋅ Vin( peak )
θ = tan−1 ⎜⎜
Cin(max)
(
=
2 ⋅ Vo ⋅ Io
ω ⋅ Vin2( peak _ max)
(11)
Pin = Iin( rms ) ⋅ Vin( rms ) ⋅ (1 − cos(2ωt ) ) = IDVo
)
ID =
(
tan cos−1(IDF )
)
Iin ( rms ) ⋅ Vin( rms )
Vo
(1 − cos(2ωt ))
= Io ⋅ (1 − cos(2ωt ) )
(12)
(13)
ID(avg) = IO (1- cos(2ωt))
Lin
iA
ia
iC
+
Cin
VA
−
IO
+
PFC
Circuit
Va
ΔVO =
−
IO
ωCO
VO
Input Filter
Figure 13. Diode Current and Output Voltage Waveform
Im
iA
Co(min) ≥
iC
θ
ia
2π ⋅ fac ⋅ ΔVo(max)
(14)
5) MOSFET and Diode Selection
Re
The maximum MOSFET RMS current is obtained by Equation 15 and the conduction loss of the MOSFET is calculated
by Equation 16. When MOSFET turns on, the MOSFET current rises from zero, so the turn-on loss is negligible. The
MOSFET turn-off loss and the MOSFET discharge loss are
obtained by Equations 17 and 18, respectively. The switching frequency of the critical conduction mode boost PFC
converter varies according to the line and load conditions.
VA
Figure 11. Input Voltage and Current Displacement Due to
Input Filter Capacitance
© 2006 Fairchild Semiconductor Corporation
Rev. 1.0.3 • 1/11/07
Io(max)
www.fairchildsemi.com
6
AN6027
APPLICATION NOTE
The switching frequency is the average value during a line
period. The total MOSFET loss can be calculated by Equation 19 and a MOSFET can be selected considering the
MOSFET thermal characteristic.
IQrms = IL( peak _ max)
=
η ⋅ Vin(LL )
1 4 2 ⋅ Vin( LL )
−
6
9π ⋅ Vo
2
Pon = IQrms
⋅ RDSon
=
R o1
1 4 2 ⋅ Vin( LL )
−
6
9π ⋅ Vo
2 2 ⋅ Vo ⋅ Io(max)
Pturn −off =
PFC OUT
1
Cp
(15)
4
Coss.Vo ⋅ Vo2 ⋅ fsw
3
+ Pturn −off + Pdisch arg e
Pdisch arg e =
PMOSFET = Pon
Figure 14. Output Voltage Sensing Circuit
(17)
The feedback loop bandwidth must be lower than 20Hz for
the PFC application. If the bandwidth is higher than 20Hz,
the control loop may try to reduce the 120Hz ripple of the
output voltage and the line current may be distorted, decreasing the power factor. A capacitor is connected between
COMP and GND to eliminate the 120Hz ripple voltage by
40dB. If a capacitor is connected between the output of the
error amplifier and the GND, the error amplifier works as an
integrator and the error amplifier compensation capacitor
can be calculated by Equation 23. To improve the power factor, Ccomp must be higher than the calculated value. If the
value is too high, the output voltage control loop may
become slow.
(18)
(19)
The diode average current can be calculated by Equation 20.
The total diode loss can be calculated by Equation 21. Select
a diode considering diode thermal characteristic.
IDavg = Io(max)
(20)
PDiode = Vf ⋅ IDavg
(21)
Ccomp = gm ⋅
3.2 Control Circuit Design
1)
Output Voltage Sensing Resistor and Feedback Loop
Design
© 2006 Fairchild Semiconductor Corporation
Rev. 1.0.3 • 1/11/07
Ro 2
0.01⋅ 2π ⋅ 120Hz ⋅ (Ro1 + Ro 2 )
(23)
To improve the output voltage regulation, a resistor and a
capacitor can be added to a simple integrator, as shown in
Figure 15. The resistor, Rcomp, increases mid-band gain and
the capacitor, Cfilter, which is 1/10~1/5 of the Ccomp, is used
to filter high-frequency noise. The gain of the error amplifier
with the circuit in Figure 15 is shown in Figure 16.
The output voltage sensing resistors, Ro1 and Ro2, are determined by the output voltage at the high line by Equation 22.
The output voltage sensing resistors cause power loss, therefore Ro1 should be higher than 1MΩ. Too high resistance can
cause some delay of the OVP circuit due to internal capacitance (Cp), which may slightly increase the OVP level.
Ro1 Vo _ high − 2.5
=
Ro 2
2.5
R o2
(16)
1
Vo ⋅ IL( peak _ max) ⋅ tf ⋅ fsw
6
2
2 Vo ⋅ Io(max)
⋅ tf ⋅ fsw
3 η ⋅ Vin( LL )
INV
(22)
www.fairchildsemi.com
7
AN6027
APPLICATION NOTE
crossing point of the AC line, as shown in Figure 18. To minimize the zero crossing distortion, COSS must be minimized
and a larger inductor should be used. There is a limitation in
minimizing COSS and using a large inductor because a small
MOSFET increases MOSFET conduction loss and a larger
inductor is more expensive.
VOUT
Error
Amp
Ro1
INV
1
Gm
Ro2
Vref
3
INEG =
(25)
COMP
IPEAK
Rcomp
tzero
Inductor
Current
Cfilter
Ccomp
Coss
⋅ (Vo − Vin )
L
0A
ton
tdis
INEG
toff
Figure 15. Error Amplifier Circuit
n·(VOUT-VIN)
VAUX
Integrator
C comp
0V
-n·VIN
Proportional gain
R comp
Delay Time
Freq
Vclamp
ZCD
Voltage
C filter
High frequency
Noise filter
Vth
RZCD Delay
0V
OUT
Figure 16. Gain of the Error Amplifier
Figure 17. ZCD Waveforms
2) Zero Current Detection Resistor Design
If the RZCD is selected appropriately, the MOSFET can be
turned on when the Vds voltage is minimum to reduce
switching loss. It is recommended to design the RZCD to turn
on the MOSFET when the Vds voltage is minimum.
The ZCD current should be less than 10mA; therefore the
zero current detection resistor, RZCD is determined by Equation 24.
⎛ N ⋅V
⎞
RZCD = ⎜ aux o − 5.8V ⎟ /10mA
⎜ Np
⎟
⎝
⎠
To improve the zero crossing distortion, the MOSFET turnon time should be increased near the AC line zero crossing
point. If a resistor is connected between the MOT and the
auxiliary winding, as shown in Figure 19, the function can be
implemented easily. Because the auxiliary winding voltage is
negatively proportional to the input voltage during the MOSFET turn-on time, the current I2 is proportional to the input
voltage (as shown in Figure 19). Therefore, the slope of the
internal ramp changes according to input voltage as the current flowing out of the MOT pin changes, as shown in Figure
20. I2 current is maximum at the highest line voltage and the
zero crossing improvement is best when I2 is 100% ~ 200%
of I1. R2 value should be chosen by experiment.
(24)
Because the ZCD pin has some capacitance, the ZCD resistor and the capacitor cause some delay for ZCD detection, as
shown in Figure 17. Because of this delay, the MOSFET is
not turned on when the inductor current reaches zero and the
MOSFET junction capacitor and the inductor resonate. The
inductor current changes its direction and flows negatively.
The peak value of this negative current is determined by
Equation 25. As shown in Equation 25, the negative current
increases as the input voltage is close to zero and COSS
increases. This negative current decreases average inductor
current and causes zero crossing distortion near the zero
© 2006 Fairchild Semiconductor Corporation
Rev. 1.0.3 • 1/11/07
www.fairchildsemi.com
8
AN6027
APPLICATION NOTE
3) Start-up Circuit Design
To start up the FAN7530, the start-up current must be supplied through a start-up resistor. The resistor value is calculated by Equations 26 and 27. The start-up capacitor must
supply IC operating current before the auxiliary winding
supplies IC operating current, maintaining VCC voltage
higher than the UVLO voltage. The start-up capacitor is
determined by Equation 28.
Output
Voltage
1st
Input
Current
3rd
RST ≤
5th
Vin( peak _ min) − Vth(st )max
PRST =
CST ≥
Figure 18. Zero Crossing Distortion
(26)
IST max
Vin2( rms _ max)
≤ 1W
(27)
Idcc
2π ⋅ fac ⋅ HY(ST )min
(28)
RST
4) Current Sense Resistor Design
L
AC
IN
VAUX
I2
D
The CS pin voltage is highest when the AC line voltage is
lowest and the output power is maximum. The current sense
resistor is determined by Equations 29 and 31, limiting the
power loss of the resistor to under 1W.
VO
NAUX
RZCD
R2 ZCD
Rsense <
CO
VCC
FAN7529
INV
PRsense
MOT
CS
I1
COMP
R1
0.8V
IL( peak _ max)
η ⋅ Vin( peak _ min)
⎛ Vo ⋅ Io(max)
= 2⋅⎜
⎜
⎝ η ⋅ Vin( peak _ min)
Rsense <
GND
= 0.8V
4 ⋅ Vo ⋅ Io(max)
(29)
2
⎞
⎟ ⋅ Rsense < 1W
⎟
⎠
1 ⎛ η ⋅ Vin ( peak _ min)
⋅⎜
2 ⎜⎝ Vo ⋅ Io(max)
⎞
⎟
⎟
⎠
(30)
2
(31)
Figure 19. Zero Crossing Improvement Circuit
Ramp Slope
Change
Slope
Decrease
VAC
Slope Increase
VEAO
On-time Increase
Ramp
Variable On-time
On-time Decrease
Figure 20. On-Time Variation According to VAC
© 2006 Fairchild Semiconductor Corporation
Rev. 1.0.3 • 1/11/07
www.fairchildsemi.com
9
AN6027
APPLICATION NOTE
4. Design Example
A 100W converter is used here to illustrate the design procedure using a design spreadsheet. Enter the system parameters
in the file to get the designed parameters. The system parameters are as follows:
•
•
•
•
•
•
•
•
•
Maximum output power
Input voltage range
Output voltage
AC line frequency
PFC efficiency
Minimum switching frequency
Input displacement factor (IDF)
Input capacitor ripple voltage
Output voltage ripple
100W
90Vrms~264Vrms
392V
60Hz
90%
37kHz
0.98
24V
8V
4.1 Inductor Design
The boost inductor is determined by Equation 6. Calculate it
at both the lowest voltage and the highest voltage of the AC
line and choose the lower value. The calculated value in this
example is 403µH. To get the calculated inductor value,
EI30 core is used and the primary winding is 44 turns. The
air gap is 0.6mm at both legs of the EI core. The auxiliary
winding number, determined by Equation 7, is five; but if
more windings are used, the number is six.
ZCD pin and the ground to increase the delay time for the
MOSFET minimum voltage turn-on.
4.7 Start-up Circuit Design
The maximum start-up resistor is 1.63MΩ and the minimum
is 140kΩ, as determined by Equations 26-27. The selection
is 330kΩ. The VCC capacitance must be larger than 7µF, calculated by Equation 28, so the selected value is 47µF.
4.8 Current Sense Resistor Design
The maximum current sense resistance is 0.23Ω as a result
of Equation 31 and the selected value is 0.2Ω.
4.9 MOT Resistor Design
The MOT resistor is determined to get the maximum on-time
when the AC line voltage is lowest and the output power is
maximum. The calculated value is 20.44kΩ and the maximum on-time is 12.26µs. To improve THD performance, a
33kΩ resistor is used for the MOT resistor and a 370kΩ
resistor is connected between the MOT pin and the auxiliary
winding. The maximum on-time is determined by Equation
32 and the MOT resistor is determined by Equation 33.
MOT =
4.2 Input Capacitor Design
The minimum input capacitance is determined by the input
voltage ripple specification. The calculated minimum input
capacitor value is 0.33µF. The maximum input capacitance
is restricted by the IDF. The calculated value is 0.77µF. The
selected value is 0.63µF (sum of all the capacitors connected
to the input side, C1, C2, C3, C4, and C5).
4.3 Output Capacitor Design
The minimum output capacitor is determined by Equation 14
and the calculated value is 85µF. The selected value for the
capacitor is 100µF.
4.4 MOSFET and Diode Selection
RMOT >
(33)
Error Amp. Output
Switching
Nosie
The upper output voltage sense resistor is chosen to be 2MΩ
and the bottom output voltage sense resistor is 12.6kΩ. The
error amplifier compensation capacitance must be larger
than 0.1µF, as calculated by Equation 23. Therefore, 0.22µF
capacitor is used.
© 2006 Fairchild Semiconductor Corporation
Rev. 1.0.3 • 1/11/07
MOT
× 1012
600
(32)
As shown in Figure 21, noise voltage can be added to the
internal ramp signal during MOSFET turn-on. Because of
this noise, the AC line current waveform can be distorted if
the error amplifier output voltage is close to 1V. It is recommended to use higher resistor for MOSFET turn-on if there
is waveform distortion and use a turn-off diode to speed up
the turn-off process.
4.5 Output Voltage Sense Resistor and
Feedback Loop Design
The calculated value is 3.1kΩ and the selected value is
20kΩ. A 47pF ceramic capacitor is connected between the
⋅ 10−6
4.10 MOSFET Gate Drive Resistor Design
By calculating Equations 15-19, a 500V/13A MOSFET
FQPF13N50C is selected, and a 600V/1A diode BYV26C is
selected by the result of Equations 20-21.
4.6 Zero Current Detection Resistor Design
2 ⋅ L ⋅ Po
η ⋅ Vin2( rms _ min)
Internal
Ramp Signal
IC OUT Signal
Figure 21. Turn-on Noise on Internal Ramp Signal
Figure 22 shows the designed application circuit diagram and
Table 2 shows the 100W demo board components list.
www.fairchildsemi.com
10
AN6027
APPLICATION NOTE
T1
PFC OUTPUT
VAUX
D2
C5
R4
R3
R5
V1
5
6
C6
CS
COMP
R1 R8
F1
ZCD
7
R11
4
2
1
INV
C1
C9
FAN7530
R2
3
C2
R6
C11
OUT
Vcc
8
D1
GND
ZD1
C3 C4
LF1
Q1
MOT
NTC
R10
D3
C10
R9
BD
C7
R7
C8
AC INPUT
Figure 22. Application Circuit Schematic
© 2006 Fairchild Semiconductor Corporation
Rev. 1.0.3 • 1/11/07
www.fairchildsemi.com
11
AN6027
APPLICATION NOTE
Table 2. 100W Demo Board Part List
PART#
VALUE
NOTE
PART#
Fuse
F1
V1
RT1
VALUE
NOTE
Capacitor
250V/3A
C1
150nF/275VAC
Box Capacitor
TNR
C2
470nF/275VAC
Box Capacitor
C3,C4
2.2nF/3kV
Ceramic Capacitor
NTC
C6
22µF/25V
Electrolytic Capacitor
10D-9
C7
47nF/50V
Ceramic Capacitor
Resistor
C8
220nF
MLCC
471
470V
R1
42kΩ
1/4W
C9
100µF/450V
Electrolytic Capacitor
R2
370kΩ
1/4W
C10
12nF/100V
Film Capacitor
R3
330kΩ
1/2W
C11
47pF/50V
Ceramic Capacitor
R4
150Ω
1/2W
R5
20kΩ
1/4W
BD
KBL06
Fairchild
R6
100Ω
1/4W
D1
1N4148
Fairchild
R7
0.2Ω
1/2W
D2
BYV26C
600V/1A
R8
10kΩ
1/4W
D3
SB140
Fairchild
R9
10kΩ
1/4W
ZD1
1N4746
Fairchild
R10
2MΩ
1/4W
R11
12.6kΩ
1/4W
IC1
LF1
Diode
Inductor
T1
400µH(44T:6T)
EI3026
IC
Primary: 0.2φ*10, from Pin 5 to Pin 3
FAN7530
Secondary: 0.2φ, from Pin 2 to Pin 4
Line Filter
MOSFET
38mH
Wire 0.45mm
Q1
FQPF13N50C
500V/13A
Table 3. Performance Data
100W
50W
90VAC
110VAC
220VAC
264VAC
PF
0.999
0.998
0.991
0.985
THD
3.97%
4.43%
5.25%
5.47%
Efficiency
90.3%
92.7%
94.7%
95.2%
PF
0.998
0.997
0.974
0.956
THD
4.81%
5.28%
6.74%
7.67%
Efficiency
90.1%
90.8%
91.7%
92.5%
© 2006 Fairchild Semiconductor Corporation
Rev. 1.0.3 • 1/11/07
www.fairchildsemi.com
12
AN6027
APPLICATION NOTE
Table 4. 200W Demo Board Part List (600µH, Wide Input Range Application)
PART#
VALUE
NOTE
PART#
VALUE
Fuse
F1
V1
RT1
NOTE
Capacitor
250V/5A
C1
470nF/275VAC
Box Capacitor
TNR
C2
470nF/275VAC
Box Capacitor
C3,C4
2.2nF/3kV
Ceramic Capacitor
NTC
C6
47µF/25V
Electrolytic Capacitor
10D-9
C7
47nF/50V
Ceramic Capacitor
Resistor
C8
220nF
MLCC
471
470V
R1
37kΩ
1/4W
C9
220µF/450V
Electrolytic Capacitor
R2
250kΩ
1/4W
C10
12nF/100V
Film Capacitor
R3
330kΩ
1/2W
C11
47pF/50V
Ceramic Capacitor
R4
150Ω
1/2W
R5
20kΩ
1/4W
BD
KBU8K
Fairchild
R6
100Ω
1/4W
D1
1N4148
Fairchild
R7
0.1Ω
1W
D2
SUF30J
600V/3A
R8
10kΩ
1/4W
D3
SB140
Fairchild
R9
10kΩ
1/4W
ZD1
1N4746
Fairchild
R10
2MΩ
1/4W
R11
12.6kΩ
1/4W
IC1
LF1
Diode
Inductor
T1
200µH(30T:3T)
PQ3230
IC
Primary: 0.1φ*100, from Pin 5 to Pin 3
FAN7530
Secondary: 0.2φ, from Pin 2 to Pin 4
Line Filter
MOSFET
22mH
Wire 0.7mm
Q1
FDPF20N50
Fairchild
Table 5. Performance Data
200W
150W
100W
85VAC
115VAC
230VAC
265VAC
PF
0.999
0.998
0.993
0.990
THD
3.8%
4.3%
6.5%
6.5%
Efficiency
91.8%
94.8%
96.9%
97.3%
PF
0.999
0.998
0.990
0.985
THD
4.7%
5.2%
7.0%
6.9%
Efficiency
93.3%
95.5%
96.9%
97.0%
PF
0.997
0.996
0.981
0.971
THD
6.5%
7.4%
9.0%
8.5%
Efficiency
94.3%
95.3%
96.2%
96.0%
© 2006 Fairchild Semiconductor Corporation
Rev. 1.0.3 • 1/11/07
www.fairchildsemi.com
13
AN6027
APPLICATION NOTE
Table 6. 300W Wide Input Range Application Part List
PART#
VALUE
NOTE
PART#
Fuse
F1
V1
RT1
VALUE
NOTE
Capacitor
250V/5A
C1
680nF/275VAC
Box Capacitor
TNR
C2
680nF/275VAC
Box Capacitor
C3,C4
2.2nF/3kV
Ceramic Capacitor
NTC
C6
47µF/25V
Electrolytic Capacitor
6D-22
C7
33nF/50V
Ceramic Capacitor
Resistor
C8
220nF
MLCC
471
470V
R1
60kΩ
1/4W
C9
33µF/450V
Electrolytic Capacitor
R2
330kΩ
1/4W
C10
12nF/100V
Film Capacitor
R3
330kΩ
1/2W
C11
9pF/50V
Ceramic Capacitor
R4
100Ω
1/2W
R5
20kΩ
1/4W
BD
KBU8J
Fairchild
R6
100Ω
1/4W
D1
1N4148
Fairchild
R7
0.06Ω
1W
D2
SUF30J
600V/3A
R8
10kΩ
1/4W
D3
SB140
Fairchild
R9
10kΩ
1/4W
ZD1
1N4746
Fairchild
R10
2MΩ
1/4W
R11
12.6kΩ
1/4W
IC1
LF1
Diode
Inductor
T1
200µH(36T:3T)
PQ3535
IC
Primary: 0.1φ, *100, from Pin 5 to Pin 3
FAN7530
Secondary: 0.2φ, from Pin 2 to Pin 4
Line Filter
MOSFET
40mH
Wire 1mm
Q1
FQA28N50
Fairchild
Table 7. Performance Data
300W
225W
150W
75W
85VAC
115VAC
230VAC
265VAC
PF
0.999
0.998
0.993
0.988
THD
4.5%
4.7%
6.4%
6.5%
Efficiency
91.4%
94.5%
97.4%
97.7%
PF
0.999
0.998
0.989
0.982
THD
3.9%
4.7%
6.1%
6.2%
Efficiency
92.8%
95.1%
97.4%
97.7%
PF
0.998
0.997
0.978
0.963
THD
4.8%
5.8%
7.4%
7.4%
Efficiency
94.0%
95.7%
97.0%
97.3%
PF
0.994
0.989
0.929
0.885
THD
9.3%
10.8%
11.2%
12.0%
Efficiency
94.8%
95.9%
95.3%
95.2%
© 2006 Fairchild Semiconductor Corporation
Rev. 1.0.3 • 1/11/07
www.fairchildsemi.com
14
AN6027
APPLICATION NOTE
Nomenclature
RST: start-up resistance
Ccomp: compensation capacitance
Rzcd: zero current detection resistance
CIN: input capacitance
tf: MOSFET current falling time
COUT: output capacitance
toff: switch off time
CST: start-up capacitance
ton: switch on time
fac: AC line frequency
TS: switching period
fsw(max): maximum switching frequency
Vin (peak): input voltage peak value
fsw(min): minimum switching frequency
Vin (peak_low): input voltage peak value at low line
fsw: switching frequency
Vin (peak_max): maximum input voltage peak value
HY(ST) min: minimum UVLO hysteresis
Vin (peak_min): minimum input voltage peak value
ID: boost diode current
Vin (rms): input voltage RMS value
IDavg: diode average current
Vin (rms_max): maximum input voltage RMS value
IDrms: diode RMS current
Vin (rms_min): minimum input voltage RMS value
Iin (peak): input current peak value
Vin (t): input voltage
Iin (peak_max): maximum of the input current peak value
VO or VOUT: output voltage
Iin (rms): input current RMS value
ΔVin (max): maximum input voltage ripple
Iin (t): input current
ΔVO (max): maximum output voltage ripple
IL (t): inductor current
η: converter efficiency
IL(peak) (t): inductor current peak value during one switching
ω: AC line angular frequency
cycle
IL(peak): inductor current peak value during one AC line
cycle
IL(peak_max): maximum inductor current peak value
IO (max): maximum output current
IO: output current
IQrms: MOSFET RMS current
ISTmax: maximum start-up supply current
L: boost inductance
Naux: auxiliary winding turn number
NP: boost inductor turn number
Pin: input power
PO(max): maximum output power
PO: output power
Rsense: current sense resistance
© 2006 Fairchild Semiconductor Corporation
Rev. 1.0.3 • 1/11/07
www.fairchildsemi.com
15
AN6027
APPLICATION NOTE
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS
HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE
APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS
PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS
WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used
herein:
1. Life support devices or systems are devices or systems which,
(a) are intended for surgical implant into the body, or
(b) support or sustain life, or
(c) whose failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be reason
ably expected to result in significant injury to the user.
© 2006 Fairchild Semiconductor Corporation
Rev. 1.0.3 • 1/11/07
2. A critical component is any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
16
www.fairchildsemi.com
AN-8025
Design Guideline of Single-Stage Flyback AC-DC
Converter Using FAN7530 for LED Lighting
output should be controlled by CC mode in the normal state
while CV mode only works as over voltage protection.
Summary
This application note describes the single-stage power
factor correction (PFC) and presents the design guidelines
of a 75W universal-input, single-stage PFC for LED
lighting applications. Flyback converter topology controlled
by the critical conduction mode control IC, FAN7530 is
applied and several functions; such as CV/CC mode
feedback circuits, cycle-by-cycle current limit, soft-starting
function, and so on, are considered for LED lighting
applications.
Introduction
Figure 2.
Despite large output voltage ripple, single-stage AC-DC
conversion is a more attractive solution than two-stage
conversion from the standpoint of the cost and power
density. Especially in applications like battery chargers,
Plasma Display Panel (PDP)-sustaining power supplies, and
LED lighting; low frequency, 100Hz or 120Hz, large output
voltage ripple is inconsequential.
Circuit Diagram of a Flyback AC-DC
Converter
Single-stage AC-DC converter directly converts AC input
voltage to the DC output voltage without a pre-regulator, as
shown in Figure 1.
This application note presents a 75W single-stage AC-DC
converter for LED lighting. As a power-conversion
topology, flyback converter is normally chosen because it
doesn’t need an inductive output filter; the main transformer
works as an inductive filter itself.
Figure 3.
Block Diagram of FAN7530
Figure 3 shows the block diagram of FAN7530. Its major
features are:
Figure 1.
Single-Stage AC-DC Converter
Figure 2 shows the circuit diagram of a flyback AC-DC
converter. FAN7530 is used as a controller and both CV
(constant voltage) and CC (constant current) mode feedback
circuits are applied to prevent overload and over-voltage
conditions. In LED lighting, the output is always full-load
condition and the forward voltage drop of LED decreases if
the junction temperature of LED increases. Therefore the
© 2009 Fairchild Semiconductor Corporation
Rev. 1.0.1 • 12/29/09
ƒ
ƒ
ƒ
ƒ
ƒ
ƒ
Fixed On Time CRM PFC Controller
Zero Current Detector (ZCS) & Valley Switching
MOSFET Over-Current Protection
Low Startup (40μA) and Operating Current (1.5mA)
Totem Pole Output with High State Clamp
+500/-800mA Peak Gate Drive Current
FAN7530 is a voltage-mode CRM PFC controller; the turnon time of switch is fixed while the turn-off time is varied
during the steady state. Therefore, the switching frequency
varies in accordance with the input voltage variation shown
in Figure 4.
www.fairchildsemi.com
AN-8025
APPLICATION NOTE
A proper turn ratio, N1/N2, should also be considered in a
flyback single-stage AC-DC converter because the
maximum voltage rating of the MOSFET and Fast Recover
Diode (FRD) strongly relates to the turn ratio of
transformer. There is a trade-off relationship between the
drain-to-source voltage rating, Vdss, of MOSFET and the
reverse voltage rating, VR, of the FRD in accordance with
the turn ratio of the transformer. A larger turn ratio (N1/N2)
requires a higher VR of FRD while Vdss, of MOSFET is
decreased. In contrast, a lower turn ratio causes a higher
voltage stress on the MOSFET, while VR of the FRD is
decreased. Figure 6 shows the trade-off relationship
between Vdss of the MOSFET and VR of the FRD.
Vin / Iin
Vin
Average input current
fs
Figure 4.
Switching Frequency Variation
Figure 5.
Theoretical Waveforms
Figure 5 illustrates the theoretical waveforms of the
primary-side switch current, the secondary-side diode
current, and gating signal. MOSFET Q turns on and Fast
Recovery Diode (FRD) Do turns off under zero-current
condition, while Q turns off and Do turns on under the hardswitching condition.
Figure 6.
From Po=ηVinIin, the maximum line current Iin(max) =
Po/ηVin(min). If switching frequency fs is much higher than the
AC line frequency, fac, the input current can be assumed to
be constant during one switching period.
To define the magnetizing inductance of transformer, the
largest period must be defined. The largest switching period
occurs at the peak of input current, Iin(max)_pk, when the
minimum input voltage is applied. It can be defined as:
Design Example
A design guideline of 75W single-stage flyback AC-DC
converter using FAN7530 is presented. The applied system
parameters are shown in Table 1.
Table 1.
Iin (max) _ pk =
System Parameters
Parameter
Value
Output Power
75W
Input Voltage Range
85~265VAC
Output Voltage
45V
Output Limit Voltage
50V
Duty Ratio at Iin(max)_pk, D@ Iin(max)_pk
0.6
Minimum Switching Frequency, fs_min@ Vin_min
50kHz
Efficiency, η
85%
DIQ (max) _ pk
1 DT IQ (max) _ pk
t dt =
∫
T 0
DT
2
(1)
2
I in (max) _ pk
D
(2)
I Q (max) _ pk =
where D = D@ Iin( max ) _ pk , Iin (max) _ pk =
respectively.
2 I in (max) ,
and Vin (min) _ pk = 2Vin (min) ,
The transformer primary-side voltage, VT, is defined as:
VT = Lm
I
f
ΔI
= Lm Q (max) _ pk s (min)
ΔT
D@ Iin(max)_pk
(3 )
Therefore, the magnetizing inductance is calculated by:
1. Flyback Transformer Design
In flyback converter, the transformer is easily saturated
because the transformer is only utilized in the first quadrant
of B-H loop. Moreover, if it works under the critical
conduction mode, the peak current is much higher than that
of the continuous conduction mode. Therefore, air-gap
should be inserted to prevent saturation of the transformer.
© 2009 Fairchild Semiconductor Corporation
Rev. 1.0.1 • 12/29/09
Trade-Off Between VDS and VR
Lm ≥
D@ Iin(max)_pk 2Vin (min)
2 I in (max) _ pk f s (min)
=
0.62 × 85
2 ×1.04 × 50 × 103
(4 )
−6
= 294 × 10
From Equation (4) and Table 1, the calculated magnetizing
inductance is 294μH.
www.fairchildsemi.com
2
AN-8025
APPLICATION NOTE
There are several methods defining the turn number for the
desirable inductance, but using the AL-value is the most
common and the easiest. The turn number can be obtained
with AL-value as:
The maximum reverse voltage and the forward peak current
of the FRD are:
L
AL − value
17
= 50 + × 2 × 265 = 195V
44
2
2
75
=
Io =
×
= 7.5 A
1 − D@ Iin (max) _ pk
(1 − 0.6 ) 45
N=
VR (max) = Vo _ Limit +
(5 )
However, if air-gap is inserted into the magnetic core, a
designer should find the AL-value. To obtain AL-value,
wind several turns into a bobbin and measure the
inductance, then calculate AL-value with the equation:
AL − value =
L
N2
I R _ pk
(
N2
Vin (max) _ pk
N1
)
(12)
(13)
respectively. Therefore, the Ultra-Fast Rectifier Diode
(UFRD), F06UP20S (200V, 6A, VF=1.15V), is finally
chosen in consideration of the margins.
(6 )
3. Snubber Circuit Design
Once the AL-value is obtained, calculate the turn number
using Equation (6).
In flyback converter, the resonant between Lleak and Coss
causes an excessively high voltage surge that causes damage
to the MOSFET during turn-off. This voltage surge must be
suppressed and a snubber circuit is therefore necessary to
prevent MOSFET failures.
Applying coil dummy EER3435 with 0.33mm of air gap for
the transformer and 14.9μH is measured when 10 turns are
winded into the core and 0.149×10-6 of AL-value is
obtained. Therefore, the calculated primary-side turn
number is 44.4 from Equation (6) and finally determines 44
as the primary-side turn number. (The actual inductance is
measured as 330μH.)
The secondary-side turn number is obtained as 17 turns by
following equation:
N2 =
π N1Vo (1 − Dmax )
2 2 DmaxVin (min)
=
π × 44 × 45(1 − 0.6)
2 2 × 0.6 × 85
= 17
(7 )
2. MOSFET and FRD
The voltage stress of MOSFET is calculated as:
Vds (max) = Vin (max) _ pk + Vsn (max)
= Vin (max) _ pk + V f + VLk
(8 )
where Vsn is the maximum capacitor voltage of the snubber
circuit, Vf is the flyback voltage, and VLr is the ringing
voltage at the leakage inductance of the transformer. Vf is
derived by N1Vo/N2 and VLr is normally estimated as 1.5
times of the flyback voltage, Vf. Therefore, the maximum
voltage of MOSFET is obtained as:
44
⎛ 44
⎞
Vds (max) = 2 × 265 + × 45 + 1.5 ⎜ × 45 ⎟ = 665.94V (9)
17
⎝ 17
⎠
The maximum rms current and the peak current are:
Po
75
I in (max) =
=
= 1.04 A
(10)
ηVin (min) 0.85 × 85
Figure 7.
The clamping voltage by snubber is:
Vsn = V f + Lleak
I Q (max) _ pk =
η D@ Iin(max)_pkVin (min)
2 2 × 75
=
= 4.89 A
0.85 × 0.6 × 85
ts =
(11)
(14)
Lleak × I Dsn _ pk
Vsn − V f
=
Lleak × I Dsn _ pk
1.5V f
(15)
The maximum power dissipation of the snubber circuit is
determined by:
respectively.
Therefore, an N-Channel enhancement-mode MOSFET,
FQPF8N80C (800V, 8A, RDS_ON = 1.55Ω), is chosen in
consideration of the margins.
© 2009 Fairchild Semiconductor Corporation
Rev. 1.0.1 • 12/29/09
I Dsn _ pk
Δi
= V f + Lleak
Δt
ts
Therefore:
and
2 2 Po
Snubber Circuit
Psn =
1 ts
1
VsniDsn (t )dt = Lleak I Dsn _ pk 2 f s
∫
0
2
T
(16)
www.fairchildsemi.com
3
AN-8025
APPLICATION NOTE
The maximum power dissipation is:
Psn (max) =
4. Sensing Resistor
2
v
1
Lleak I Dsn _ pk 2 f s @ vin max = c
Rsn
2
The CS pin of FAN7530 limits the peak current and
protects the MOSFET during transient state or over load
condition. Normally, it is reasonable to limit to 1.5 times the
switching peak current. The limiting level of switching peak
current and the sensing resistor are obtained as:
(17)
where vc=Vsn=Vf +VLr.
Therefore, the resistance, Rsn, is determined by:
Rsn =
2vc 2
Lleak I Dsn _ pk 2 f s @ vin max
(18)
The maximum ripple voltage of the snubber circuit is
obtained by:
Δvc =
vc
Csn Rsn f s @ vin max
(19)
The larger snubber capacitor results, the lower voltage
ripple, but the power dissipation increases. Consequently,
selecting the proper value is important. In general, it is
reasonable to determine that the surge voltage of snubber
circuit, Vsur is 1.5 times of the flyback voltage, Vf and the
ripple voltage, Δvc is 50V. Thus, the snubber resistor and
capacitor are determined by the following equations:
I Dsn _ pk @Vin = 265V =
2 2 Po
η DminVin
= 1.5 ×
N1
Vo _ Limit
N2
44
50 = 194.1V
17
15 ×10−6 × 2.85
= 220.3n s
194.1
DminVsur
f s @ vin( max ) =
Lm I Dsn _ pk @Vin= 265V
ts =
0.33 × 194
= 75.63kHz
297 ×10−6 × 2.85
2 ×1942
Rsn =
= 23.3k Ω
15 × 10−6 × 2.85 × 75.63kHz
Csn =
=
Switching Current Limit
I Q _ Limit = 1.5I Q (max) _ pk = 1.5 ×
2 2 × 75
=
= 2.85 A
0.85 × 0.33 × 265
Vsur = 1.5V f = 1.5 ×
Figure 8.
Vsn
Δvc × Rsn × f s @ vin( max )
194 + 129
= 3.67nF
50 × 23.3 × 2.85 × 75.63 × 103
(20)
2
Dmax
⎛
Po ⎞
⎜⎜ 2
⎟⎟
⎝ ηVin (min) ⎠
2 ⎛
75 ⎞
⎜ 2
⎟ = 7.4 A
0.6 ⎝
0.85 × 85 ⎠
0.8
0.8
Rs ≤
=
= 0.11Ω
I Q _ Limit 7.4
(27)
= 1.5 ×
(21)
(28)
5. Soft-starting Circuit
(22)
(23)
(24)
(25)
where the minimum duty ratio is obtained as:
Dmin =
=
Vo
N2
Viavg (max) + Vo
N1
45
⎞
17 ⎛ 2 2
×⎜
× 265 ⎟ + 45
44 ⎝ π
⎠
= 0.33
(26)
Figure 9.
© 2009 Fairchild Semiconductor Corporation
Rev. 1.0.1 • 12/29/09
Soft-Starting Circuit
www.fairchildsemi.com
4
AN-8025
APPLICATION NOTE
Since the FAN7530 is designed for a non-isolated boost
PFC circuit, some circuits are added externally. The internal
disable amplifier can be used as soft-start function when
FAN7530 is applied to non-isolated PFC circuit. However,
the disable amplifier can not participate in the operation if it
is applied to isolated single stage PFC circuit because the
initial voltage at Pin 1 is zero and FAN7530 can not start.
To exclude the disable amplifier from operation, over 0.5V
of voltage must be applied through a blocking diode, as
shown in Figure 9(a).
Experimental Results
To verify the validity of the design guideline in this
application note, a prototype test set-up was built and tested.
The design parameter and component values are shown in
the appendix.
Figure 11shows the input voltage and current at 110VAC
input and 220VAC input conditions. The power factors at
110VAC and 220VAC condition are measured as 0.997 and
0.955, respectively.
The initial VFB is approximately defined as:
VFB _ initial
R1 RFB
=
⋅VCC
RFB ( R1 + R2 ) + R1R2
Figure 12 shows the waveforms of the switching voltage
and current, which shows the switching current waveforms
following the shape of the input voltage well. The switch is
turned on at zero current condition.
(29)
To prevent MOSFET failure due to the initial excessive
switching current, an external soft-start function is
necessary. The circuit shown in Figure 9(b) makes the
output voltage of E/A increase slowly and, consequently,
the converter can be smoothly started in accordance with the
gradual increase of the on time.
Line Voltage
@ 110Vac
Line Current
6. Voltage and Current Feedback
Power supplies for LED lighting must be controlled by
constant current (CC) mode as well as a constant voltage
(CV) mode. Because the forward voltage drop of LED
varies with the junction temperature and the current also
increases greatly consequently, devices can be damaged.
PF=0.997
@ 220Vac
Figure 10 shows an example of a CC and CV mode feedback
circuit. During normal operation, CC mode is dominant and
CV mode only acts as OVP for abnormal modes.
VCC VCC_2
PF=0.955
Vo
C7
R6
R5
C8
Figure 11.
R1
R8
VCC_2
ISO1
D4
R12
VFB
8
1
U1A 4
C12
D8
R21
7
U1B
+
2
3
R17
+
6
R10
R11
Vref2
R18
R13
R19
R20
Vref2
5
R22
R24
Figure 10.
Input Voltage and Current
Io_sen
R25
Example of CC & CV Feedback Circuit
(a) at 110 Vac Input
Figure 12.
© 2009 Fairchild Semiconductor Corporation
Rev. 1.0.1 • 12/29/09
(b) at 220 Vac Input
Switching Voltage and Current
www.fairchildsemi.com
5
AN-8025
APPLICATION NOTE
Figure 13. Drain-Source Voltage and Switching
Current at 265VAC Input Condition
Figure 13 shows the waveforms of the drain-source voltage
and current of 265V of input line voltage, the maximum
input voltage, is applied. The voltage ripple of snubber
circuit is measured at 54V and the maximum voltage stress
is 688V, which shows the actual results are approximately
in accord with the calculation. Since the maximum voltage
is 688V, 800V rating MOSFET is needed for wide input
voltage range.
Figure 15.
In the case of 220Vac input, the maximum efficiency is
measured as 85.95% at full-load condition 75W.
In LED lighting, LED strings are driven by the rating
current and the power supply should be operated under the
full-load condition. Therefore, the power supply is
controlled by constant current during normal condition.
Figure 15 shows the V-I characteristics of the prototype
experimental set-up. The result verifies that the output is
driven well by the constant current control for whole input
voltage condition.
The efficiency characteristics according to the load variation
for 110 Vac and 220 Vac of the input conditions are plotted in
Figure 14. In the case of 110V ac input, the maximum
efficiency is measured as 85.17% at 45W load condition.
Figure 14.
Output V-I Characteristic
Efficiency Comparison
© 2009 Fairchild Semiconductor Corporation
Rev. 1.0.1 • 12/29/09
www.fairchildsemi.com
6
© 2009 Fairchild Semiconductor Corporation
Rev. 1.0.1 • 12/29/09
Figure 16.
7
ZC
VFB
VCC
J1
R23
FUSE1
L1
LF1
R26 C5
C15
D6
R15
R14
C11
C3
R27
R28
C17
R16
C18
D7
C4
D5
BD1
GND
ZCD
COMP
CS
FAN7530
OUT
VCC
D2
I_sense
MOT
INV
U3
C9
VCC
R4
GATE
C5
C16
R29
C14
DZ1
R2
VCC
D3
R3
Q1
D1
R7
RS2
ZC
GATE
C1 RZ1 RZ2 RZ3
VFB
N3_2
N3_3
N1
5
4
3
7
1
R6
DO2
DO1
D8
D4
R5
VCC_2
N3_1
N2
VCC
ZC
8
9
11
14
ISO1
T1
R21
R12
C6
8
U1B
7
C12
3
2
+
5
6
R17
+
VCC_2
R8
CO1 CO2 C2
C7
U1A 4
1
C8
VCC_2
R24
R22
R20
R18
Vref2
R11
RS1
Vref2
R25
R19
R13
R10
RO1 R1
Io_sen
Vref2
U2
R9
VCC_2
C10
Io_sen
J2
Vo
AN-8025
APPLICATION NOTE
Schematic
Schematic
www.fairchildsemi.com
AN-8025
APPLICATION NOTE
Part List
Component
Symbol
Value/Part Number
Rectifier
BD1
Symbol
Value/Part Number
GBU8J
R1
49.9kΩ
C1
472/1kV
R2
15Ω
C2
104
R3
1.5kΩ
C3
220nF
R4
56kΩ/2Watt
C4
440nF
R5
3.3kΩ
C5
474/NP/630V
R6
11kΩ
C6
33µ/35V
R7
1.5/1W
C7
473
R8
100kΩ
C8
224
R9
1.2kΩ
C9
33µ/35V
R10
47kΩ
C10
105
R11
50kΩ
C11
224
R12
11kΩ
C12
155
R13
5.1kΩ
C13
33µ/35V
R14
1.2kΩ
C14
105
R15
10kΩ
C15
683
R16
33Ω
C16
56p
R17
10kΩ
C17
473
R18
2kΩ
C18
224
R19
10Ω
CO1
2200µ/63V
R20
2kΩ
CO2
2200µ/63V
R21
8.2kΩ
D1
UF4005
R22
2kΩ
D2
RGF1J
R23
330kΩ
D3
UF4005
R24
2.1kΩ
D4
1N4148
R25
33Ω
D5
1N4148
R26
30kΩ
D6
1N4148
R27
5.1kΩ
D7
1N4148
R28
100kΩ
D8
1N4148
R29
47kΩ
DO1
F06UP20S
RO1
56kΩ/2Watt
DO2
UF4005
RS1
0.05Ω/5Watt
Zener diode
DZ1
1N4746(18V)
RS2
0.1Ω/5Watt
Fuse
FUSE1
FUSE
RZ1
56kΩ/2Watt
Opto-coupler
ISO1
PC817
RZ2
56kΩ/2Watt
J1
CON4
RZ3
56kΩ/2Watt
Capacitor
Diode
Connector
Component
Resistor
J2
CON4
Transformer
T1
EER3435
Inductor
L1
330µH
Op-Amp.
U1A,B
KA358
Chock-coil
LF1
EMI_CHOCK
Regulator
U2
KA431E
MOSFET
Q1
FQPF8N80C
PFC IC
U3
FAN7530
© 2009 Fairchild Semiconductor Corporation
Rev. 1.0.1 • 12/29/09
www.fairchildsemi.com
8
AN-8025
APPLICATION NOTE
Related Datasheets
FAN7527 — Boundary Mode PFC Control IC
FAN7528 — Dual-Output Critical Conduction Mode PFC Controller
FAN7529 — Critical Conduction Mode PFC Controller
FAN7530 — Critical Conduction Mode PFC Controller
Author
by Jae-Eul Yeon/Ph. D.
HV-PCIA/Fairchild Korea Semiconductor
+82-32-680-1935
E-mail : [email protected]
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS
HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE
APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS
PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS
WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1.
Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body, or
(b) support or sustain life, or (c) whose failure to perform
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to
result in significant injury to the user.
© 2009 Fairchild Semiconductor Corporation
Rev. 1.0.1 • 12/29/09
2.
A critical component is any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
9