RAM Mapping 32 X 4 LCD Controller for I/O uC *********************************************************************************************************** General Descriptions The ESC1621 is a 128-pattern (32x4), memory mapping, and multi- function LCD driver. The S/W configuration feature of the ESC1621 makes it suitable for multiple LCD applications including LCD modules and display subsystems. Only three or four lines are required for the interface between the host controller and the ESC1621. The ESC1621 contains a power down command to reduce power consumption. Features • • • • • • • • • • • • • • • • • • • Operating voltage: 2.4V~5.2V. Built- in 256kHz RC oscillator. External 32.768kHz crystal or 256kHz frequency source input. Selection of 1/2 or 1/3 bias, and selection of 1/2 or 1/3 or 1/4 duty LCD applications. Internal time base frequency sources. Two selectable buzzer frequencies (2kHz/4kHz). Built- in time base generator and WDT. Time base or WDT overflow output. Power down command reduces power Consumption. 8 kinds of time base/WDT clock sources. 32x4 LCD driver. Built- in 32x4 bit display RAM. 3-wire serial interface. Internal LCD driving frequency source. Software configuration feature. Data mode and command mode instructions. R/W address auto increment. Three data accessing modes. VLCD pin for adjusting LCD operating voltage. p. 1 Last update: 2004-03-05 12:03 ESC1621 Block Diagram BZ BZ Tone Generator Watchdog Timer & Time Base Generator VDD GND IRQ VLCD COM0 CS LCD Driver & Bias Circuit WR RD DATA Control Logic & Timing Generator COM3 SEG0 SEG31 OSCI OSCO Display Memory Note: CS: Chip selection BZ, BZ: Tone outputs WR, RD, DATA: Serial interface IRQ: Time base or WDT overflow output COM0~COM3, SEG0~SEG31: LCD outputs p. 2 Last update: 2004-03-05 12:13 ESC1621 Pin Assignment ESC1621B-48SSOP ESC1621D-28SKDIP p. 3 Last update: 2004-03-05 12:13 ESC1621 Pad Description Pad No. 1 Pad Name CS I/O Function I Chip selection input with pull-high resistor When the CS is logic high, the data and command read from or written to the ESC1621 are disabled. The serial interface circuit is also reset. But if CS is at logic low level and is input to the CS pad, the data and command transmission between the host controller and the ESC1621 are all enabled. 2 RD I READ clock input with pull-high resistor Data in the RAM of the ESC1621 are clocked out on the falling edge of the RD signal. The clocked out data will appear on the DATA line. The host controller can use the next rising edge to latch the clocked out data. 3 WR I WRITE clock input with pull-high resistor Data on the DATA line are latched into the ESC1621 on the rising edge of the WR signal. 4 DATA I/O Serial data input/output with pull-high resistor 5 GND — Negative power supply, ground 6 OSCO O 7 OSCI I The OSCI and OSCO pads are connected to a 32.768kHz crystal in order to generate a system clock. If the system clock comes from an external clock source, the external clock source should be connected to the OSCI pad. But if and on-chip RC oscillator is selected instead, the OSCI and OSCO pads can be left open. 8 VLCD I 9 VDD — Positive power supply 10 IRQ O Time base or WDT overflow flag, NMOS open drain output 11,12 BZ, BZ O 2kHz or 4kHz tone frequency output pair 13~16 COM0~COM3 O LCD common outputs 48~17 SEG0~SEG31 O LCD segment outputs LCD power input Absolute Maximum Ratings Supply Voltage…………...…..… -0.3V ~ 5.5V Input Voltage… … … V SS - 0.3V ~ VDD + 0.3V Storage Temperature… … … … … -50°C ~ 125°C Operating Temperature… … … … . . -25°C ~ 75°C Note: These are stress ratings only. Stresses exceeding the range specified under “Absolute Maximum Ratings”may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. p. 4 Last update: 2004-03-05 12:13 ESC1621 D.C. Characteristics Symbol Test Conditions Parameter VDD Operating Voltage IDD1 Operating Current IDD2 Operating Current IDD3 Operating Current ISTB Standby Current VIL Input Low Voltage VIH Input High Voltage IOL1 DATA, BZ, BZ, IRQ IOH1 DATA, BZ, BZ Min. Typ. Max. Unit 2.4 — 5.2 V — 220 300 µA 5V No load/LCD ON On-chip RC oscillator — 450 600 µA 3V 5V No load/LCD ON Crystal oscillator — — 90 180 120 240 µA µA 3V — 150 200 µA 5V No load/LCD ON External clock source — 300 400 µA 3V 5V No load Power down mode — — 0.1 0.3 5 10 µA µA 0 — 0.6 V 0 — 1.0 V VDD Conditions — — 3V 3V 5V IOL2 LCD Common Sink Current IOH2 LCD Common Source Current IOL3 LCD Segment Sink Current IOH3 LCD Segment Source Current RPH Pull-high Resistor DATA, WR, CS, RD 3V 5V DATA, WR, CS, RD 2.4 4.0 — — 3.0 5.0 V V 3V VOL =0.3V 0.5 1.2 — mA 5V 3V VOL =0.5V VOH =2.7V 1.3 -0.4 2.6 -0.8 — — mA mA 5V VOH =4.5 V -0.9 -1.8 — mA 3V VOL =0.3V 80 150 — µA 5V 3V VOL =0.5V VOH =2.7V 150 -80 250 -120 — — µA µA 5V VOH =4.5 V -120 -200 — µA 3V VOL =0.3V 60 120 — µA 5V 3V VOL =0.5V VOH =2.7V 120 -40 200 -70 — — µA µA 5V VOH =4.5 V -70 -100 — µA 40 80 150 kO 30 60 100 kO 3V 5V DATA, WR, CS, RD p. 5 Last update: 2004-03-05 12:13 ESC1621 A.C. Characteristics Sym. Test Conditions Parameter Min. Typ. Max. Unit — 256 — kHz — 256 — kHz — 32.768 — kHz — 32.768 — kHz — 256 — kHz — 256 — kHz On-chip RC oscillator — FSYS1 /1024 — Hz Crystal oscillator — FSYS2 /128 — Hz External clock source — FSYS3 /1024 — Hz n: Number of COM — n/fLCD — s — 150 kHz — 300 kHz — 75 kHz — 150 kHz VDD fSYS1 System Clock 3V Conditions On-chip RC oscillator 5V fSYS2 System Clock 3V Crystal oscillator 5V fSYS3 System Clock 3V External clock source 5V fLCD LCD Clock — tCOM LCD Common Period fCLK1 Serial Data Clock ( WR Pin) 3V Duty cycle 50% 5V fCLK2 Serial Data Clock ( RD Pin) 3V Duty cycle 50% 5V fTONE Tone Frequency tCS Serial Interface Reset Pulse Width (Figure 3) 3V WR, RD Input Pulse Width (Figure 1) 5V tr, tf tsu th tsu1 th1 — 2.0 or 4.0 — kHz CS — 250 — ns Write mode 3.34 — — Read mode 6.67 — — Write mode 1.67 — — Read mode 3.34 — — — — 120 — ns — — 120 — ns — — 120 — ns — — 100 — ns — — 100 — ns 5V 3V tCLK On-chip RC oscillator Rise/Fall Time Serial Data Clock Width (Figure 1) 3V Setup Time for DATA to WR, RD Clock Width (Figure 2) 3V Hold Time for DATA to WR, RD Clock Width (Figure 2) 3V Setup Time for CS to WR, RD Clock Width (Figure 3) 3V Hold Time for CS to WR, RD Clock Width (Figure 3) 3V µs µs 5V 5V 5V 5V 5V p. 6 Last update: 2004-03-05 12:13 ESC1621 Application Circuits Host controller with a ESC1621 display system CS * VDD RD * WR µC DATA VLCD ESC1621 * R BZ Piezo IRQ BZ OSCI Clock Out VR OSCO COM0~ COM3 SEG0 ~ SEG31 External Clock 1 External Clock 2 On-chip OSC 1/2 or 1/3 Bias; 1/2, 1/3 or 1/4 Duty LCD PANEL Crystal 32768Hz Note: The connection of IRQ and RD pin can be selected depending on the requirement of the µC. The voltage applied to VLCD pin must be lower than VDD. Adjust VR to fit LCD display, at VDD=5V, VLCD=4V, VR=15kO+20% Adjust R (external pull- high resistance) to fit user’s time base clock. p. 7 Last update: 2004-03-05 12:13