SCAS172 − D3680, JANUARY 1991 − REVISED APRIL 1993 • • • • • • DL PACKAGE (TOP VIEW) Member of the Texas Instruments Widebus Family Packaged in Plastic 300-mil Shrink Small-Outline Package Using 25-mil Center-to-Center Pin Spacings Flow-Through Architecture Optimizes PCB Layout Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise EPIC (Enhanced-Performance Implanted CMOS) 1-µm Process 500-mA Typical Latch-Up Immunity at 125°C 1OEAB 1B1 1B2 GND 1B3 1B4 VCC 1B5 1B6 GND 1B7 1B8 2B1 2B2 GND 2B3 2B4 VCC 2B5 2B6 GND 2B7 2B8 2OEAB description The 74AC16623 is a 16-bit transceiver designed for asynchronous communication between data buses. The control function implementation allows for maximum flexibility in timing. This device can be used as two 8-bit transceivers or one 16-bit transceiver. It allows data transmission from the A bus to the B bus or from the B bus to the A bus, depending upon the logic level at the output-enable (OEBA and OEAB) inputs. The output-enable inputs can be used to disable the device so that the buses are effectively isolated. 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 32 18 31 19 30 20 29 21 28 22 27 23 26 24 25 1OEBA 1A1 1A2 GND 1A3 1A4 VCC 1A5 1A6 GND 1A7 1A8 2A1 2A2 GND 2A3 2A4 VCC 2A5 2A6 GND 2A7 2A8 2OEBA The dual-enable configuration gives the bus transceiver the capability to store data by simultaneous enabling of OEBA and OEAB. Each output reinforces its input in this transceiver configuration. Thus, when both control inputs are enabled and all other data sources to the two sets of bus lines are at high impedance, the bus lines will remain at their last states. The 74AC16623 is packaged in TI’s shrink small-outline package (DL), which provides twice the I/O pin count and functionality of standard small-outline packages in the same printed-circuit-board area. The 74AC16623 is characterized for operation from − 40°C to 85°C. FUNCTION TABLE (each 8-bit section) INPUTS OEBA OPERATION OEAB L L B data to A bus H H A data to B bus H L Isolation L H B data to A bus, A data to B bus EPIC and Widebus are trademarks of Texas Instruments Incorporated. Copyright 1993, Texas Instruments Incorporated !" # $%&" !# '%()$!" *!"&+ *%$"# $ " #'&$$!"# '& ",& "&# &-!# #"%&"# #"!*!* .!!"/+ *%$" '$&##0 *&# " &$&##!)/ $)%*& "&#"0 !)) '!!&"&#+ • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77001 • 3−1 SCAS172 − D3680, JANUARY 1991 − REVISED APRIL 1993 logic symbol† 48 1OEBA 1OEAB 1 25 2OEBA 2OEAB 1A1 24 47 logic diagram (positive logic) EN1 1OEBA EN2 1OEAB EN3 1A1 EN4 1 1 1A2 1A3 1A4 1A5 1A6 1A7 1A8 2A1 3 44 5 43 6 41 8 40 9 38 11 37 12 36 3 2A3 2A4 2A5 2A6 2A7 2A8 1 47 2 1B1 1B1 2 46 13 1 1 2A2 2 1 48 1B2 1B3 To Seven Other Channels 1B4 1B5 1B6 2OEBA 1B7 2OEAB 1B8 2A1 2B1 25 24 36 4 35 14 33 16 32 17 30 19 29 20 27 22 26 23 13 2B2 2B1 2B3 2B4 2B5 To Seven Other Channels 2B6 2B7 2B8 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡ Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 400 mA Maximum power package dissipation at TA = 55°C (in still air) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.85 W Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C ‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 3−2 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77001 • SCAS172 − D3680, JANUARY 1991 − REVISED APRIL 1993 recommended operating conditions (see Note 2) VCC Supply voltage VIH High-level input voltage VCC = 3 V VCC = 4.5 V NOM MAX 3 5 5.5 0.9 0 Output voltage 0 IOH High-level output current VCC VCC VCC = 3 V VCC = 4.5 V Low-level output current V 1.65 Input voltage ∆t /∆v V 1.35 VI VO IOL V 3.85 VCC = 4.5 V VCC = 5.5 V Low-level input voltage UNIT 2.1 3.15 VCC = 5.5 V VCC = 3 V VIL MIN V V −4 −24 VCC = 5.5 V VCC = 3 V −24 VCC = 4.5 V VCC = 5.5 V 24 mA 12 mA 24 Input transition rise or fall rate TA Operating free-air temperature NOTE 2: Unused or floating pins (input or I/O) must be held high or low. 0 10 ns/ V −40 85 °C electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) TA = 25°C PARAMETER TEST CONDITIONS IOH = − 50 µA IOH = − 4 mA VOH MIN 3V 2.9 2.9 4.5 V 4.4 4.4 5.5 V 5.4 5.4 3V 2.58 2.48 3.8 TYP MAX MIN MAX 4.5 V 3.94 5.5 V 4.94 IOH = − 75 mA† 5.5 V 3V 0.1 0.1 IOL = 50 µA 4.5 V 0.1 0.1 5.5 V 0.1 0.1 IOL = 24 mA II Control inputs IOL = 75 mA† VI = VCC or GND IOZ‡ A or B ports VO = VCC or GND ICC Ci Control inputs VI = VCC or GND, VI = VCC or GND IO = 0 4.8 3.85 3V 0.36 0.44 4.5 V 0.36 0.44 5.5 V 0.36 0.44 5.5 V ± 0.1 ±1 µA 5.5 V ± 0.5 ±5 µA 8 80 µA 5V 1.65 4.5 Cio A or B ports VO = VCC or GND 5V 16 † Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms. ‡ For I/O ports, the parameter IOZ includes the input leakage current. • V 5.5 V 5.5 V POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77001 • UNIT V IOL = − 24 mA IOL = 12 mA VOL VCC pF pF 3−3 SCAS172 − D3680, JANUARY 1991 − REVISED APRIL 1993 switching characteristics over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) tPLH tPHL A or B B or A tPZH tPZL OEBA A tPHZ tPLZ OEBA A tPZH tPZL OEAB B tPHZ tPLZ OEAB B MIN TA = 25°C TYP MAX MIN MAX 2.7 8.1 10 2.7 11.2 3.1 9.3 11.4 3.1 12.5 2.7 8.3 10.3 2.7 11.5 3.5 11.8 14.2 3.5 15.6 4.8 7.7 9.3 4.8 9.9 4.1 7.5 9.2 4.1 9.8 2.8 8.1 9.9 2.8 11.1 3.8 10.7 14.1 3.8 15.1 4.7 7.5 9.1 4.7 9.5 4.3 7.3 8.9 4.3 9.3 UNIT ns ns ns ns ns switching characteristics over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) tPLH tPHL A or B B or A tPZH tPZL OEBA A tPHZ tPLZ OEBA A tPZH tPZL OEAB B tPHZ tPLZ OEAB B MIN TA = 25°C TYP MAX MIN MAX 2.3 5.1 6.9 2.3 7.7 2.6 6 7.8 2.6 8.6 2.1 5.3 6.8 2.1 7.6 2.8 6.9 8.5 2.8 9.4 4.7 6.9 8.4 4.7 8.9 4 6.3 7.7 4 8.2 2.3 5.2 6.7 2.3 7.5 3 6.7 8.4 3 9.3 4.5 6.9 8.4 4.5 8.9 4 6.2 7.6 4 7.9 UNIT ns ns ns ns ns operating characteristics, VCC = 5 V, TA = 25°C PARAMETER Cpd 3−4 Power dissipation capacitance per transceiver TEST CONDITIONS Outputs enabled Outputs disabled • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77001 • CL = 50 pF, f = 1 MHz TYP 47 8 UNIT pF SCAS172 − D3680, JANUARY 1991 − REVISED APRIL 1993 PARAMETER MEASUREMENT INFORMATION 2 × VCC S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) Output Control (low-level enabling) VCC 50% 50% 50% 0V tPHL Output Waveform 2 S1 at GND (see Note C) VOH 50% VCC VCC 0V tPZL tPLZ Output Waveform 1 S1 at 2 × VCC (see Note C) 50% tPLH Output S1 Open 2 × VCC GND 500 Ω LOAD CIRCUIT Input (see Note B) TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH 50% VCC VOL 50% VCC 20% VCC VOL tPHZ tPZH VOLTAGE WAVEFORMS [ VCC 50% VCC 80% VCC VOH [0V VOLTAGE WAVEFORMS NOTES: A. CL includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns. C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. D. The outputs are measured one at a time with one input transition per measurement. Figure 1. Load Circuit and Voltage Waveforms • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77001 • 3−5 SCAS172 − D3680, JANUARY 1991 − REVISED APRIL 1993 3−6 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77001 • IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. 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