SCAS240A − JULY 1990 − REVISED APRIL 1996
D Members of the Texas Instruments
D
D
D
D
D
54AC16640 . . . WD PACKAGE
74AC16640 . . . DL PACKAGE
(TOP VIEW)
Widebus Family
Flow-Through Architecture Optimizes
PCB Layout
Distributed VCC and GND Pin Configuration
Minimizes High-Speed Switching Noise
EPIC (Enhanced-Performance Implanted
CMOS) 1-µm Process
500-mA Typical Latch-Up Immunity at
125°C
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) Packages Using
25-mil Center-to-Center Pin Spacings and
380-mil Fine-Pitch Ceramic Flat (WD)
Packages Using 25-mil Center-to-Center
Pin Spacings
1DIR
1B1
1B2
GND
1B3
1B4
VCC
1B5
1B6
GND
1B7
1B8
2B1
2B2
GND
2B3
2B4
VCC
2B5
2B6
GND
2B7
2B8
2DIR
description
The ’AC16640 are inverting 16-bit transceivers
designed for asynchronous communication
between data buses.
These devices can be used as two 8-bit
transceivers or one 16-bit transceiver. They allow
data transmission from the A bus to the B bus or
from the B bus to the A bus, depending on the logic
level at the direction-control (1DIR and 2DIR)
inputs. The output-enable (1OE and 2OE) inputs
can be used to disable the device so that the
buses are effectively isolated.
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17
32
18
31
19
30
20
29
21
28
22
27
23
26
24
25
1OE
1A1
1A2
GND
1A3
1A4
VCC
1A5
1A6
GND
1A7
1A8
2A1
2A2
GND
2A3
2A4
VCC
2A5
2A6
GND
2A7
2A8
2OE
The 74AC16640 is packaged in TI’s shrink small-outline package, which provides twice the I/O pin count and
functionality of standard small-outline packages in the same printed-circuit-board area.
The 54AC16640 is characterized for operation over the full military temperature range of −55°C to 125°C. The
74AC16640 is characterized for operation from −40°C to 85°C.
FUNCTION TABLE
(each section)
INPUTS
OPERATION
OE
DIR
L
L
B data to A bus
L
H
A data to B bus
H
X
Isolation
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
Copyright 1996, Texas Instruments Incorporated
!"#$%& "!&'& &(!)$'!& "#))%& ' !( *#+,"'!& '%- )!#" "!&(!)$ !
*%"("'!& *%) % %)$ !( %.' &)#$%& '&') /'))'&0)!#"!& *)!"%&1 !% &! &%"%'),0 &",#% %&1 !( ',,
*')'$%%)-
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1
SCAS240A − JULY 1990 − REVISED APRIL 1996
logic symbol†
1OE
1DIR
48
1
25
2OE
2DIR
1A1
24
G3
3 EN1 [BA]
3 EN2 [AB]
G6
6 EN4 [BA]
6 EN5 [AB]
47
1
1A2
1A3
1A4
1A5
1A6
1A7
1A8
2A1
3
44
5
43
6
41
8
40
9
38
11
37
12
36
13
4
2A3
2A4
2A5
2A6
2A7
2A8
1B1
2
46
1
1
2A2
2
1
1
1B2
1B3
1B4
1B5
1B6
1B7
1B8
2B1
5
35
14
33
16
32
17
30
19
29
20
27
22
26
23
2B2
2B3
2B4
2B5
2B6
2B7
2B8
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
1OE
1DIR
1A1
48
2OE
1
2DIR
47
2
1B1
2A1
24
36
13
To Seven Other Channels
To Seven Other Channels
2
25
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2B1
SCAS240A − JULY 1990 − REVISED APRIL 1996
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±400 mA
Maximum power dissipation at TA = 55°C (in still air)(see Note 2): DL package . . . . . . . . . . . . . . . . . . . . 1.2 W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
recommended operating conditions (see Note 3)
54AC16640
VCC
VIH
Supply voltage
VCC = 3 V
VCC = 4.5 V
High-level input voltage
VCC = 5.5 V
VCC = 3 V
VIL
VI
VO
IOH
IOL
∆t/∆v
MIN
NOM
MAX
3
5
5.5
MAX
3
5
5.5
3.15
3.15
3.85
3.85
0
Output voltage
0
VCC = 3 V
VCC = 4.5 V
Low-level output current
NOM
2.1
Input voltage
High-level output current
MIN
2.1
VCC = 4.5 V
VCC = 5.5 V
Low-level input voltage
74AC16640
0.9
1.35
1.35
1.65
1.65
0
0
VCC
VCC
−4
−4
−24
−24
VCC = 5.5 V
VCC = 3 V
−24
−24
12
12
VCC = 4.5 V
VCC = 5.5 V
24
24
24
24
Input transition rise or fall rate
TA
Operating free-air temperature
NOTE 3: Unused inputs must be held high or low to prevent them from floating.
V
V
0.9
VCC
VCC
UNIT
V
V
V
mA
mA
0
10
0
10
ns/V
−55
125
−40
85
°C
&(!)$'!& "!&"%)& *)!#" & % (!)$'2% !)
%1& *'% !( %2%,!*$%&- ')'"%)" '' '& !%)
*%"("'!& ')% %1& 1!',- %.' &)#$%& )%%)2% % )1 !
"'&1% !) "!&&#% %% *)!#" /!# &!"%-
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3
SCAS240A − JULY 1990 − REVISED APRIL 1996
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
IOH = −50 µA
54AC16640
MIN
74AC16640
MAX
MIN
3V
2.9
2.9
2.9
4.4
4.4
4.4
5.5 V
5.4
5.4
5.4
3V
2.58
2.48
2.48
4.5 V
3.94
3.8
3.8
IOH = −24 mA
5.5 V
4.94
4.8
4.8
IOH = −75 mA†
5.5 V
IOL = 50 µA
IOL = 24 mA
3.85
MAX
UNIT
V
3.85
3V
0.1
0.1
0.1
4.5 V
0.1
0.1
0.1
5.5 V
0.1
0.1
0.1
3V
0.36
0.44
0.44
4.5 V
0.36
0.44
0.44
5.5 V
0.36
0.44
0.44
1.65
1.65
IOL = 12 mA
VOL
TA = 25°C
TYP
MAX
4.5 V
IOH = −4 mA
VOH
MIN
V
IOL = 75 mA†
VI = VCC or GND
5.5 V
5.5 V
±0.1
±1
±1
µA
A or B ports
5.5 V
±0.5
±5
±5
µA
ICC
Ci
VO = VCC or GND
VI = VCC or GND,
8
80
80
µA
Control inputs
Cio
A or B ports
VI = VCC or GND
VO = VCC or GND
II
IOZ‡
Control inputs
IO = 0
5.5 V
5V
4.5
pF
5V
16
pF
† Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
‡ For I/O ports, the parameter IOZ includes the input leakage current.
switching characteristics over recommended operating free-air temperature range,
VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tPLH
tPHL
A or B
B or A
tPZH
tPZL
OE
A or B
tPHZ
tPLZ
OE
A or B
TA = 25°C
MIN
TYP
MAX
54AC16640
MIN
74AC16640
MAX
MIN
MAX
2.2
6.9
9.1
2.2
10
2.2
10
3
8.5
11
3
11.9
3
11.9
3
8.2
11
3
12.3
3
12.3
3.9
10.9
14
3.9
15.5
3.9
15.5
5.1
8.3
10.6
5.1
11.2
5.1
11.2
4.3
7.8
10.1
4.3
10.6
4.3
10.6
UNIT
ns
ns
ns
switching characteristics over recommended operating free-air temperature range,
VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tPLH
tPHL
A or B
B or A
tPZH
tPZL
OE
A or B
tPHZ
tPLZ
OE
A or B
MIN
TA = 25°C
TYP
MAX
•
MAX
MIN
MAX
4.7
1.8
7.3
1.8
7.3
2.6
5.7
2.6
8.6
2.6
8.6
2.4
5.6
2.4
8
2.4
8
3
6.6
3
9.9
3
9.9
5
7.5
5
9.9
5
9.9
4.1
6.5
4.1
9
4.1
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74AC16640
MIN
1.8
&(!)$'!& "!&"%)& *)!#" & % (!)$'2% !)
%1& *'% !( %2%,!*$%&- ')'"%)" '' '& !%)
*%"("'!& ')% %1& 1!',- %.' &)#$%& )%%)2% % )1 !
"'&1% !) "!&&#% %% *)!#" /!# &!"%-
4
54AC16640
UNIT
ns
ns
ns
SCAS240A − JULY 1990 − REVISED APRIL 1996
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER
Cpd
TEST CONDITIONS
Outputs enabled
Power dissipation capacitance per transceiver
Outputs disabled
CL = 50 pF,
TYP
f = 1 MHz
55
8
UNIT
pF
PARAMETER MEASUREMENT INFORMATION
2 × VCC
500 Ω
From Output
Under Test
S1
Open
GND
CL = 50 pF
(see Note A)
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
500 Ω
LOAD CIRCUIT
Output
Control
(low-level
enabling)
VCC
Input
50%
50%
0V
tPHL
tPLH
In-Phase
Output
50% VCC
Out-of-Phase
Output
50% VCC
0V
tPZL
tPLZ
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
VOH
50% VCC
VOL
tPLH
tPHL
VCC
Output
Waveform 2
S1 at GND
(see Note B)
VOH
50% VCC
VOL
50%
50%
50% VCC
VOL
tPHZ
tPZH
VOLTAGE WAVEFORMS
[ VCC
20% VCC
50% VCC
80% VCC
VOH
[0V
VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveform
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5
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