SCAS267A − MARCH 1993 − REVISED MAY 1995 D Member of the Texas Instruments D D D D D DGG OR DL PACKAGE (TOP VIEW) Widebus Family EPIC (Enhanced-Performance Implanted CMOS) Submicron Process ESD Protection Exceeds 2000 V Per MIL-STD-883C, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 250 mA Per JEDEC Standard JESD-17 Bus Hold On Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors Package Options Include Plastic 300-mil Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages OE Q1 Q2 GND Q3 Q4 VCC Q5 Q6 Q7 GND Q8 Q9 Q10 Q11 Q12 Q13 GND Q14 Q15 Q16 VCC Q17 Q18 GND Q19 Q20 NC description This 20-bit flip-flop is designed specifically for low-voltage (3.3-V) VCC operation; it is tested at 2.5-V, 2.7-V, and 3.3-V VCC. The SN74ALVC16721’s 20 flip-flops are edgetriggered D-type flip-flops with qualified clock storage. On the positive transition of the clock (CLK) input, the device provides true data at the Q outputs if the clock-enable (CLKEN) input is low. If CLKEN is high, no data is stored. 1 56 2 55 3 54 4 53 5 52 6 51 7 50 8 49 9 48 10 47 11 46 12 45 13 44 14 43 15 42 16 41 17 40 18 39 19 38 20 37 21 36 22 35 23 34 24 33 25 32 26 31 27 CLK D1 D2 GND D3 D4 VCC D5 D6 D7 GND D8 D9 D10 D11 D12 D13 GND D14 D15 D16 VCC D17 D18 GND D19 D20 CLKEN 30 A buffered output-enable (OE) input places the 28 29 20 outputs in either a normal logic state (high or low level) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. OE does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. Active bus-hold circuitry holds unused or floating data inputs at a valid logic level. The SN74ALVC16721 is available in TI’s shrink small-outline (DL) and thin shrink small-outline (DGG) packages, which provide twice the I/O pin count and functionality of standard small-outline packages in the same printed-circuit-board area. The SN74ALVC16721 is characterized for operation from − 40°C to 85°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC and Widebus are trademarks of Texas Instruments Incorporated. Copyright 1995, Texas Instruments Incorporated !"#$ % &'!!($ #% )'*+&#$ ,#$( !,'&$% &!" $ %)(&&#$% )(! $-( $(!"% (.#% %$!'"($% %$#,#!, /#!!#$0 !,'&$ )!&(%%1 ,(% $ (&(%%#!+0 &+',( $(%$1 #++ )#!#"($(!% • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 1 SCAS267A − MARCH 1993 − REVISED MAY 1995 FUNCTION TABLE (each flip-flop) INPUTS OE CLKEN CLK D OUTPUT Q L H X X Q0 L L ↑ H H L L ↑ L L L L L or H X Q0 H X X X Z logic diagram (positive logic) OE CLK CLKEN 1 56 29 CE C1 D1 55 1D 2 Q1 To 19 Other Channels absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 100 mA Maximum power dissipation at TA = 55°C (in still air) (see Note 3): DGG package . . . . . . . . . . . . . . . . . . 1 W DL package . . . . . . . . . . . . . . . . . . 1.4 W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This value is limited to 4.6 V maximum. 3. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils. For more information, refer to the Package Thermal Considerations application note in the 1994 ABT Advanced BiCMOS Technology Data Book, literature number SCBD002B. 2 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • SCAS267A − MARCH 1993 − REVISED MAY 1995 recommended operating conditions (see Note 4) VCC Supply voltage VIH High-level input voltage VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VIL Low-level input voltage VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VI VO Input voltage IOH IOL ∆t /∆v MIN MAX 2.3 3.6 Low-level output current 0.7 0.8 −12 VCC = 3 V VCC = 2.3 V −24 VCC = 2.7 V VCC = 3 V 12 TA Operating free-air temperature NOTE 4: Unused or floating control pins must be held high or low. • VCC VCC VCC = 2.3 V VCC = 2.7 V Input transition rise or fall rate POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • V 2 0 High-level output current V 1.7 0 Output voltage UNIT −12 V V V mA 12 mA 24 0 10 ns / V −40 85 °C 3 SCAS267A − MARCH 1993 − REVISED MAY 1995 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER IOH = − 100 µA IOH = − 6 mA, VOH MIN to MAX IOH = − 12 mA, IOH = − 12 mA, IOH = − 12 mA, IOH = − 24 mA, IOL = 100 µA IOL = 6 mA, VOL II II(hold) IOZ‡ ICC nICC Ci Cio VCC† TEST CONDITIONS IOL = 12 mA, IOL = 12 mA, IOL = 24 mA, VI = VCC or GND TA = − 40°C to 85°C MIN TYP MAX VIH = 1.7 V VIH = 1.7 V 2.3 V VCC −0.2 2 2.3 V 1.7 VIH = 2 V VIH = 2 V 2.7 V 2.2 3V 2.4 VIH = 2 V 3V 2 MIN to MAX 0.2 2.3 V 0.4 2.3 V 0.7 VIL = 0.8 V VIL = 0.8 V 2.7 V 0.4 3V 0.55 ±5 3.6 V 2.3 V VI = 0.8 V VI = 2 V 3V V µA 45 −45 µA 75 VI = 0 to 3.6 V VO = VCC or GND VI = VCC or GND, VCC = 3 V to 3.6 V, Other inputs at VCC or GND IO = 0 One input at VCC − 0.6 V, VI = VCC or GND VO = VCC or GND • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • −75 3.6 V ± 500 3.6 V ±10 µA 3.6 V 40 µA 750 µA 3.3 V 3.5 pF 3.3 V 7 pF † For conditions shown as MIN or MAX, use the appropriate values under recommended operating conditions. ‡ For I/O ports, the parameter IOZ includes the input-leakage current. 4 V VIL = 0.7 V VIL = 0.7 V VI = 0.7 V VI = 1.7 V UNIT SCAS267A − MARCH 1993 − REVISED MAY 1995 timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figures 1 and 2) VCC = 3.3 V ± 0.15 V fclock tw Clock frequency Pulse duration, CLK high or low tsu Setup time th Hold time VCC = 3.3 V ± 0.3 V VCC = 2.7 V MIN MAX MIN MAX MIN MAX 0 150 0 150 0 150 3.3 3.3 3.3 Data before CLK↑ High or low 4 3.6 3.1 CLKEN before CLK↑ High or low 3.4 3.1 2.7 Data after CLK↑ High or low 0 0 0 CLKEN after CLK↑ High or low 0 0 0 UNIT MHz ns ns ns switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figures 1 and 2) VCC = 2.5 V ± 0.2 V VCC = 2.7 V VCC = 3.3 V ± 0.3 V FROM (INPUT) TO (OUTPUT) fmax tpd CLK Q 1 7 1 5.7 1 4.9 ns ten OE Q 1 7.4 1 6.5 1 5.4 ns tdis OE Q 1 6.2 1 5.1 1 4.8 ns PARAMETER MIN MAX 150 MIN MAX 150 MIN UNIT MAX 150 MHz operating characteristics, TA = 25°C PARAMETER Cpd Power dissipation capacitance TEST CONDITIONS Outputs enabled Outputs disabled CL = 50 pF, • f = 10 MHz POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • VCC = 2.5 V ± 0.2 V VCC = 3.3 V ± 0.3 V TYP TYP 55 59 46 49 UNIT pF 5 SCAS267A − MARCH 1993 − REVISED MAY 1995 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V " 0.2 V 4.6 V S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 4.6 V GND tw LOAD CIRCUIT 2.3 V Input 2.3 V Timing Input VOLTAGE WAVEFORMS PULSE DURATION th 2.3 V Data Input 1.2 V 1.2 V 0V tPHL Output Waveform 2 S1 at GND (see Note B) VOH 1.2 V 1.2 V VOL 1.2 V 0V tPLZ 2.3 V Output Waveform 1 S1 at 4.6 V (see Note B) 1.2 V tPLH 1.2 V tPZL 2.3 V 1.2 V 2.3 V Output Control (low-level enabling) 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Output 1.2 V 0V 0V tsu Input 1.2 V 1.2 V 1.2 V tPZH VOL + 0.3 V VOL tPHZ 1.2 V VOH − 0.3 V VOH 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR v 10 MHz, ZO = 50 Ω, tr v 2.5 ns, tf v 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms 6 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • SCAS267A − MARCH 1993 − REVISED MAY 1995 PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V " 0.3 V 6V S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND tw LOAD CIRCUIT 2.7 V Input 2.7 V Timing Input VOLTAGE WAVEFORMS PULSE DURATION th 2.7 V Data Input 1.5 V 1.5 V 0V tPHL Output Waveform 2 S1 at GND (see Note B) VOH 1.5 V 1.5 V VOL 1.5 V 0V tPLZ 3V Output Waveform 1 S1 at 6 V (see Note B) 1.5 V tPLH 1.5 V tPZL 2.7 V 1.5 V 2.7 V Output Control (low-level enabling) 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Output 1.5 V 0V 0V tsu Input 1.5 V 1.5 V 1.5 V tPZH VOL + 0.3 V VOL tPHZ 1.5 V VOH − 0.3 V VOH 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR v 10 MHz, ZO = 50 Ω, tr v 2.5 ns, tf v 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 2. Load Circuit and Voltage Waveforms • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 7 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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