ACX301AKM
5.1cm (2.0 Type) NTSC/PAL Color LCD Panel (Module with Backlight)
Description
The ACX301AKM is an LCD panel module with
back light developed exclusively for the ACX301AK
5.1cm diagonal active matrix TFT-LCD panel
addressed by low temperature polycrystalline silicon
transistors with built-in peripheral driving circuitry.
This module provides full-color representation for
NTSC and PAL systems. In addition, RGB dots are
arranged in a delta pattern that provides smooth
picture quality without fixed color patterns compared
to vertical stripe and mosaic patterns.
Features
• Number of active dots: 200,000, 5.1cm (2.0 Type) in diagonal
• Horizontal resolution: 440 TV lines
• Center luminance:
250cd/m2 (typ.)
• High contrast ratio with normally white mode: 200 (typ.)
• Built-in H and V driving circuitry (built-in input level conversion circuit, 3V drive possible)
• Low voltage, low power consumption: 12V drive: 50mW (panel block, typ.)
0.48W (CCFL∗ power consumption, typ.)
∗ Cold cathode fluorecene lamp
• Smooth pictures with a RGB delta arrangement
• Supports NTSC/PAL
• Built-in picture quality improvement circuit
• Up/down and/or right/left inverse display function
• 16:9 screen display function
• LR (low reflectance) surface treatment provides an easy-to-see display even outdoors
• Dirt-resistant surface treatment
• Thin package using a dedicated backlight (5.8mm thick)
• High color reproductivity using a backlight optimum for LCD panels
Element Structure
• Active matrix TFT-LCD panel with built-in peripheral driving circuitry using low temperature polycrystalline
silicon transistors
• Edge-light type backlight using cold cathode tubes
• Number of pixels
Total number of dots:
896 (H) × 230 (V) = 206,080
Number of active dots:
880 (H) × 228 (V) = 200,640
• Module dimensions
Package dimensions:
50.5 (W) × 45.6 (D) × 5.8 (H) (mm)
Effective display dimensions: 40.5 (H) × 30.6 (V) (mm)
Applications
LCD monitors, etc.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E99633A01-PS
ACX301AKM
Module Configuration
This module is comprised of a 2.0 Type 200,000dot color TFT-LCD panel (ACX301AK) combined
with an integrated type dedicated backlight as
shown in the figure on the right.
Backlight block
harness
Integrated type
dedicated backlight
LCD panel
ACX301AK
1Pinマークに流用
Block Diagram
The panel block diagram is shown below.
COM
LC
V Shift Register
CS
H Shift Register
H, V Level
Shifter
Common
Voltage
VCK
EN
DWN
VVDD
VSS
HVDD
VSSG
TEST2
18
19 20
21
22
23 24
TESTR
VST
17
RGT
COM
–2–
16
BLUE
11 12 13 14 15
RED
10
GREEN
9
PSIG
8
HCK1
7
HCK2
6
Cext/Rext
5
TEST
4
REF
3
HST
2
WIDE
1
TESTL
Negative Voltage
Generation Circuit
ACX301AKM
Absolute Maximum Ratings (Vss = 0V)
• H driver supply voltage
HVDD, Cext/Rext
• V driver supply voltage
VVDD
• V driver negative supply voltage VSSG
• Common voltage of panel
COM
• H driver input pin voltage
HST, HCK1, HCK2, RGT, WIDE
• V driver input pin voltage
VST, VCK, EN, DWN, REF
• Video signal, uniformity improvement signal input pin voltage
GREEN, RED, BLUE, PSIG
• Operating temperature
Topr
• Storage temperature
Tstg
• Storage humidity
Hstg
• CCFL voltage
Vcfl
• CCFL current
Icfl
–1.0 to +17
–1.0 to +15
–3.0 to +1.0
–1.0 to +17
–1.0 to +17
–1.0 to +15
V
V
V
V
V
V
–1.0 to +13
V
–10 to +60
°C
–30 to +85
°C
40°C 95%
RH
2.0
kVp-p
4
mArms
Operating Conditions of Panel Block
1. Input/output supply voltage conditions∗1
Item
(VSS = 0V)
Min.
Typ.
Max.
Unit
HVDD
11.4
12.0
14.0
V
VVDD
11.4
12.0
14.0
V
Cext/Rext∗2 HVDD – 3.4
12.0
—
V
VSSG output voltage setting∗3
VSSG
–2.3
–1.8
–1.5
V
Resistor connected to Cext/Rext pin∗2
Rext
—
10
160
kΩ
Symbol
Supply voltage
∗1 The HVDD/VVDD typical voltage setting is noted as 12.0V in these specifications.
∗2 Connect the resistor and capacitor to the Cext/Rext pin as shown in the figure below.
∗3 For the VSSG output setting, connect an external smoothing capacitor and a voltage stabilizing Zener diode
as shown in the figure below.
Cext/Rext constant setting condition
ACX301AKM
HVDD
HVDD
Voltage
HVDD
VSSG
Cext/Rext
Rext
1µF
HVDD – Cext/Rext
7
text
Cext/Rext
Cext
Time
Set a Cext and a Rext value that
satisfies text > 1ms for the period
HVDD – Cext/Rext > 7V.
–3–
VSS
Use a Zener
voltage of 2.7V.
(RD2.7UM is
recommended)
ACX301AKM
(VSS = 0V)
2. Panel input signal voltage conditions
Item
H/V driver input voltage
Symbol
Min.
Typ.
Max.
Unit
(Low)
VIL
–0.3
0.0
0.3
V
(High)
VIH
2.6
3.0
5.5
V
VIH/2 – 0.3
VIH/2
VIH/2 + 0.3
V
REF input voltage
VREF
Video signal center voltage
VVC
5.3
5.5
5.7
V
Video signal input range
Vsig
1.0
VVC ± 4.0
VVDD – 2.0
(however, 10V or less)
V
Uniformity improvement signal
Vpsig
VVC ± 2.3
VVC ± 2.5
VVC ± 2.7
V
16:9 display top/bottom black signal∗4
VpsigBK
VVC ± 4.0
VVC ± 4.5
V
VVC – 0.4
VVC – 0.25
V
VVC – 0.55
Common voltage of panel (Ta = 25°C) Vcom
∗4 Input video and uniformity improvement signals should be symmetrical to VVC.
The input conditions for the uniformity improvement signal Vpsig differ for 4:3 display and 16:9 display.
1) During 4:3 display, input the voltage amplitude symmetrical to VVC as shown in Fig. 1.
2) During 16:9 display, input the same signal amplitude as in 1) above during the effective display portion,
and input the black signal level VpsigBK during the top/bottom black input portion as shown in Fig. 2.
During 4:3 display
PSIG waveform
Vpsig
VVC
Fig. 1
During 16:9 display
PSIG waveform
Vpsig
VVC
VpsigBK
VVC ± 4.0V
VVC ± 2.5V
Top/bottom black display portion
(letterbox portion)
Effective display portion
Fig. 2
Operating Conditions of Backlight Block
Input supply voltage conditions
Item
Symbol
Min.
Typ.
Max.
Unit
Lighting start voltage (Ta = –10°C)
Vstart
—
—
640
Vrms
Driving frequency
Fcfl
50
—
100
kHz
CCFL voltage (Ta = 25°C)
VLcfl
180
200
220
Vrms
CCFL current (Ta = 25°C)
ILcfl
1.0
2.4
4.0
mArms
Wire harness applied voltage
Vlmax
—
—
2.0
kVp-p
–4–
ACX301AKM
Pin Description of Panel Block
Pin
No.
Symbol
Panel test output; no connection
13
HST
Start pulse input for H shift register
drive
COM
Common voltage input of panel
14
REF
Level shifter circuit REF voltage
input
3
VST
Start pulse input for V shift register
drive
15
TEST
Panel test output; no connection
4
VCK
Clock input for V shift register drive
16
Cext/
Rext
Time constant power supply input
for H shift register drive
5
EN
Gate selection pulse enable input
17
HCK2
Clock input for H shift register drive
6
DWN
V shift register drive direction signal
input
18
HCK1
Clock input for H shift register drive
7
VVDD
Power supply input for V driver
19
PSIG
Uniformity improvement signal input
8
VSS
H and V driver GND
20
GREEN Video signal (G) input to panel
9
HVDD
Power supply input for H driver
21
RED
Video signal (R) input to panel
10
VSSG
Negative power supply setting for
V driver
22
BLUE
Video signal (B) input to panel
11
TEST2
No connection inside the panel.
(with 1MΩ terminating resistor)
23
RGT
H shift register drive direction signal
input
12
WIDE
Pulse input for 16:9 mode
24
TESTR
Panel test output; no connection
Description
Pin
No.
Symbol
CCFL high voltage side connection
4
Pin
No.
Symbol
1
TESTL
2
Description
Description
Pin Description of Backlight Block
Pin
No.
1
Symbol
CH
–5–
CL
Description
CCFL low voltage side connection
ACX301AKM
Input Equivalent Circuits of Panel Block
To prevent static charges, protective diodes are provided for each pin except the power supplies. In addition,
protective resistors are added to all pins except the video signal input pins. All pins are connected to VSS with a
high resistance of 1MΩ (typ.). The equivalent circuit of each input pin is shown below: (Resistor value: typ.)
(1) RED, GREEN, BLUE, PSIG
HVDD
Input
1MΩ
Signal line
(2) HCK1, HCK2
HVDD
HVDD
H level shifter and
shift register circuit
HCK1
1MΩ
HCK2
1MΩ
(3) HST, WIDE, REF
HVDD
HVDD
350Ω
350Ω
Level conversion
circuit
Input
1MΩ
REF
1MΩ
(4) RGT, REF
HVDD
HVDD
2kΩ
2kΩ
Level conversion
circuit
Input
1MΩ
REF
1MΩ
(5) VST, VCK, EN, REF
VVDD
VVDD
800Ω
800Ω
Level conversion
circuit
Input
1MΩ
REF
1MΩ
–6–
ACX301AKM
(6) DWN, REF
VVDD
VVDD
2kΩ
2kΩ
Level conversion
circuit
Input
1MΩ
REF
1MΩ
(7) VSSG
HVDD
Negative voltage
generation circuit
VSSG
(8) COM
Input
LC
1MΩ
(9) Cext/Rext
HVDD
H driver
Cext/Rext
1MΩ
(10) TEST/TEST2
HVDD
350Ω
350Ω
TEST
TEST2
1MΩ
1MΩ
(11) TESTL, TESTR
VVDD
1.5MΩ
TESTL
TESTR
–7–
ACX301AKM
Clock Timing Conditions of Panel Block
(VIH = 3.0V, HVDD = VVDD = 12V, Ta = 25°C)
Symbol
Item
Min.
Typ.
Max.
HST rise time
trHst
—
—
30
HST fall time
tfHst
—
—
30
HST data setup time
tdHst
137
167
197
HST data hold time
HCKn∗5 rise time
thHst
–30
0
30
trHckn
—
—
30
HCKn∗5 fall time
tfHckn
—
—
30
HCK1 fall to HCK2 rise time
to1Hck
–15
0
15
HCK1 rise to HCK2 fall time
to2Hck
–15
0
15
VST rise time
trVst
—
—
100
VST fall time
tfVst
—
—
100
VST data setup time
tdVst
30
32
34
VST data hold time
thVst
–30
–32
–34
VCK rise time
trVckn
—
—
100
VCK fall time
tfVckn
—
—
100
EN rise time
trEn
—
—
100
EN fall time
tfEn
—
—
100
EN fall to VCK rise/fall time
tdEn
2400
2500
2600
EN pulse width
twEn
5400
5500
5600
WIDE rise time
trWide
—
—
100
WIDE fall time
tfWide
—
—
100
WIDE (H) rise to VCK rise/fall time
tdhWide
0.9
1.1
1.3
WIDE WIDE (H) pulse width
twhWide
2.8
3.0
3.3
WIDE (V) pulse width
twvWide
1928
1933
1938
WIDE (V) fall to EN rise time
tov1Wide
25
32
—
EN rise to WIDE (V) fall time
tov2Wide
25
32
—
HST
HCK
VST
VCK
EN
∗5 HCKn means HCK1 and HCK2. (fHCKn = 3.0MHz)
–8–
Unit
ns
µs
ns
µs
ACX301AKM
Horizontal Standard Timing
5.0µs
HST
Hck1
Hck2
1.3µs
FRP
Vck
2.5µs
3µs
EN
WIDE 1∗7
(CXA3268AR)
1.1µs
1.9µs
WIDE 2
(CXA3268R)
WIDE signal has two timing of CXA3268R and CXA3268AR,
and panel characteristics guarantee both timing.
–9–
ACX301AKM
<Horizontal Shift Register Driving Waveforms>
Item
HST rise time
Symbol
Waveform
trHst
90%
HST
HST
HST fall time
tfHst
HST data setup time
tdHst
Conditions
90%
10%
10%
trHst
tfHst
∗6
HST 50%
50%
HST data hold time
thHst
thHst
tdHst
HCKn∗5 rise time
trHckn
∗5
90%
HCKn
HCKn∗5 fall time
• HCKn∗5 duty cycle
50%
to1Hck = 0ns
to2Hck = 0ns
tdHst = 167ns
thHst = 0ns
90%
10%
tfHckn
HCK
HCK1 fall to HCK2 rise
time
• HCKn∗5 duty cycle
50%
to1Hck = 0ns
to2Hck = 0ns
50% 50%
HCK1
10%
trHckn
tfHckn
∗6
to1Hck
HCK1
50%
50%
50%
• tdHst = 167ns
thHst = 0ns
50%
HCK2
HCK1 rise to HCK2 fall
time
to2Hck
WIDE rise time
trWide
to2Hck
to1Hck
90%
90%
WIDE
10%
∗7
WIDE
• HCKn∗5 duty cycle
50%
to1Hck = 0ns
to2Hck = 0ns
WIDE fall time
tfWide
WIDE rise to Vck rise/
fall time
tdhWide
trWide
tfWide
∗6
VCK
WIDE
WIDE pulse width
10%
twhWide
50%
50%
50%
twhWide
tdhWide
∗6 Definitions:
The right-pointing arrow (
) means +.
The left-pointing arrow (
) means –.
The black dot at an arrow (
) indicates the start of measurement.
∗7 WIDE represents every 1H pulse as shown in the Horizontal Timing.
– 10 –
ACX301AKM
Vertical Standard Timing
NTSC 4:3 (in case of EVEN field)
VST
Vck
FRP
HST
EN
WIDE
NTSC WIDE (in case of EVEN field)
VST
Vck
FRP
HST
EN
∗8
WIDE
– 11 –
ACX301AKM
<Vertical Shift Register Driving Waveforms>
Item
VST rise time
Symbol
Waveform
trVst
90%
Conditions
90%
VST
10%
VST fall time
tfVst
10%
trVst
tfVst
∗6
VST
VST data setup time
tdVst
VST
50%
50%
50%
50%
VCK
VST data hold time
VCK rise time
thVst
trVck
VCK
VCK
VCK fall time
tfVck
EN rise time
trEn
tdVst
thVst
90%
90%
10%
10%
trVck
tfVck
• VCK duty cycle
50%
to1Vck = 0ns
to2Vck = 0ns
90%
90%
10%
EN fall time
tfEn
10%
EN fall to VCK rise/fall
time
tdEn
EN pulse width
twEn
trEn
tfEn
∗6
VCK
50%
50%
EN
tdEn
WIDE rise time
trWide
50%
twEn
90%
90%
WIDE
10%
∗8
WIDE
WIDE fall time
tfWide
WIDE pulse width
twvWide
10%
trWide
WIDE
tfWide
50%
50%
twvWide
∗6
WIDE fall to EN rise time
tov1Wide
EN
EN fall to WIDE fall time
50%
WIDE
50%
tov2Wide
50%
tov1Wide
tov2Wide
∗8 WIDE represents 1F cycle as shown in the Vertical Timing.
– 12 –
• VCK duty cycle
50%
to1Vck = 0ns
to2Vck = 0ns
• VCK duty cycle
50%
to1Vck = 0ns
to2Vck = 0ns
tdVst = 32µs
thVst = –32µs
EN
EN
• VCK duty cycle
50%
to1Vck = 0ns
to2Vck = 0ns
ACX301AKM
Electrical Characteristics of Panel Block (Ta = 25°C, HVDD = 12.0V, VVDD = 12.0V, VIH = 3.0V, VREF = 1.5V)
1. Horizontal drivers
Item
Symbol
Min.
Typ.
Max.
Unit
HCKn input pin capacitance
CHckn
—
50
85
pF
HST input pin capacitance
CHst
—
15
40
pF
Video signal input pin capacitance
Csig
—
170
210
pF
Psig input pin capacitance (4:3 display)
Cpsig
—
11
15
nF
Psig input pin capacitance (16:9 display) Cpsig
—
22
34
nF
Input pin current
Conditions
HCK1
I Hck1
–900
–300
—
µA
HCK1: actual driving
HCK2
I Hck2
–900
–300
—
µA
HCK2: actual driving
HST
I Hst
–300
–100
—
µA
HST = GND
RGT
I RGT
–150
–50
—
µA
RGT = GND
REF
I REF
–1200
–300
—
µA
REF = VIH/2
Current consumption (Ta = 25°C)
I H25
—
3.3
4.0
mA
(Ta = 60°C)
I H60
—
—
5.0
mA
Min.
Typ.
Max.
Unit
HCKn: HCK1, HCK2 (3.0MHz)
2. Vertical drivers
Item
Symbol
Conditions
VCK input pin capacitance
CVck
—
15
20
pF
VST input pin capacitance
CVst
—
15
20
pF
Input pin current
VCK
I Vck
–150
–50
—
µA
VCK = GND
VST
I Vst
–150
–50
—
µA
VST = GND
EN
I En
–150
–50
—
µA
EN = GND
DWN
I DWN
–150
–50
—
µA
DWN = GND
WIDE
I WIDE
–150
–50
—
µA
WIDE = GND
Current consumption (Ta = 25°C)
I V25
—
0.7
1.0
mA
(Ta = 60°C)
I V60
—
—
1.3
mA
Symbol
Min.
Typ.
Max.
Unit
Total power consumption of the panel
(NTSC)
(Ta = 25°C)
PWR25
—
48
60
mW
(Ta = 60°C)
PWR60
—
—
75
mW
Symbol
Min.
Typ.
Max.
Unit
Pin – VSS input resistance 1
Rin1
0.5
1
—
MΩ
Test pin – VVDD input resistance 2
Rin2
0.75
1.5
—
MΩ
3. Total power consumption of the panel
Item
4. Pin input resistance
Item
– 13 –
ACX301AKM
Electro-optical Characteristics of Module/Panel Block
Item
Symbol
Contrast ratio
CR25
Panel transmittance∗1
T
Center luminance
Lm
Center color temperature
Tcm
(Ta = 25°C, NTSC mode)
Measurement
method
Min.
Typ.
Max.
Unit
1
100
200
—
—
5.2
5.6
—
%
200
250
—
cd/m2
5700
6600
—
K
—
0.31
0.33
2
2
X
Rx
Y
Ry
—
0.34
0.36
X
Rx
0.61
0.63
0.65
Y
Ry
0.32
0.34
0.36
X
Gx
0.26
0.28
0.30
Y
Gy
0.59
0.61
0.63
X
Bx
0.13
0.15
0.17
Y
By
0.09
0.11
0.13
25°C
V90-25
1.3
1.5
1.7
60°C
V90-60
1.3
1.5
1.7
25°C
V50-25
1.7
1.9
2.1
60°C
V50-60
1.7
1.9
2.1
25°C
V10-25
2.2
2.4
2.6
60°C
V10-60
2.2
2.4
2.6
R–G
V50RG
–0.11
–0.08
–0.05
B–G
V50BG
0
0.03
0.05
0°C
ton0
—
48
60
25°C
ton25
—
17
25
0°C
toff0
—
120
180
25°C
toff25
—
30
75
Flicker∗1
60°C
F
7
—
–60
–30
dB
Image retention time∗1
60°C
YT1
8
—
—
10
s
CR ≥ 10
θT
θB
θL
θR
9
19
50
35
35
25
70
42
42
—
Degree
(°)
θ = 0°
Rf
10
—
0.8
1.5
%
25°C
CTK
11
—
0.7
1.5
%
Center chromaticity
R
G
Chromaticity
B
V90
V-T
characteristics∗1
V50
V10
Half tone color reproduction
range∗1
ON time
Response
time∗1
OFF time
Viewing angle range
Surface reflection ratio
Cross talk∗1
3
4
5
6
∗1 Conforms to the measurement results for the discrete panel.
– 14 –
CIE
standards
V
V
ms
ACX301AKM
Electro-optical Characteristics of Backlight Block
Measurement
method
Min.
Typ.
Max.
Unit
Lcbl
12
3740
4400
—
cd/m2
Tcbl
12
7100
8400
10700
K
xbl
12
0.275
0.290
0.305
ybl
12
0.289
0.304
Backlight luminance uniformity∗2
BLunif
13
60
65
—
%
Backlight life∗2
BLlife
14
10000
—
—
hr
Tbl25
15
—
—
3
s
–10°C Tbl-5
15
—
—
3
s
Item
Symbol
Backlight center luminance∗2
Backlight color temperature∗2
Backlight chromaticity∗2
Lighting time after dark storage∗2
(lighting performance after dark storage for
70 hours or more)
25°C
∗2 Conforms to the measurement results for the discrete backlight.
– 15 –
CIE
0.319 standards
ACX301AKM
<Panel/Module/Backlight Electro-optical Characteristics Measurement>
Basic measurement conditions
(1) Driving voltage
HVDD = 12.0V, VVDD = 12.0V, VIH = 3.0V, VREF = 1.5V
VVC = 5.5V, VCOM = 5.1V, Vpsig = 5.5 ± 2.5V
(2) Measurement temperature
25°C unless otherwise specified.
(3) Measurement point
One point in the center of the screen unless otherwise specified.
(4) Measurement systems
Three types of measurement systems are used as shown below.
(5) R, G and B input signal voltage Vsig
Vsig = 5.5 ± VAC [V] (VAC: signal amplitude)
• Measurement system I
Surface A∗
Luminance
Meter
Using the TOPCON BM-5A luminance meter.
Backlight
LCD panel
Low voltage side
A
Using the Stanley 13585A inverter.
DC
13585A
2.4mA
• Measurement system II
Optical fiber
Light receptor lens
Light Detector
Measurement
Equipment
Surface A∗
Measure using the discrete LCD panel.
Drive Circuit
Light
Source
• Measurement system III
Light
Source
Optical fiber
Spectroscope
Surface A∗
∗ Surface A: See the Package Outline.
1. Contrast Ratio
Contrast ratio (CR) is given by the following formula.
CR = L (White)/L (Black)
L (White): Surface luminance of the TFT-LCD panel at the input signal amplitude VAC = 0.5V.
L (Black): Surface luminance of the panel at VAC = 4.0V.
Both luminosities are measured by System I.
– 16 –
ACX301AKM
2. Optical Transmittance of Panel Block, Module Center Luminance, Color Temperature
Optical transmittance (T) is given by the following formula.
T = L (White)/Luminance of Backlight × 100 [%]
L (White) is the same expression as defined in the "Contrast Ratio" section.
Optical transmittance is measured by System I using the TOPCON BM-5A.
Lm = White luminance at the center of the panel
Tcm = Color temperature at the center of the panel
3. Chromaticity
Chromaticity of the panels is measured by System I. Raster modes of each color are defined by the
representations at the input signal amplitude conditions shown in the table below. System I uses x and y of
the CIE standards as the chromaticity here.
Signal amplitudes (VAC) supplied to each input
Raster
R input
G input
B input
R
0.5
4.0
4.0
G
4.0
0.5
4.0
B
4.0
4.0
0.5
W
0.0
0.0
0.0
4. V-T Characteristics
V-T characteristics, or the relationship between signal
amplitude and the transmittance of the panel, are
measured by System II by inputting the same signal
amplitude VAC to each input pin. V90, V50, and V10
correspond to the voltages which define 90%, 50%,
and 10% of transmittance respectively.
Transmittance [%]
(Unit: V)
90
50
10
V90 V50 V10
VAC – Signal amplitude [V]
– 17 –
100
Transmittance [%]
5. Half Tone Color Reproduction Range
The half tone color reproduction range of LCD panels
is characterized by the differences between the V-T
characteristics of R, G and B. The differences of these
V-T characteristics are measured by System II.
System II defines signal voltages of each R, G and B
raster mode which correspond to 50% of transmittance,
V50R, V50G and V50B, respectively. V50RG and V50BG,
that is to say the differences between V50R and V50G
and between V50B and V50G, are given by the following
formulas respectively.
V50RG = V50R – V50G
V50BG = V50B – V50G
V50RG
V50BG
50
R raster
G raster
B raster
0
V50R V50B
V50G
VAC – Signal amplitude [V]
ACX301AKM
6. Response Time
Response times ton and toff are measured
by System II by applying the input signal
voltages in the figure to the right to each
input pin. These times are defined by the
following formulas.
ton = t1 – tON
toff = t2 – tOFF
t1: time which gives 10% transmittance
of the panel.
t2: time which gives 90% transmittance
of the panel.
Input signal voltage (Waveform applied to measured pixels)
4.0V
0.5V
5.5V
0V
Optical transmittance output
waveform
100%
90%
10%
0%
The relationships between t1, t2, tON and
tOFF are shown in the figure to the right.
tON
t1
ton
tOFF
t2
toff
7. Flicker
Flicker (F) is given by the following formula. DC and AC components (NTSC: 30Hz, rms; PAL: 25Hz, rms)
of the panel output signal for gray raster∗ mode are measured by a DC voltmeter and a spectrum analyzer
in System II.
F (dB) = 20 log {AC component/DC component}
∗ R, G, B input signal voltage for gray raster mode is given by Vsig = 5.5 ± V50 (V)
where: V50 is the signal amplitude which gives 50% of transmittance in V-T curve.
8. Image Retention Time
Image retention time is given by the following procedures.
Apply the monoscope pattern∗ to the LCD panel for 1 minute and then change to a gray scale signal
(Vsig = 5.5 ± VAC (V); VAC = 3 to 4V). Judging by sight at the VAC that holds the maximum image
retention, measure the time for the residual image to disappear.
∗ Monoscope pattern input conditions
Vsig = 5.5 ± 4.0 or 5.5 ± 2.0 [V]
(shown in the figure to the right)
Vcom = 5.1V
Black level
White level
4.0V
2.0V
5.5V
2.0V
4.0V
0V
Vsig waveform
– 18 –
ACX301AKM
9. Definition of Viewing Angle Range
Viewing angle range is measured by System Ι. The
contrast ratio (CR) is measured at the angles
defined in the figure to the right and the range where
CR ≥ 10 is taken as the viewing angle range.
Measure with surface A∗ facing upwards.
∗ Surface A: See the Package Outline.
Normal (θ = 0°)
θB
θT
θL
Left
θR
Top
Bottom
Right
Surface A
10. Surface Reflection Ratio
Surface reflection ratio (Rf) is given by the following formula.
Rf = Reflected optical luminance of the panel surface A∗/Reflected optical luminance of Al (wafer) × 100 [%]
The incident and reflected angles of light are both 0°.
Both luminosities are measured by System III.
∗ Surface A: See the Package Outline.
11. Cross Talk
Cross talk is determined by the luminance differences between adjacent areas represented by Wi' and Wi
(i = 1 to 4) around the black window (Vsig = 4.0V/1V).
Cross talk value CTK = | Wi' – Wi/Wi | × 100 [%]
W1 W1'
W2
W4
W2'
W4'
W3 W3'
– 19 –
ACX301AKM
12. Backlight Characteristic Measurement Conditions
1) Test inverter operating conditions (using a Stanley 13585A inverter)
Driving frequency: 58.4kHz
Input voltage: 6.1V
Input current: 0.105mA
Input power: 0.64W
Tube current: 2.4mA
Tube voltage: 200V
Tube power: 0.48W
2) Ambient temperature and humidity
Temperature: 25 ± 1°C
Humidity: 30 to 85%
(Start measurement after leaving the module in the above environment for one hour.)
Measurement should be performed in a dark room with a luminance of 10 lx or less and which is not
subject to the effects of reflective or external light.
There should be no heat insulating objects around the module unit, and measurement should be
performed in a draftless condition.
3) Luminance and chromaticity measurement
Measurement equipment: TOPCON BM-5A, viewing angle: 0.1°, distance: 500mm
Measure 10 minutes after the backlight is lit.
13. Backlight Uniformity Measurement Method
Start each measurement 10 minutes after the backlight is lit.
Luminance uniformity of the backlight is obtained by measuring the luminance at the 9 points shown below
and calculating Min. luminance ÷ Max. luminance × 100 [%].
10.1
10.1
13.1
13.1
×
1
×
2
×
3
×
4
×
5
×
6
×
7
×
8
×
9
14. Backlight Life Measurement Method
Definition or life: When the center luminance drops to 50% of the initial value during continuous lighting, or
when normal lighting becomes impossible.
Lighting conditions: 25 ± 5°C, CCFL current: 2.4mArms
15. Backlight Dark Lighting Characteristics Measurement Method
Shelf conditions: Leave for 70 hours or more in the dark at each temperature (25°C, –10°C) condition.
Lighting conditions: 0.5 lx or less at each temperature (25°C, –10°C) condition.
The used inverter should have a Vp-p or 1.81kVp-p or more.
Lighting time: Time from power-on until the backlight is lit.
– 20 –
ACX301AKM
Description of Panel Block Operation
1. Color Coding
The color filters are coded in a delta arrangement. The shaded area is used for the dark border around the
display.
Gate SW
Gate SW
Gate SW
Gate SW
Gate SW
1
Gate SW
G
B
R
B
G
R
G
B
R
B
B
R
G
B
R
G
B
R
G
B
R
G
B
R
G
B
R
G
G
B
G
B
R
B
R
R
B
R
G
G
B
Active area
R
G
B
R
G
B
R
G
B
R
G
B
R
G
B
R
G
B
R
G
R
G
B
R
228
R
G
G
B
R
B
G
B
G
R
B
R
8
G
R
B
R
G
B
R
G
B
R
G
B
R
G
B
R
G
B
R
G
B
R
R
B
G
B
G
R
G
880
896
– 21 –
B
R
G
B
R
G
B
R
G
B
R
G
B
R
G
B
R
G
B
R
G
B
R
G
8
R
G
B
R
1
R
230
R
ACX301AKM
2. Description of LCD Panel Operations
• A vertical driver, which consists of vertical shift registers, enable-gates and buffers, applies a selected pulse
to each of 228 line electrodes sequentially one line electrode at a time in a single horizontal scanning period.
• The selected pulse is output when the enable pin goes to high level. PAL signal pulse elimination display and
16:9 mode pulse elimination display are possible by using the enable pin and simultaneously controlling VCK.
• A horizontal driver, which consists of horizontal shift registers, gates and CMOS sample-and-hold circuitry,
applies selected pulses to each of 880 signal electrodes sequentially in a single horizontal scanning period.
These pulses are used to supply the sampled video signal to the row signal lines.
• The scanning direction of the horizontal shift registers can be switched with the RGT pin. The scanning
direction is left to right (right scan) for RGT pin at high level (2.6 to 5.5V), and right to left (left scan) for RGT
pin at low level (0V). In addition, the scanning direction of the vertical shift registers can be switched with the
DWN pin. The scanning direction is top to bottom for DWN pin at high level (2.6 to 5.5V), and bottom to top
for DWN pin at low level (0V). (These scanning directions are from a front view.)
• The vertical and horizontal drivers address one pixel, and then thin film transistors (TFTs; two TFTs for one
pixel) turn on to apply a video signal to the pixel. The same procedures lead to the entire 228 × 880 pixels to
display a picture in a single vertical scanning period.
• Pixel dots are arranged in a delta pattern, where sets of RGB pixels are positioned shifted by 1.5 dots against
adjacent horizontal lines. The horizontal driver output pulse must be shifted by 1.5 dots for each horizontal
line against the horizontal sync signal to apply a video signal to each pixel properly.
• The video signal should be input with the polarity-inverted every horizontal cycle.
• The relationships between the vertical shift register start pulse VST and the vertical display period, and
between the horizontal shift register start pulse HST and the horizontal display period are shown below for
top to bottom and left to right scan.
(1) Vertical display period (DWN: high level)
VD
VST
VCK
1
2
227
228
Vertical display period 228H (14.5ms)
(2) Vertical display period (DWN: low level)
VD
VST
1
VCK
2
227
228
Vertical display period 228H (14.5ms)
(3) Horizontal display period (RGT: high level)
BLK
HST
294
HCK1
1
2
3
293
295
Horizontal display period (48.9µs)
HCK2
– 22 –
ACX301AKM
3. RGB Simultaneous Sampling
The horizontal driver samples R, G and B video signal simultaneously, which requires phase matching
between the R, G and B signals to prevent the horizontal resolution from deteriorating. Thus phase matching
by an external signal delay circuit is needed before applying the video signal to the LCD panel.
Two methods are applied for the delaying procedure: Sample-and-hold and Delay circuit. These two block
diagrams are as follows.
The ACX301AK has a right/left inversion function. The following phase relationship diagram indicates the
phase setting for right scan (RGT = high level). For left scan (RGT = low level), the phase setting should be
inverted for the B and G signals.
B
S/H
S/H
CKB
CKG
R
S/H
S/H
CKR
CKG
G
S/H
AC Amp
22 BLUE
AC Amp
21 RED
AC Amp
20 GREEN
ACX301AK
(1) Sample-and-hold (right scan)
CKG
<Phase relationship of delaying sample-and-hold pulses> (right scan)
HCKn
CKB
CKR
CKG
B
R
Delay
Delay
AC Amp
22 BLUE
Delay
AC Amp
21 RED
AC Amp
20 GREEN
G
– 23 –
ACX301AK
(2) Delay element (right scan)
ACX301AKM
System Configuration
+12.0V
+12.0V
+3.0V
Rext∗1
PSIG
Buffer
Y/color difference
Cext/Rext
RED
Cext∗1
R/G/B
GREEN
BLUE
COM
HST
HCK1
CXA3268R
CXA3268AR
Serial data
HCK2
LCD Panel
ACX301AK
VST
VCK
DWN
EN
RGT
REF
Use a Zener diode
RD2.7UM is recommended.
WIDE
VSSG
1µF
Inverter
Dedicated backlight
ACX301AKM
(module with backlight)
∗1 See page 3 for the value setting.
∗2 When the CXA3268AR is used, insert buffer circuit to PSIG output.
– 24 –
ACX301AKM
Notes on Handling
(1) Static charge prevention
Be sure to take the following protective measures. TFT-LCD panels are easily damaged by static charges.
a) Use non-chargeable gloves, or simply use bare hands.
b) Use an earth-band when handling.
c) Do not touch any electrodes of a panel.
d) Wear non-chargeable clothes and conductive shoes.
e) Install grounded conductive mats on the working floor and working table.
f) Keep panels away from any charged materials.
g) Use ionized air to discharge the panels.
(2) Protection from dust and dirt
a) Operate in a clean environment.
b) When delivered, the panel surface (Polarizer) is covered by a protective sheet. Peel off the protective
sheet carefully so as not to damage the panel.
c) Do not touch the polarizer surface. The surface is easily scratched. When cleaning, use a clean-room
wiper with isopropyl alcohol. Be careful not to leave stains on the surface.
d) Use ionized air to blow dust off the panel.
(3) Module fixing method
a) The design reference edges are the upper and left edges as viewed from the front. (See the Package
Outline.)
b) Positioning in the x and y directions should be based on the panel frame or the panel window frame.
c) Do not set positioning guides inside the following ranges.
c-1: Within 2.3mm on both sides of the four panel frame corners
c-2: FPC outlet portion
c-3: Back light lamp socket portion
d) Set the backlight holder on the rear of the backlight outside of the effective area of the panel. In
particular, use a structure that does not apply pressure near the center of the rear of the backlight.
e) Connect the panel or backlight frame to GND. (static charge prevention)
f) High voltage is applied around the CCFL, so avoid locating metal objects within 1mm from the side of
the lamp socket (rubber) in order to prevent discharge. (See the figure below.)
Metal object prohibited area
(lamp socket side)
(High voltage side)
1.0
(4) Other handling precautions
a) Do not twist or bend the flexible PC board especially at the connecting region because the board is
easily deformed.
b) Do not fold or pull on the backlight harness.
c) Do not drop the panel.
d) Do not twist or bend the panel, panel frame or backlight.
e) Keep the panel and backlight away from heat sources.
f) Do not dampen the panel or backlight with water or other solvents.
g) Avoid storage or use the panel at high temperatures or high humidity, as this may result in damage
(faulty backlight lighting).
– 25 –
40±2
5
Electrode
75±2
Rear View
16
5
Note1. Tolerance with no indication± 0.2)
2. SONY logotype
3. Label is stuck here
4. Dimension of harness connection block rubber socket
15
8
7
Note3
10
14 Backlight frame
15 Connector(J.S.T. mfg.:ZHR-4)
16 Harness
CCFL
Reflection sheet
Light guide plate
Prism sheet
Deffusion sheet
18.63
2 Note4
9
10
11
12
13
(Backlight)
43.6 ±0.3
7.5
9.5
Shield case(front)
Shield case(rear)
Double coated abhesive tape
Reflector
Lamp socket
5.8 ±0.4
1.1
0.3 ±0.05
14
2.2
4.3 ±0.4
7
7
4
5
6
7
8
Mass: Approximately 20g
12.5 ±0.05
12.8±0.5
Center
(reference)
40.48 (Active area)
42.7 ±0.4 (Polarizer)
45.5 (Window)
24.9
Front view
Note2
2.15
49.8
50.5 ±0.3
2
1
(2.15)
30.55 (Active area)
1 FPC
2 Reinforcing board
3 Polarizer
18.93
(25.27)
(0.5)
Pin24
2.03
33.8 (Window)
Unit: mm
32.8 ±0.4(Polarizer)
30.5±0.5
– 26 –
(8.37)
Package Outline
13
12
11
3
4
9
6
3
5
Erectrode enlarged (back)
P : 0.5 ±0.02×23=11.5±0.03
0.35 ±0.03
0.5
Pin1
ACX301AKM
Sony corporation
44.2