Fractional-N Frequency Synthesizer ADF4154 Data Sheet FEATURES GENERAL DESCRIPTION RF bandwidth to 4 GHz 2.7 V to 3.3 V power supply Separate VP allows extended tuning voltage Programmable dual-modulus prescaler 4/5, 8/9 Programmable charge pump currents 3-wire serial interface Digital lock detect Power-down mode Pin compatible with the ADF4110/ADF4111/ ADF4112/ADF4113, ADF4106, ADF4153 Programmable modulus on fractional-N synthesizer Trade-off noise vs. spurious performance Fast-lock mode with built-in timer Loop filter design possible with ADIsimPLL™ The ADF4154 is a fractional-N frequency synthesizer that implements local oscillators in the up conversion and down conversion sections of wireless receivers and transmitters. It consists of a low noise digital phase frequency detector (PFD), a precision charge pump, and a programmable reference divider. There is a Σ-Δ based fractional interpolator to allow programmable fractional-N division. The INT, FRAC, and MOD registers define an overall N-divider (N = (INT + (FRAC/MOD))). In addition, the 4-bit reference counter (R-counter) allows selectable REFIN frequencies at the PFD input. A complete phase-locked loop (PLL) can be implemented if the synthesizer is used with an external loop filter and a voltage-controlled oscillator (VCO). A key feature of the ADF4154 is the fast-lock mode with a builtin timer. The user can program a predetermined countdown time value so that the PLL remains in wide bandwidth mode, instead of the user having to control this time externally. APPLICATIONS Base stations for mobile radio (WiMAX, PHS, GSM, PCS, DCS, CDMA, PMR, W-CDMA, supercell 3G) Wireless handsets (PMR, GSM, PCS, DCS, CDMA, WCDMA) CATV equipment Wireless LANs Communications test equipment Control of all on-chip registers is via a simple 3-wire interface. The device operates with a power supply ranging from 2.7 V to 3.3 V and can be powered down when not in use. FUNCTIONAL BLOCK DIAGRAM AVDD DVDD VP SDVDD RSET ADF4154 REFERENCE 4-BIT R COUNTER ×2 DOUBLER + PHASE FREQUENCY DETECTOR – CHARGE PUMP HIGH Z DGND LOCK DETECT MUXOUT OUTPUT MUX CURRENT SETTING FAST-LOCK SWITCH VDD RDIV RFCP3 RFCP2 RFCP1 NDIV N COUNTER DATA LE FRACTION REG 24-BIT DATA REGISTER AGND MODULUS REG DGND RFINA RFINB THIRD ORDER FRACTIONAL INTERPOLATOR CLOCK CP VDD INTEGER REG CPGND 04833-001 REFIN Figure 1. Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. 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ADF4154 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Register Definitions ................................................................... 16 Applications ....................................................................................... 1 R-Divider Register, R1 ............................................................... 16 General Description ......................................................................... 1 Control Register, R2 ................................................................... 16 Functional Block Diagram .............................................................. 1 Noise and Spur Register, R3 ...................................................... 17 Revision History ............................................................................... 2 Reserved Bits ............................................................................... 17 Specifications..................................................................................... 3 Initialization Sequence .............................................................. 18 Timing Characteristics ................................................................ 4 RF Synthesizer: A Worked Example ........................................ 18 Absolute Maximum Ratings............................................................ 5 Modulus ....................................................................................... 18 ESD Caution .................................................................................. 5 Reference Doubler and Reference Divider ............................. 18 Pin Configuration and Pin Function Descriptions ...................... 6 12-Bit Programmable Modulus ................................................ 18 Typical Performance Characteristics ............................................. 7 Spurious Optimization and Fast Lock ..................................... 18 Circuit Description ........................................................................... 9 Fast-Lock Timer and Register Sequences ............................... 19 Reference Input Section ............................................................... 9 Fast Lock: An Example .............................................................. 19 RF Input Stage ............................................................................... 9 Fast Lock: Loop Filter Topology ............................................... 19 RF INT Divider ............................................................................. 9 Spur Mechanisms ....................................................................... 19 INT, FRAC, MOD, and R Relationship ..................................... 9 Spur Consistency ........................................................................ 20 R-Counter ...................................................................................... 9 Filter Design—ADIsimPLL....................................................... 20 Phase Frequency Detector (PFD) and Charge Pump .............. 9 Interfacing ................................................................................... 20 MUXOUT and Lock Detect ...................................................... 10 PCB Design Guidelines for Chip Scale Package .................... 21 Input Shift Registers ................................................................... 10 Outline Dimensions ....................................................................... 22 Program Modes .......................................................................... 10 Ordering Guide .......................................................................... 22 Registers ........................................................................................... 11 REVISION HISTORY 8/12—Rev. B to Rev. C Changes to Figure 4 .......................................................................... 6 Updated Outline Dimensions (Changed CP-20-1 to CP-20-6) .... 22 Changes to Ordering Guide .......................................................... 22 9/11—Rev. A to Rev. B Changes to Noise Characteristics Parameter ................................ 3 Updated Outline Dimensions ....................................................... 22 Changes to Ordering Guide .......................................................... 22 12/06—Rev. 0 to Rev. A Changes to Features.......................................................................... 1 Changes to Applications .................................................................. 1 Changes to Functional Block Diagram .......................................... 1 Changes to Specifications ................................................................ 3 Changes to Absolute Maximum Ratings ....................................... 5 Changes to Typical Performance Characteristics Conditions .... 7 Replaced Figure 5 through Figure 7 ............................................... 7 Changes to Figure 13.........................................................................8 Changes to R-Divider Register Map ............................................ 13 Changes to Control Register Map ................................................ 14 Change to REFIN Doubler Section ................................................ 18 Added Initialization Sequence Section ........................................ 18 Change to 12-Bit Programmable Modulus Section ................... 18 Changes to Fast-Lock Timer and Register Sequences Section........ 19 Changes to Fast Lock: Loop Filter Topology Section ................ 19 Deleted Spurious Signal Section ................................................... 18 Added Spur Mechanisms Section ................................................ 19 Added Spur Consistency Section ................................................. 20 Change to Filter Design—ADIsimPLL Section .......................... 20 Change to Interfacing Section ...................................................... 20 Updated Outline Dimensions ....................................................... 22 Changes to Ordering Guide .......................................................... 22 5/04—Revision 0: Initial Version Rev. C | Page 2 of 24 Data Sheet ADF4154 SPECIFICATIONS AVDD = DVDD = SDVDD = 2.7 V to 3.3 V; VP = AVDD to 5.5 V; AGND = DGND = 0 V; TA = TMIN to TMAX, unless otherwise noted; dBm referred to 50 Ω. The operating temperature for the B version is −40°C to +80°C. Table 1. Parameter RF CHARACTERISTICS (3 V) RF Input Frequency (RFIN) 1 REFERENCE CHARACTERISTICS REFIN Input Frequency1 REFIN Input Sensitivity REFIN Input Capacitance REFIN Input Current PHASE DETECTOR Phase Detector Frequency 3 CHARGE PUMP ICP Sink/Source High Value Low Value Absolute Accuracy RSET Range ICP Three-State Leakage Current Matching ICP vs. VCP ICP vs. Temperature LOGIC INPUTS VINH, Input High Voltage VINL, Input Low Voltage IINH/IINL, Input Current CIN, Input Capacitance LOGIC OUTPUTS VOH, Output High Voltage VOL, Output Low Voltage POWER SUPPLIES AVDD DVDD, SDVDD VP IDD Low Power Sleep Mode NOISE CHARACTERISTICS Normalized Phase Noise Floor (PNSYNTH) 4 Normalized 1/f Noise (PN1_f) 5 Phase Noise Performance 6 1750 MHz Output 7 B Version Unit 0.5/4.0 1.0/4.0 GHz min/max GHz min/max 10/250 MHz min/max 0.7/AVDD 10 ±100 V p-p min/max pF max µA max 32 MHz max 5 312.5 2.5 2.7/10 1 2 2 2 mA typ µA typ % typ kΩ min/max nA typ % typ % typ % typ 1.4 0.6 ±1 10 V min V max µA max pF max 1.4 0.4 V min V max 2.7/3.3 AVDD AVDD/5.5 24 1 V min/V max V min/V max mA max µA typ −220 dBc/Hz typ −114 dBc/Hz typ −102 dBc/Hz typ Test Conditions/Comments See Figure 15 for the input circuit. −8 dBm/0 dBm min/max. For lower frequencies, ensure slew rate > 400 V/µs. −10 dBm/0 dBm min/max. See Figure 14 for input circuit. For f < 10 MHz, use a dc-coupled, CMOS-compatible square wave, slew rate > 25 V/µs. Biased at AVDD/2. 2 Programmable. See Table 5. With RSET = 5.1 kΩ. With RSET = 5.1 kΩ. Sink and source current. 0.5 V < VCP < VP − 0.5 V. 0.5 V < VCP < VP − 0.5 V. VCP = VP/2. Open-drain 1 kΩ pull-up to 1.8 V. IOL = 500 µA. 20 mA typical. PLL loop BW = 500 kHz. Measured at 100 kHz offset. 10 kHz offset; normalized to 1GHz. @ VCO output. @ 1 kHz offset, 26 MHz PFD frequency. Use a square wave for frequencies below fMIN. AC coupling ensures AVDD/2 bias. See Figure 14 for a typical circuit. Guaranteed by design. Sample tested to ensure compliance. 4 The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log(N) (where N is the N divider value) and 10 log(FPFD). PNSYNTH = PNTOT − 10 log(FPFD) − 20 log(N). 5 The PLL phase noise is composed of 1/f (flicker) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency, FRF, and at a frequency offset f is given by PN = PN1_f + 10 log(10 kHz/f) + 20 log(FRF/1 GHz). Both the normalized phase noise floor and flicker noise are modeled in ADIsimPLL. 6 The phase noise is measured with the EVAL-ADF4154EB1 and the HP8562E spectrum analyzer. 7 fREFIN = 26 MHz, fPFD = 26 MHz, offset frequency = 1 kHz, RFOUT = 1750 MHz, loop B/W = 20 kHz, lowest noise mode. 1 2 3 Rev. C | Page 3 of 24 ADF4154 Data Sheet TIMING CHARACTERISTICS AVDD = DVDD = SDVDD = 2.7 V to 3.3 V; VP = AVDD to 5.5 V; AGND = DGND = 0 V; TA = TMIN to TMAX, unless otherwise noted; dBm referred to 50 Ω. Table 2. Parameter 1 t1 t2 t3 t4 t5 t6 t7 Unit ns min ns min ns min ns min ns min ns min ns min Test Conditions/Comments LE setup time DATA to CLOCK setup time DATA to CLOCK hold time CLOCK high duration CLOCK low duration CLOCK to LE setup time LE pulse width Guaranteed by design, but not production tested. t4 t5 CLOCK t2 DATA DB23 (MSB) t3 DB22 DB2 DB1 (CONTROL BIT C2) DB0 (LSB) (CONTROL BIT C1) t7 LE t1 t6 04833-026 1 Limit at TMIN to TMAX (B Version) 20 10 10 25 25 10 20 LE Figure 2. Timing Diagram Rev. C | Page 4 of 24 Data Sheet ADF4154 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 3. Parameter 1, 2, 3 VDD to GND VDD to VDD VP to GND VP to VDD Digital I/O Voltage to GND Analog I/O Voltage to GND REFIN, RFIN to GND Operating Temperature Range Industrial (B Version) Storage Temperature Range Maximum Junction Temperature TSSOP θJA Thermal Impedance LFCSP θJA Thermal Impedance (Paddle Soldered) Reflow Soldering Peak Temperature Time at Peak Temperature Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rating −0.3 V to +4 V −0.3 V to +0.3 V −0.3 V to +5.8 V −0.3 V to +5.8 V −0.3 V to VDD + 0.3 V −0.3 V to VDD + 0.3 V −0.3 V to VDD + 0.3 V ESD CAUTION −40°C to +85°C −65°C to +150°C 150°C 112°C/W 30.4°C/W 260°C 40 sec This device is a high performance RF-integrated circuit with an ESD rating of <2 kV, and it is ESD sensitive. Proper precautions should be taken when handling and assembling the device. 2 GND = AGND = DGND = 0 V. 3 VDD = AVDD = DVDD = SDVDD. 1 Rev. C | Page 5 of 24 ADF4154 Data Sheet 16 DVDD 18 VP 17 DVDD 20 CP 19 RSET PIN CONFIGURATION AND PIN FUNCTION DESCRIPTIONS 15 MUXOUT CPGND 1 15 DVDD RFINB 4 14 MUXOUT RFINA 5 10 SDVDD 9 DGND 04833-002 AVDD 7 REFIN 8 12 CLK 11 SDVDD AVDD 6 13 LE TOP VIEW RFINB 5 (Not to Scale) 12 DATA 11 CLK RFINA 6 AGND 4 13 DATA DGND 10 ADF4154 REFIN 8 CPGND 3 TOP VIEW (Not to Scale) DGND 9 CP 2 14 LE AGND 3 NOTES 1. THE EXPOSED PAD MUST BE CONNECTED TO AGND. 04833-003 16 VP ADF4154 AVDD 7 RSET 1 AGND 2 Figure 4. LFCSP Pin Configuration Figure 3. TSSOP Pin Configuration Table 4. Pin Function Descriptions TSSOP 1 LFCSP 19 Mnemonic RSET Description Set Resistor. Connecting a resistor between this pin and ground sets the maximum charge pump output current. The relationship between ICP and RSET is I CPmax 2 20 CP 3 4 5 1 2, 3 4 CPGND AGND RFINB 6 7 5 6, 7 RFINA AVDD 8 8 REFIN 9 10 9, 10 11 DGND SDVDD 11 12 CLK 12 13 DATA 13 14 LE 14 15 MUXOUT 15 16, 17 DVDD 16 18 VP N/A EP EPAD 25.5 R SET where RSET = 5.1 kΩ and ICPmax = 5 mA. Charge Pump Output. When enabled, this pin provides ±ICP to the external loop filter, which in turn drives the external VCO. Charge Pump Ground. This is the ground return path for the charge pump. Analog Ground. This is the ground return path of the prescaler. Complementary Input to the RF Prescaler. This point should be decoupled to the ground plane with a small bypass capacitor, typically 100 pF (see Figure 15). Input to the RF Prescaler. This small-signal input is normally ac-coupled from the VCO. Positive Power Supply for the RF Section. Decoupling capacitors to the digital ground plane should be placed as close as possible to this pin. AVDD has a value of 3 V ± 10%. AVDD must have the same voltage as DVDD. Reference Input. This CMOS input has a nominal threshold of VDD/2 and an equivalent input resistance of 100 kΩ (see Figure 14). This input can be driven from a TTL or CMOS crystal oscillator, or it can be ac-coupled. Digital Ground. Σ-∆ Power. Decoupling capacitors to the digital ground plane should be placed as close as possible to this pin. SDVDD has a value of 3 V ± 10%. SDVDD must have the same voltage as DVDD. Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into the shift register on the CLK rising edge. This input is a high impedance CMOS input. Serial Data Input. The serial data is loaded MSB first with the two LSBs as the control bits. This input is a high impedance CMOS input. Load Enable, CMOS Input. When LE is high, the data stored in the shift registers is loaded into one of the four latches, which is selected by the user via the control bits. Multiplexer Output. This pin allows either the RF lock detect, the scaled RF, or the scaled reference frequency to be accessed externally. Positive Power Supply for the Digital Section. Decoupling capacitors to the digital ground plane should be placed as close as possible to this pin. DVDD has a value of 3 V ± 10%. DVDD must have the same voltage as AVDD. Charge Pump Power Supply. This should be greater than or equal to VDD. In systems where VDD is 3 V, it can be set to 5.5 V and used to drive a VCO with a tuning range of up to 5.5 V. Exposed Pad. The exposed pad must be connected to AGND. Rev. C | Page 6 of 24 Data Sheet ADF4154 TYPICAL PERFORMANCE CHARACTERISTICS Loop bandwidth = 20 kHz; reference = 250 MHz; VCO = Vari-L Company, Inc., VCO190-1750T; evaluation board = EVAL-ADF4154EB1; measurements taken with the Agilent E5500 phase noise measurement system. –130 –30 –50 PHASE NOISE (dBc/Hz) –60 PHASE NOISE (dBc/Hz) –40 20kHz LOOP BW, LOW NOISE MODE RF = 1.7202MHz, PFD = 25MHz, N = 68, FRAC = 101, MOD = 125, ICP = 625µA, DSB INTEGRATED PHASE ERROR = 0.23° rms SIRENZA 1750T VCO –70 –80 –90 –100 –110 –120 –130 –140 –150 –160 04833-004 –150 –160 –170 1k 10k 100k 1M FREQUENCY (Hz) 10M –170 100 100M 5 20kHz LOOP BW, LOW NOISE AND SPUR MODE RF = 1.7202MHz, PFD = 25MHz, N = 68, FRAC = 101, MOD = 125, ICP = 625µA, DSB INTEGRATED PHASE ERROR = 0.33° rms SIRENZA 1750T VCO 0 –5 –70 AMPLITUDE (dBm) PHASE NOISE (dBc/Hz) –60 100000 Figure 8. PFD Noise Floor vs. PFD Frequency (Lowest Noise Mode) –30 –50 10000 PHASE DETECTOR FREQUENCY (kHz) Figure 5. Single-Sideband Phase Noise Plot (Lowest Noise Mode) –40 1000 04833-010 –140 –80 –90 –100 –110 –120 –130 –10 P = 4/5 –15 –20 –25 –140 10k 100k 1M FREQUENCY (Hz) 10M –35 100M P = 8/9 0 0.5 1.0 3.0 3.5 4.0 4.5 6 20kHz LOOP BW, LOW SPUR MODE RF = 1.7202MHz, PFD = 25MHz, N = 68, FRAC = 101, MOD = 125, ICP = 625µA, DSB INTEGRATED PHASE ERROR = 0.36° rms SIRENZA 1750T VCO 5 4 3 –70 2 –80 1 ICP (mA) –90 –100 –110 0 –1 –120 –2 –130 –3 –140 –4 –160 –170 1k 10k 100k 1M FREQUENCY (Hz) 10M –5 –6 0 100M 1 2 3 4 VCP (V) Figure 10. Charge Pump Output Characteristics Figure 7. Single-Sideband Phase Noise Plot (Lowest Spur Mode) Rev. C | Page 7 of 24 5 04833-012 –150 04833-006 PHASE NOISE (dBc/Hz) –60 2.5 Figure 9. RF Input Sensitivity –30 –50 2.0 FREQUENCY (GHz) Figure 6. Single-Sideband Phase Noise Plot (Low Noise Mode and Spur Mode) –40 1.5 04833-011 –160 –170 1k –30 04833-005 –150 ADF4154 Data Sheet 1.700 –80 1.696 1.692 1.688 1.684 –90 FREQUENCY (GHz) –95 –100 1.680 LOCK TIME IN FAST-LOCK MODE (FAST COUNTER = 150) 1.676 1.672 1.668 LOCK TIME IN NORMAL MODE 1.664 1.660 1.656 1.652 –105 1.648 LOW SPUR MODE: 1649.7MHz TO 1686.8MHz FINAL LOOP BANDWIDTH = 60kHz –110 0 5 10 15 20 RSET VALUE (kΩ) 25 30 35 04833-013 1.644 –90 –94 –96 –98 –100 –102 –20 0 20 40 TEMPERATURE (°C) 60 80 100 04833-014 PHASE NOISE (dBc/Hz) –92 –40 0 10 20 30 40 50 60 TIME (µs) 70 80 Figure 13. Frequency vs. Lock Time Figure 11. Phase Noise vs. RSET –104 –60 1.640 Figure 12. Phase Noise vs. Temperature Rev. C | Page 8 of 24 90 100 110 04833-028 PHASE NOISE (dBc/Hz) –85 Data Sheet ADF4154 CIRCUIT DESCRIPTION REFERENCE INPUT SECTION INT, FRAC, MOD, AND R RELATIONSHIP The reference input stage is shown in Figure 14. While the device is operating, usually SW1 and SW2 are closed switches and SW3 is open. When a power-down is initiated, SW3 is closed and SW1 and SW2 are opened. This ensures that the REFIN pin is not loaded while the device is powered down. The INT, FRAC, and MOD values, in conjunction with the R-counter, enable generating output frequencies that are spaced by fractions of the PFD. See the RF Synthesizer: A Worked Example section for more information. The RF VCO frequency (RFOUT) equation is RFOUT = FPFD × (INT + (FRAC MOD )) POWER-DOWN CONTROL where RFOUT is the output frequency of the external voltagecontrolled oscillator (VCO). 100kΩ NC FPFD = REFIN × (1 + D ) R SW2 REFIN NC BUFFER TO R COUNTER 04833-027 SW1 SW3 NO Figure 14. Reference Input Stage RF INPUT STAGE The RF input stage is shown in Figure 15. It is followed by a two-stage limiting amplifier to generate the current mode logic (CML) clock levels needed for the prescaler. 1.6V BIAS GENERATOR AVDD 2kΩ (1) (2) where: REFIN is the reference input frequency. D is the REFIN doubler bit. R is the preset divide ratio of binary 4-bit programmable reference counter (1 to 15). INT is the preset divide ratio of binary 9-bit counter (31 to 511). MOD is the preset modulus ratio of binary 12-bit programmable FRAC counter (2 to 4095). FRAC is the preset fractional ratio of binary 12-bit programmable FRAC counter (0 to MOD-1). R-COUNTER 2kΩ The 4-bit R-counter allows the input reference frequency (REFIN) to be divided down to produce the reference clock to the PFD. Division ratios from 1 to 15 are allowed. RFINA PHASE FREQUENCY DETECTOR (PFD) AND CHARGE PUMP RFINB 04833-015 The PFD takes inputs from the R-counter and N-counter and produces an output proportional to the phase and frequency difference between them. Figure 17 is a simplified schematic. The PFD includes a fixed delay element that sets the width of the antibacklash pulse, which is typically 3 ns. This pulse ensures that there is no dead zone in the PFD transfer function and gives a consistent reference spur level. AGND Figure 15. RF Input Stage RF INT DIVIDER The RF INT CMOS counter allows a division ratio in the PLL feedback counter. Division ratios from 31 to 511 are allowed. RF N-DIVIDER D1 Q1 UP U1 +IN N = INT + FRAC/MOD FROM RF INPUT STAGE HI CLR1 TO PFD DELAY N COUNTER U3 CHARGE PUMP CP THIRD ORDER FRACTIONAL INTERPOLATOR HI FRAC VALUE CLR2 DOWN D2 Q2 U2 Figure 16. A and B Counters Rev. C | Page 9 of 24 –IN Figure 17. PFD Simplified Schematic 04833-017 MOD REG 04833-016 INT REG ADF4154 Data Sheet MUXOUT AND LOCK DETECT Data is transferred from the shift register to one of four latches on the rising edge of LE. The destination latch is determined by the state of the two control bits (C2 and C1) in the shift register. These are the two LSBs, DB1 and DB0, as shown in Figure 2. The truth table for these bits is shown in Table 5. Table 6 shows a summary of how the latches are programmed. The output multiplexer on the ADF4154 allows the user to access various internal points on the chip. The state of MUXOUT is controlled by M3, M2, and M1 (see Table 8). Figure 18 shows the MUXOUT section in block diagram form. The N-channel, open-drain, analog lock detect should be operated with an external pull-up resistor of 10 kΩ nominal. When lock has been detected, the lock detect is high with narrow low-going pulses. PROGRAM MODES Table 5 through Table 9 show how to set up the program modes in the ADF4154. DVDD LOGIC LOW ANALOG LOCK DETECT R-DIVIDER OUTPUT N-DIVIDER OUTPUT MUX MUXOUT CONTROL FAST-LOCK CONTROL THREE-STATE OUTPUT DIGITAL LOCK DETECT 04833-018 LOGIC HIGH DGND Figure 18. MUXOUT Schematic INPUT SHIFT REGISTERS The ADF4154 digital section includes a 4-bit R value, a 9-bit RF N value, a 12-bit RF FRAC value, and a 12-bit interpolator modulus value/fast-lock timer. Data is clocked MSB first into the 24-bit shift register on each rising edge of CLK. The ADF4154 programmable modulus is double buffered, meaning that two events must occur before the part can use a new modulus value. The first event is that the new modulus value must be latched into the device by writing to the R-divider register, and the second event is that a new write must be performed on the N-divider register. Therefore, whenever the modulus value is updated, the N-divider register must be written to so that the modulus value is loaded correctly. Table 5. C2 and C1 Truth Table Control Bits C2 C1 0 0 0 1 1 0 1 1 Rev. C | Page 10 of 24 Data Latch N-divider register R-divider register Control register Noise and spur register Data Sheet ADF4154 REGISTERS Table 6. Register Summary FAST-LOCK N-DIVIDER REG 9-BIT RF N VALUE DB23 DB22 FL1 N9 DB21 DB20 N8 N7 DB19 DB18 N6 N5 DB17 N4 CONTROL BITS 12-BIT RF FRAC VALUE DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 N2 F12 F11 F10 F9 F8 F7 N3 N1 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 F6 F5 F4 F3 F2 F1 C2 (0) C1 (0) R4 R3 R2 DB13 DB12 R1 M12 M11 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 M10 M8 M7 M6 M5 M4 M3 M2 M1 M9 DB1 DB0 C2 (0) C1 (1) RF CHARGE PUMP THREE-STATE RF COUNTER RESET CONTROL REG RESERVED CONTROL BITS DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 0 0 0 0 CP3 CP2 CP1 CP0 U5 U4 U3 U2 U1 U6 CHARGE PUMP CURRENT SETTING DB0 C2 (1) C1 (0) NOISE AND SPUR REG NOISE AND SPUR MODE RESERVED DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 T9 T8 T7 T6 T5 T4 T3 T2 T1 Rev. C | Page 11 of 24 CONTROL BITS DB1 C2 (1) DB0 C1 (1) 04833-019 P1 DB14 NOISE AND SPUR MODE P2 DB16 DB15 RF POWERDOWN M1 DB17 LOCK DETECT PRECISION M2 DB18 PHASE DETECTOR POLARITY M3 DB19 CP/2 P3 DB21 DB20 CONTROL BITS 12-BIT INTERPOLATOR MODULUS VALUE/ FAST-LOCK TIMER RESERVED DB22 4-BIT R VALUE REFIN DOUBLER DB23 PRESCALER MUXOUT RESERVED LOAD CONTROL R-DIVIDER REG ADF4154 Data Sheet FAST-LOCK Table 7. N-Divider Register Map 9-BIT RF N VALUE (INT) DB23 DB22 FL1 N9 N8 N9 0 0 0 0 . . . 1 1 1 N7 N8 0 0 0 0 . . . 1 1 1 DB19 DB18 N6 N7 0 0 0 0 . . . 1 1 1 N5 DB17 N4 N6 0 1 1 1 . . . 1 1 1 DB16 DB15 N3 N2 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 N1 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 C2 (0) C1 (0) F12 F11 0 0 0 0 . . . 1 1 1 1 0 0 0 0 . . . 1 1 1 1 N5 1 0 0 0 . . . 1 1 1 N4 1 0 0 0 . . . 1 1 1 F10 0 0 0 0 . . . 1 1 1 1 .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... F3 0 0 0 0 . . . 1 1 1 1 N3 1 0 0 0 . . . 1 1 1 N2 1 0 0 1 . . . 0 1 1 N1 1 0 1 0 . . . 1 0 1 FAST-LOCK NORMAL OPERATION FAST-LOCK ENABLED F2 0 0 1 1 . . . 0 0 1 1 F1 FRACTIONAL VALUE (FRAC) 0 1 0 1 . . . 0 1 0 1 0 1 2 3 . . . 4092 4093 4094 4095 INTEGER VALUE (INT) 31 32 33 34 . . . 509 510 511 04833-020 FL1 0 1 DB21 DB20 CONTROL BITS 12-BIT FRAC VALUE (FRAC) Rev. C | Page 12 of 24 Data Sheet ADF4154 DB23 DB22 DB21 DB20 P3 P3 0 1 M3 M2 LOAD CONTROL NORMAL OPERATION LOAD FAST LOCK TIMER DB19 DB18 M1 0 P1 0 1 P1 DB17 DB16 DB15 DB14 R4 R2 R3 R1 PRESCALER 4/5 8/9 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 M12 M11 M8 M7 M6 M5 M4 M3 M2 M1 M10 M9 .......... .......... .......... .......... .......... .......... .......... M1 0 1 0 . . . 0 INTERPOLATOR MODULUS VALUE (MOD) 2 3 4 . . . 4092 1 .......... 1 0 1 4093 1 .......... 1 1 0 4094 1 .......... 1 1 1 4095 M10 0 0 0 . . . 1 1 1 1 1 1 1 R2 R1 R VALUE DIVIDE RATIO 0 0 0 0 . . . 1 0 0 0 1 . . . 1 0 1 1 0 . . . 0 1 0 1 0 . . . 0 1 2 3 4 . . . 12 1 1 0 1 13 1 1 1 0 14 1 1 1 1 15 M2 M1 MUXOUT 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 THREE-STATE OUTPUT DIGITAL LOCK DETECT N DIVIDER OUTPUT LOGIC HIGH R DIVIDER OUTPUT ANALOG LOCK DETECT FASTLOCK SWITCH LOGIC LOW DB0 M2 1 1 0 . . . 0 M11 0 0 0 . . . 1 R3 0 0 0 0 1 1 1 1 DB1 C2 (0) C1 (1) M3 0 0 1 . . . 1 M12 0 0 0 . . . 1 R4 M3 CONTROL BITS 12-BIT INTERPOLATOR MODULUS VALUE (MOD)/ FAST-LOCK TIMER 4-BIT R VALUE 04833-021 MUXOUT PRESCALER RESERVED LOAD CONTROL Table 8. R-Divider Register Map Rev. C | Page 13 of 24 ADF4154 Data Sheet RF POWERDOWN RF CHARGE PUMP THREE-STATE RF COUNTER RESET DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 S4 S3 S2 S1 U6 CP3 CP2 CP1 CP0 U5 U4 U3 U2 U1 C2 (1) C1 (0) CHARGE PUMP CURRENT SETTING LOCK DETECT PRECISION CP/2 CONTROL BITS RESYNC PHASE DETECTOR POLARITY REFIN DOUBLER Table 9. Control Register Map REFIN DOUBLER DISABLED ENABLED U6 0 1 S4 S3 S2 S1 RESYNC 0 0 0 . . . 1 1 1 0 0 0 . . . 1 1 1 0 1 1 . . . 0 1 1 1 0 1 . . . 1 0 1 1 2 3 . . . 13 14 15 U2 0 1 U1 COUNTER RESET 0 1 DISABLED ENABLED RF CHARGE PUMP THREE-STATE DISABLED THREE-STATE U3 RF POWER-DOWN 0 1 NORMAL OPERATION POWER-DOWN ICP (mA) CP2 0 0 0 0 1 1 1 1 CP1 0 0 1 1 0 0 1 1 CP0 0 1 0 1 0 1 0 1 2.7kΩ 1.18 2.46 3.54 4.72 5.9 7.08 8.26 9.45 5.1kΩ 0.63 1.25 1.88 2.50 3.13 3.75 4.38 5.00 10kΩ 0.32 0.64 0.96 1.28 1.59 1.92 2.23 2.55 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0.59 1.23 1.77 2.36 2.95 3.54 4.13 4.73 0.31 0.63 0.94 1.25 1.57 1.88 2.19 2.50 0.16 0.32 0.48 0.64 0.8 0.96 1.12 1.28 U4 0 1 U5 0 1 Rev. C | Page 14 of 24 LOCK DETECT PRECISION 24 PFD CYCLES 40 PFD CYCLES PHASE DETECTOR POLARITY NEGATIVE POSITIVE 04833-022 CP3 0 0 0 0 0 0 0 0 Data Sheet ADF4154 NOISE AND SPUR MODE NOISE AND SPUR MODE RESERVED Table 10. Noise and Spur Register RESERVED CONTROL BITS DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 T9 T8 T7 T6 T5 T4 T3 T2 T1 C2 (1) C1 (1) DB10, DB5, DB4, DB3 0 RESERVED RESERVED DB9, DB8, DB7, DB6, DB2 00000 11100 11111 NOISE AND SPUR SETTING LOWEST SPUR MODE LOW NOISE AND SPUR MODE LOWEST NOISE MODE Rev. C | Page 15 of 24 04833-023 THESE BITS MUST BE SET TO 0 FOR NORMAL OPERATION. ADF4154 Data Sheet Prescaler (P/P + 1) REGISTER DEFINITIONS N-Divider Register, R0 The on-chip N-divider register is programmed by setting R0 [1, 0] to [0, 0]. Table 7 shows the input data format for programming this register. 9-Bit RF N Value (INT) These nine bits control what is loaded as the INT value. This is used to determine the overall feedback division factor (see Equation 1). The dual-modulus prescaler (P/P + 1), along with the INT, FRAC, and MOD counters, determines the overall division ratio from the RFIN to the PFD input. Operating at CML levels, the prescaler uses the clock from the RF input stage and divides it down for the counters. The prescaler is based on a synchronous 4/5 core. When it is set to 4/5, the maximum RF frequency allowed is 2 GHz. Therefore, when operating the ADF4154 with frequencies greater than 2 GHz, the prescaler must be set to 8/9. The prescaler limits the INT value as follows: With P = 4/5, NMIN = 31 With P = 8/9, NMIN = 91 12-Bit RF FRAC Value These 12 bits control what is loaded as the FRAC value into the fractional interpolator. This value helps determine the overall feedback division factor (see Equation 1). The FRAC value must be less than the value loaded into the MOD register. Fast Lock Setting the part to logic high enables fast-lock mode. To use fast lock, the required time value for wide bandwidth mode must be loaded into the R-divider register. The charge pump current increases from 16× the minimum current and reverts back to 1× the minimum current after the time value loaded expires. See the Fast-Lock Timer and Register Sequences section for more information. The prescaler can also influence the phase noise performance. If INT < 91, a prescaler of 4/5 should be used. For applications where INT > 91, a prescaler of 8/9 should be used for optimum noise performance (see Table 8). 4-Bit R Value The 4-bit R value allows the input reference frequency (REFIN) to be divided down to produce the reference clock for the PFD. Division ratios from 1 to 15 are allowed. 12-Bit Interpolator Modulus Value/Fast-Lock Timer Depending on the value of the load control bit, Bits DB13:DB2 can either be used to set the modulus or the fast-lock timer value. When the load control bit (DB23) is set to 0, the required modulus can be programmed in the R-divider register (DB13:DB2). R-DIVIDER REGISTER, R1 The on-chip R-divider register is programmed by setting R1 [1, 0] to [0, 1]. Table 8 shows the input data format for programming this register. When the load control bit (DB23) is set to 1, the required fastlock timer value can be programmed in the R-divider register (DB13:DB2). Load Control When this bit is set to logic high, the value being programmed in the modulus is not loaded into the modulus. Instead, it sets the fast-lock timer. The value of the fast-lock timer divided by fPFD is the amount of time the PLL stays in wide bandwidth mode. MUXOUT The on-chip multiplexer is controlled by R1 [22 ... 20] on the ADF4154. Table 8 shows the truth table. Digital Lock Detect The digital lock detect output goes high if there are 40 successive PFD cycles with an input error of less than 15 ns. It stays high until a new channel is programmed or until the error at the PFD input exceeds 30 ns for one or more cycles. If the loop bandwidth is narrow compared with the PFD frequency, the error at the PFD inputs may drop below 15 ns for 40 cycles around a cycle slip. Therefore, the digital lock detect may briefly, and falsely, go high until the error exceeds 30 ns. In this case, the digital lock detect is reliable only as a loss-of-lock detector. This programmable register sets the fractional modulus, which is the ratio of the PFD frequency to the channel step resolution on the RF output. Refer to the RF Synthesizer: A Worked Example section for more information. The ADF4154 programmable modulus is double buffered, meaning that two events must occur before the part can use a new modulus value. The first event is that the new modulus value must be latched into the device by writing to the R-divider register, and the second event is that a new write must be performed on the N-divider register. Therefore, whenever the modulus value is updated, the N-divider register must be written to so that the modulus value is loaded correctly. CONTROL REGISTER, R2 The on-chip control register is programmed by setting R2 [1, 0] to [0, 1]. Table 9 shows the input data format for programming this register. RF Counter Reset DB2 is the RF counter reset bit for the ADF4154. When this bit is set to 1, the RF synthesizer counters are held in reset. For normal operation, this bit should be set to 0. Rev. C | Page 16 of 24 Data Sheet ADF4154 RF Charge Pump Three-State This bit (DB3) puts the charge pump into three-state mode when it is programmed to 1. For normal operation, it should be set to 0. RF Power-Down DB4 on the ADF4154 provides the programmable power-down mode. Setting Bit DB4 to 1 powers down the device. Setting Bit DB4 to 0 returns the synthesizer to normal operation. While in software power-down mode, the part retains all information in its registers. Only when supplies are removed are the register contents lost. When a power-down is activated, the following events occur: 1. 2. 3. 4. 5. 6. All active dc current paths are removed. The synthesizer counters are forced to their load state conditions. The charge pump is forced into three-state mode. The digital lock detect circuitry is reset. The RFIN input is debiased. The input register remains active and capable of loading and latching data. Lock Detect Precision (LDP) When the LDP bit (DB5) is programmed to 0, 24 consecutive reference cycles of 15 ns must occur before the digital lock detect is set. When this bit is programmed to 1, 40 consecutive reference cycles of 15 ns must occur before digital lock detect is set. Phase Detector Polarity DB6 sets the phase detector polarity. When the VCO characteristics are positive, this bit should be set to 1. When they are negative, this bit should be set to 0. Charge Pump (CP) Current Setting and CP/2 DB7, DB8, DB9, and DB10 set the charge pump current, which should be set according to the loop filter design (see Table 9). REFIN Doubler The maximum allowed REFIN frequency when the doubler is enabled is 30 MHz. NOISE AND SPUR REGISTER, R3 The on-chip noise and spur register is programmed by setting R3 [1, 0] to [1, 1]. Table 10 shows the input data format for programming this register. Noise and Spur Mode Noise and spur mode allows the user to optimize a design either for improved spurious performance or for improved phase noise performance. When the lowest spur setting is chosen, dither is enabled. This randomizes the fractional quantization noise so that it looks more like white noise than spurious noise, meaning that the part is optimized for improved spurious performance. This operation is typically used when the PLL closed-loop bandwidth is wide for fast-locking applications. A wide-loop bandwidth is defined as a loop bandwidth greater than 1/10 of the RFOUT channel step resolution (fRES). A wide-loop filter does not attenuate the spurs to a level that a narrow-loop bandwidth would. When the low noise and spur setting is enabled, dither is disabled. This optimizes the synthesizer to operate with improved noise performance. However, the spurious performance is degraded in this mode compared with the lowest spur setting. To further improve noise performance, the lowest noise setting option can be used, which reduces the phase noise. As well as disabling the dither, it ensures that the charge pump operates in an optimum region for noise performance. This setting is extremely useful if a narrow-loop filter bandwidth is used. The synthesizer ensures extremely low noise, and the filter attenuates the spurs. The typical performance characteristics show the trade-offs in a typical WCDMA setup for different noise and spur settings. RESERVED BITS These bits should be set to 0 for normal operation. Setting the REFIN doubler bit (DB11) to 0 feeds the REFIN signal directly to the 4-bit R-counter, which disables the doubler. Setting the REFIN doubler bit to 1 multiplies the REFIN frequency by a factor of 2 before feeding into the 4-bit R-counter. When the doubler is disabled, the REFIN falling edge is the active edge at the PFD input to the fractional synthesizer. When the doubler is enabled, both the rising and falling edges of REFIN become active edges at the PFD input. When the doubler is enabled and the lowest spur mode is chosen, the in-band phase noise performance is sensitive to the REFIN duty cycle. The phase noise degradation can be as much as 5 dB for the REFIN duty cycles outside a 45% to 55% range. The phase noise is insensitive to the REFIN duty cycle in the lowest noise mode and in the lowest noise and spur mode. The phase noise is insensitive to the REFIN duty cycle when the doubler is disabled. Rev. C | Page 17 of 24 ADF4154 Data Sheet INITIALIZATION SEQUENCE The following initialization sequence should be followed after powering up the part: 1. 2. 3. 4. 5. 6. Clear all test modes by writing all 0s to the noise and spur register. Select the noise and spur mode required for the application by writing to the noise and spur register. For example, writing Hex 0003C7 to the part selects low noise mode. Enable the counter reset in the control register by writing a 1 to DB2 and selecting the required settings in the control register. Load the R-divider register (with the load control bit [DB23] set to 0). Load the N-divider register. Disable the counter reset by writing a 0 to DB2 in the control register. The part should now lock to the set frequency. RF SYNTHESIZER: A WORKED EXAMPLE This equation governs how the synthesizer should be programmed. RFOUT = [INT + (FRAC/MOD)] × [fPFD] (3) where: RFOUT is the RF frequency output. INT is the integer division factor. FRAC is the fractionality. MOD is the modulus. The PFD frequency can be calculated as follows: fPFD = [REFIN × (1 = D)/R] (4) where: REFIN is the reference frequency input. D is the value of the RF REFIN doubler bit. R is the RF reference division factor. For example, in a GSM 1800 system, where a 1.8 GHz RF frequency output (RFOUT) is required, a 13 MHz reference frequency input (REFIN) is available and a 200 kHz channel resolution (fRES) is required on the RF output. MOD = REFIN /f RES MOD = 13 MHz/200 kHz = 65 From Equation 4, fPFD = [13 MHz × (1 + 0)/1] = 13 MHz 1.8 GHz = 13 MHz × (INT + FRAC 65) (5) (6) where: INT is 138. FRAC is 30. the RF output. For example, a GSM 1800 system using a 13 MHz REFIN sets the modulus to 65, resulting in meeting the required RF output resolution (fRES) of 200 kHz (13 MHz/65). REFERENCE DOUBLER AND REFERENCE DIVIDER The on-chip reference doubler allows the input reference signal to be doubled. This is useful for increasing the PFD comparison frequency, which in turn improves the noise performance of the system. For example, doubling the PFD frequency usually results in an improvement in noise performance of 3 dB. It is important to note that the PFD cannot operate with frequencies greater than 32 MHz due to a limitation in the speed of the Σ-Δ circuit of the N-divider. 12-BIT PROGRAMMABLE MODULUS Unlike most fractional-N PLLs, the ADF4154 allows the user to program the modulus over a 12-bit range. Therefore, several configurations of the ADF4154 are possible for an application by varying the modulus value, the reference doubler, and the 4-bit R-counter. For example, consider an application that requires a 1.75 GHz RF and a 200 kHz channel step resolution. The system has a 13 MHz reference signal. One possible setup is feeding the 13 MHz REFIN directly into the PFD and programming the modulus to divide by 65, which results in the required 200 kHz resolution. Another possible setup is using the reference doubler to create a 26 MHz input frequency from the 13 MHz REFIN signal. The 26 MHz signal is then fed into the PFD, which programs the modulus to divide by 130. This setup also results in 200 kHz resolution, plus it offers superior phase noise performance compared with the previous setup. The programmable modulus is also very useful for multistandard applications. If a dual-mode phone requires PDC and GSM 1800 standards, the programmable modulus is a huge benefit. The PDC requires a 25 kHz channel step resolution, whereas the GSM 1800 requires a 200 kHz channel step resolution. A 13 MHz reference signal could be fed directly to the PFD. The modulus would be programmed to 520 when in PDC mode (13 MHz/520 = 25 kHz). The modulus would be reprogrammed to 65 for GSM 1800 operation (13 MHz/65 = 200 kHz). It is important that the PFD frequency remains constant (13 MHz). By keeping the PFD constant, the user can design a one-loop filter that can be used in both setups without running into stability issues. The ratio of the RF frequency to the PFD frequency affects the loop design. By keeping this relationship constant, the same loop filter can be used in both applications. SPURIOUS OPTIMIZATION AND FAST LOCK MODULUS The choice of modulus (MOD) depends on the reference signal (REFIN) available and the channel resolution (fRES) required at The ADF4154 can be optimized for low spurious signals by using the noise and spur register. However, to achieve fast-lock time, a wider loop bandwidth is needed. Note that a wider loop Rev. C | Page 18 of 24 Data Sheet ADF4154 bandwidth can lead to notable spurious signals, which cannot be reduced significantly by the loop filter. • Using the fast-lock feature can achieve the same fast-lock time as the noise and spur register, but with the advantage of lower spurious signals because the final loop bandwidth is reduced by a quarter. Connect an extra resistor (R1A) directly from MUXOUT, as shown in Figure 19. The extra resistor must be chosen such that the parallel combination of an extra resistor and the damping resistor (R1) is reduced to ¼ of the original value of R1 (see Figure 20). ADF4154 FAST-LOCK TIMER AND REGISTER SEQUENCES 5. After this procedure is complete, the user need only repeat Step 5 to invoke fast lock for subsequent frequency jumps. MUXOUT R1A 04833-029 Figure 19. Fast-Lock Loop Filter Topology—Topology 1 ADF4154 R2 CP VCO C1 C2 R1A R1 C3 MUXOUT Figure 20. Fast-Lock Loop Filter Topology—Topology 2 SPUR MECHANISMS The following section describes three spur mechanisms that can arise when using a fractional-N synthesizer and how to minimize them in the ADF4154. Fractional Spurs FAST LOCK: AN EXAMPLE If a PLL has reference frequencies of 13 MHz and fPFD = 13 MHz and a required lock time of 50 µs, the PLL is set to wide bandwidth for 40 µs. If the time period set for the wide bandwidth is 40 µs, then Fast-Lock Timer Value = Time in Wide Bandwidth × fPFD Fast-Lock Timer Value = 40 µs × 13 MHz = 520 Therefore, 520 must be loaded into the R-divider register in Step 1 of the sequence described in the Fast-Lock Timer and Register Sequences section. FAST LOCK: LOOP FILTER TOPOLOGY To use fast-lock mode, an extra connection from the PLL to the loop filter is needed. The damping resistor in the loop filter must be reduced to ¼ of its value while in wide bandwidth mode. This is required because the charge pump current is increased by 16 while in wide bandwidth mode, and stability must be ensured. During fast lock, the MUXOUT pin is shorted to ground (the fast-lock switch must be programmed to appear at the MUXOUT pin). The following two topologies can be used: • C3 04833-030 Load the R-divider register with DB23 = 1 and the chosen fast-lock timer value (DB13 to DB2) instead of the modulus. Note that the duration that the PLL remains in wide bandwidth is equal to the fast-lock timer/fPFD. Load the noise and spur register. Load the control register. Load the R-divider register with DB23 = 0 and MUXOUT = 110 (DB22 to DB20). This sets the fast-lock switch to appear at the MUXOUT pin. All the other needed parameters, including the modulus, also need to be loaded. Load the N-divider register, including fast lock = 1 (DB23), to activate fast-lock mode. C2 R1 When the load control bit is set to 1, the timer value is loaded via the 12-bit modulus value. To use fast lock, the PLL must be written to in the following sequence: 2. 3. 4. VCO C1 If the fast-lock mode is used, a timer value needs to be loaded into the PLL to determine the time spent in wide bandwidth mode. 1. R2 CP The fractional interpolator in the ADF4154 is a third-order Σ-Δ modulator (SDM) with a modulus MOD that is programmable to an integer value between 2 and 4095. In low spur mode (dither enabled), the minimum allowed value of MOD is 50. The SDM is clocked at the PFD reference rate (fPFD) that allows PLL output frequencies to be synthesized at a channel step resolution of fPFD/MOD. In low noise mode and low noise and spur mode (dither off), the quantization noise from the Σ-Δ modulator appears as fractional spurs. The interval between spurs is fPFD/L, where L is the repeat length of the code sequence in the digital Σ-Δ modulator. For the third-order modulator used in the ADF4154, the repeat length depends on the value of MOD, as shown in Table 11. Table 11. Fractional Spurs with Dither Off Condition (Dither Off) If MOD is divisible by 2, but not 3 If MOD is divisible by 3, but not 2 If MOD is divisible by 6 Otherwise Divide the damping resistor (R1) into two values (R1 and R1A) that have a ratio of 1:3 (see Figure 19). Rev. C | Page 19 of 24 Repeat Length 2 × MOD 3 × MOD 6 × MOD MOD Spur Interval Channel step/2 Channel step/3 Channel step/6 Channel step ADF4154 Data Sheet In low spur mode (dither enabled), the repeat length is extended to 221 cycles, regardless of the value of MOD, which makes the quantization error spectrum appear as broadband noise. This can degrade the in-band phase noise at the PLL output by as much as 10 dB. Therefore, for lowest noise, dither off is a better choice, particularly when the final loop BW is low enough to attenuate even the lowest frequency fractional spur. Integer Boundary Spurs Another mechanism for fractional spur creation are interactions between the RF VCO frequency and the reference frequency. When these frequencies are not integer related (as is the case with fractional-N synthesizers), spur sidebands appear on the VCO output spectrum at an offset frequency that corresponds to the beat note or the difference in frequency between an integer multiple of the reference and the VCO frequency. These spurs are attenuated by the loop filter and are more noticeable on channels close to integer multiples of the reference, where the difference frequency can be inside the loop bandwidth, thus the name integer boundary spurs. The maximum allowable serial clock rate is 20 MHz. This means that the maximum update rate possible for the device is 909 kHz or one update every 1.1 µs. ADuC812 Interface Figure 21 shows the interface between the ADF4154 and the ADuC812 MicroConverter®. Because the ADuC812 is based on an 8051 core, this interface can be used with any 8051-based microcontroller. The MicroConverter is set up for SPI master mode with CPHA set to 0. To initiate the operation, bring the I/O port driving LE low. Each latch of the ADF4154 requires a 24-bit word, which is accomplished by writing three 8-bit bytes from the MicroConverter to the device. After the third byte is written, the LE input should be brought high to complete the transfer. When operating in the mode described, the maximum SCLOCK rate of the ADuC812 is 4 MHz. This means that the maximum rate at which the output frequency can be changed is 180 kHz. ADuC812 Reference Spurs ADF4154 SCLOCK SPUR CONSISTENCY When jumping from Frequency A to Frequency B and then back again using fractional-N synthesizers, the spur levels often differ each time Frequency A is programmed. However, in the ADF4154, the spur levels on any particular channel are always consistent. FILTER DESIGN—ADIsimPLL A filter design and analysis program is available to help the user implement the PLL design. Visit www.analog.com/pll for a free download of the ADIsimPLL software. The software designs, simulates, and analyzes the entire PLL frequency and time domain response. Various passive and active filter architectures are allowed. MOSI SDATA LE I/O PORTS MUXOUT (LOCK DETECT) 04833-024 Reference spurs are generally not a problem in fractional-N synthesizers because the reference offset is far outside the loop bandwidth. However, any reference feedthrough mechanism that bypasses the loop can cause a problem. One such mechanism is feedthrough of low levels of on-chip reference switching noise through the RFIN pin back to the VCO, resulting in reference spur levels as high as –90 dBc. Care should be taken in the PCB layout to ensure that the VCO is well separated from the input reference to avoid a possible feedthrough path on the board. SCLK Figure 21. ADuC812-to-ADF4154 Interface ADSP-21xx Interface Figure 22 shows the interface between the ADF4154 and the ADSP-21xx digital signal processor. As discussed previously, the ADF4154 requires a 24-bit serial word for each latch write. The easiest way to accomplish this using a device in the ADSP-21xx family is to use the autobuffered transmit mode of operation with alternate framing. This provides a means for transmitting an entire block of serial data before an interrupt is generated. Set up the word length for eight bits and use three memory locations for each 24-bit word. To program each 24-bit latch, store each of the three 8-bit bytes, enable the autobuffered mode, and write to the transmit register of the DSP. This last operation initiates the autobuffered transfer. ADSP-21xx SCLOCK DT The ADF4154 has a simple, SPI®-compatible serial interface for writing to the device. SCLK, SDATA, and LE control the data transfer. When LE (latch enable) is high, the 22 bits that have been clocked into the input register on each rising edge of SCLK are transferred to the appropriate latch. See Figure 2 for the timing diagram and Table 5 for the latch truth table. Rev. C | Page 20 of 24 TFS I/O FLAGS SDATA LE MUXOUT (LOCK DETECT) 04833-025 INTERFACING ADF4154 SCLK Figure 22. ADSP-21xx-to-ADF4154 Interface Data Sheet ADF4154 PCB DESIGN GUIDELINES FOR CHIP SCALE PACKAGE The lands on the chip scale package (CP-20-1) are rectangular. The printed circuit board pad for these should be 0.1 mm longer than the package land length and 0.05 mm wider than the package land width. The land should be centered on the pad. This ensures that the solder joint size is maximized. The bottom of the chip scale package has a central thermal pad. The thermal pad on the printed circuit board should be at least as large as this exposed pad. On the printed circuit board, there should be a clearance of at least 0.25 mm between the thermal pad and the inner edges of the pad pattern to avoid shorting. Thermal vias may be used on the printed circuit board thermal pad to improve thermal performance of the package. If vias are used, they should be incorporated into the thermal pad at 1.2 mm pitch grid. The via diameter should be between 0.3 mm and 0.33 mm, and the via barrel should be plated with 1 oz of copper to plug the via. The user should connect the printed circuit board thermal pad to AGND. Rev. C | Page 21 of 24 ADF4154 Data Sheet OUTLINE DIMENSIONS 5.10 5.00 4.90 16 9 4.50 4.40 4.30 6.40 BSC 1 8 PIN 1 1.20 MAX 0.15 0.05 0.20 0.09 0.30 0.19 0.65 BSC COPLANARITY 0.10 0.75 0.60 0.45 8° 0° SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-153-AB Figure 23. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters 0.30 0.25 0.18 0.50 BSC PIN 1 INDICATOR 20 16 15 1 EXPOSED PAD 2.30 2.10 SQ 2.00 11 TOP VIEW 0.80 0.75 0.70 0.65 0.60 0.55 5 10 0.20 MIN BOTTOM VIEW 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE 6 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-WGGD-1. 08-16-2010-B PIN 1 INDICATOR 4.10 4.00 SQ 3.90 Figure 24. 20-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 4 mm × 4 mm Very Very Thin Quad, (CP-20-6) Dimensions shown in millimeters ORDERING GUIDE Model 1 ADF4154BRU ADF4154BRU-REEL ADF4154BRU-REEL7 ADF4154BRUZ ADF4154BRUZ-RL ADF4154BRUZ-RL7 ADF4154BCPZ ADF4154BCPZ-RL ADF4154BCPZ-RL7 EVAL-ADF4154EBZ1 1 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C Description 16-Lead Thin Shrink Small Outline Package [TSSOP] 16-Lead Thin Shrink Small Outline Package [TSSOP] 16-Lead Thin Shrink Small Outline Package [TSSOP] 16-Lead Thin Shrink Small Outline Package [TSSOP] 16-Lead Thin Shrink Small Outline Package [TSSOP] 16-Lead Thin Shrink Small Outline Package [TSSOP] 20-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 20-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 20-Lead Lead Frame Chip Scale Package [LFCSP_WQ] Evaluation Board Z = RoHS Compliant Part. Rev. C | Page 22 of 24 Package Option RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 CP-20-6 CP-20-6 CP-20-6 Data Sheet ADF4154 NOTES Rev. C | Page 23 of 24 ADF4154 Data Sheet NOTES I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2004–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04833-0-8/12(C) Rev. C | Page 24 of 24