TI SN74ALVCHG162282

SN74ALVCHG162282
18-BIT TO 36-BIT REGISTERED BUS EXCHANGER
WITH 3-STATE OUTPUTS
SCES094C – FEBRUARY 1997 – REVISED JUNE 1999
D
D
D
D
D
D
D
DBB PACKAGE
(TOP VIEW)
Member of the Texas Instruments
Widebus Family
EPIC  (Enhanced-Performance Implanted
CMOS) Sub-Micron Process
A-Port Outputs Have Equivalent 50-Ω
Series Resistors and B-Port Outputs Have
Equivalent 20-Ω Series Resistors, So No
External Resistors Are Required
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
Latch-Up Performance Exceeds 250 mA Per
JESD 17
Bus-Hold On Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
Packaged in Thin Very Small-Outline
Package
VCC
GND
2B9
1B9
2B8
GND
1B8
2B7
1B7
VCC
2B6
1B6
2B5
1B5
GND
2B4
1B4
2B3
1B3
VCC
GND
2B2
1B2
2B1
1B1
VCC
A1
A2
A3
GND
A4
A5
A6
VCC
A7
A8
A9
GND
CLK
SEL
NOTE: For order entry:
The DBB package is abbreviated to G.
For tape and reel:
The DBBR package is abbreviated to GR.
description
The SN74ALVCHG162282 is an 18-bit to 36-bit
registered bus exchanger. This device is intended
for use in applications where data must be
transferred from a narrow high-speed bus to a
wide lower-frequency bus. It is designed
specifically for low-voltage (3.3-V) VCC operation.
The device provides synchronous data exchange
between the two ports. Data is stored in the
internal registers on the low-to-high transition of
the clock (CLK) input. For data transfer in the
B-to-A direction, the select (SEL) input selects 1B
or 2B data for the A outputs.
For data transfer in the A-to-B direction, a
two-stage pipeline is provided in the 1B path, with
a single storage register in the 2B path. Data flow
is controlled by the active-low output-enable (OE)
and direction-control (DIR) input. DIR is registered
to synchronize the bus direction changes with the
clock.
1
80
2
79
3
78
4
77
5
76
6
75
7
74
8
73
9
72
10
71
11
70
12
69
13
68
14
67
15
66
16
65
17
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
51
31
50
32
49
33
48
34
47
35
46
36
45
37
44
38
43
39
42
40
41
VCC
GND
1B10
2B10
1B11
GND
2B11
1B12
2B12
VCC
1B13
2B13
1B14
2B14
GND
1B15
2B15
1B16
2B16
VCC
GND
1B17
2B17
1B18
2B18
VCC
A18
A17
A16
GND
A15
A14
A13
VCC
A12
A11
A10
GND
OE
DIR
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus and EPIC are trademarks of Texas Instruments Incorporated.
Copyright  1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SN74ALVCHG162282
18-BIT TO 36-BIT REGISTERED BUS EXCHANGER
WITH 3-STATE OUTPUTS
SCES094C – FEBRUARY 1997 – REVISED JUNE 1999
description (continued)
The A-port N-channel output transistors are sized at 450 µm and the P-channel output transistors are sized at
700 µm. All A-port outputs have equivalent 50-Ω series resistors. The B-port N-channel output transistors are
sized at 225 µm, and the P-channel output transistors are sized at 560 µm. All B-port outputs have equivalent
20-Ω series resistors.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The switching characteristics are based on 25-pF (A port) and 80-pF (B port) loads, but are tested with the
standard 50-pF load.
The SN74ALVCHG162282 is characterized for operation from 0°C to 70°C.
Function Tables
A-TO-B STORAGE
(OE = L, DIR = H)
OUTPUTS
INPUTS
SEL
CLK
A
H
X
X
L
↑
L
1B
1B0†
2B
2B0†
L‡
H‡
L
L
↑
H
H
† Output
level
before
indicated
steady-state input conditions were
established
‡ Two CLK edges are needed to propagate
the data.
B-TO-A STORAGE
(OE = L, DIR = L)
INPUTS
OUTPUT
A
CLK
SEL
1B
2B
↑
H
X
L
↑
H
X
H
L§
H§
↑
L
L
X
L
↑
L
H
X
H
§ Two CLK edges are needed to propagate the
data. The data is loaded in the first register
when SEL is low and propagates to the
second register when SEL is high.
OUTPUT ENABLE
INPUTS
2
CLK
OE
↑
↑
↑
OUTPUTS
DIR
A
H
X
Z
Z
L
H
Z
Active
L
L
Active
Z
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1B, 2B
• DALLAS, TEXAS 75265
SN74ALVCHG162282
18-BIT TO 36-BIT REGISTERED BUS EXCHANGER
WITH 3-STATE OUTPUTS
SCES094C – FEBRUARY 1997 – REVISED JUNE 1999
logic diagram (positive logic)
CLK
SEL
OE
39
40
42
CE
C1
DIR
41
1D
25
1 of 18 Channels
1B1
G1
CE
C1
A1
27
C1
1
1D
1D
1
24
2B1
CE
C1
C1
1D
1D
CE
C1
1D
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• DALLAS, TEXAS 75265
3
SN74ALVCHG162282
18-BIT TO 36-BIT REGISTERED BUS EXCHANGER
WITH 3-STATE OUTPUTS
SCES094C – FEBRUARY 1997 – REVISED JUNE 1999
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Input voltage range, VI: Except I/O ports (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
I/O ports (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Package thermal impedance, θJA (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The input and output positive voltage ratings may be exceeded up to 4.6 V if the input and output clamp-current ratings are observed.
3. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions (see Note 4)
VCC
VIH
Supply voltage
VIL
VI
Low-level input voltage
VO
Output voltage
High-level input voltage
VCC = 3 V to 3.6 V
VCC = 3 V to 3.6 V
Input voltage
IOH
High level output current
High-level
IOL
Low level output current
Low-level
∆t/∆v
Input transition rise or fall rate
MIN
MAX
3
3.6
2
0
0
A to B
B to A
A to B
B to A
UNIT
V
V
0.8
V
VCC
VCC
V
VCC = 3 V
VCC = 3 V
8
VCC = 3 V
VCC = 3 V
8
6
6
10
V
mA
mA
ns/V
TA
Operating free-air temperature
0
70
°C
NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74ALVCHG162282
18-BIT TO 36-BIT REGISTERED BUS EXCHANGER
WITH 3-STATE OUTPUTS
SCES094C – FEBRUARY 1997 – REVISED JUNE 1999
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VOH
A to B
B to A
VOL
A to B
B to A
TEST CONDITIONS
IOH = –100 µA
IOH = –8 mA
3V
IOH = –6 mA
IOL = 100 µA
VI = VCC or GND
VI = 0.8 V
II(hold)
(
)
VI = 2 V
VI = 0 to 3.6 V‡
VO = VCC or GND
VI = VCC or GND,
∆ICC
Ci
Control inputs
Cio
A or B ports
MIN
One input at VCC – 0.6 V,
IO = 0
Other inputs at VCC or GND
TYP†
UNIT
V
2
3 V to 3.6 V
0.2
3V
0.8
3V
0.8
3.6 V
±5
3V
75
3V
–75
V
µA
µA
3.6 V
±500
3.6 V
±10
µA
3.6 V
40
µA
750
µA
3 V to 3.6 V
VI = VCC or GND
VO = VCC or GND
MAX
VCC–0.2
2
3V
IOL = 8 mA
IOL = 6 mA
II
IOZ§
ICC
VCC
3 V to 3.6 V
3.3 V
4
3.3 V
8.5
pF
pF
† All typical values are at VCC = 3.3 V, TA = 25°C.
‡ This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another.
§ For I/O ports, the parameter IOZ includes the input leakage current.
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 1)
VCC = 3.3 V
± 0.3 V
MIN
fclock
tw
tsu
th
Clock frequency
160
Pulse duration, CLK high or low
2.3
Setup time,
time high or low
Hold time,
time high or low
POST OFFICE BOX 655303
A data before CLK↑
1.5
B data before CLK↑
2
DIR before CLK↑
2
SEL before CLK↑
2
A data after CLK↑
0.3
B data after CLK↑
0.3
DIR after CLK↑
0.3
SEL after CLK↑
0.3
• DALLAS, TEXAS 75265
UNIT
MAX
MHz
ns
ns
ns
5
SN74ALVCHG162282
18-BIT TO 36-BIT REGISTERED BUS EXCHANGER
WITH 3-STATE OUTPUTS
SCES094C – FEBRUARY 1997 – REVISED JUNE 1999
switching characteristics over recommended operating free-air temperature range,
CL = 25 pF (A port), 80 pF (B port) (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
fmax
tpd
d
MIN
CLK
ten
OE
CLK
tdis
di
OE
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
UNIT
MAX
160
CLK
6
VCC = 3.3 V
± 0.3 V
MHz
A
1.5
5
B
1.5
7.4
A
1.5
6.3
B
1.5
9.4
A
1.5
6
B
1.5
9.5
A
1.5
6.4
B
1.5
7.8
A
1.5
5
B
1.5
7.6
ns
ns
ns
SN74ALVCHG162282
18-BIT TO 36-BIT REGISTERED BUS EXCHANGER
WITH 3-STATE OUTPUTS
SCES094C – FEBRUARY 1997 – REVISED JUNE 1999
PARAMETER MEASUREMENT INFORMATION
6V
S1
500 Ω
From Output
Under Test
Open
GND
CL = 50 pF
(see Note A)
500 Ω
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
6V
GND
LOAD CIRCUIT
tw
2.7 V
2.7 V
Timing
Input
1.5 V
1.5 V
1.5 V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
1.5 V
1.5 V
0V
tPLH
Output
Control
(low-level
enabling)
tPLZ
3V
1.5 V
tPZH
VOH
1.5 V
VOL
1.5 V
0V
Output
Waveform 1
S1 at 6 V
(see Note B)
tPHL
1.5 V
2.7 V
1.5 V
tPZL
2.7 V
Output
VOLTAGE WAVEFORMS
PULSE DURATION
th
2.7 V
Data
Input
1.5 V
0V
0V
tsu
Input
1.5 V
Input
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.3 V
VOL
tPHZ
1.5 V
VOH
VOH – 0.3 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The output is measured with one input transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
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7
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Copyright  1999, Texas Instruments Incorporated