SN74ALB16245 3.3-V ALB 16-BIT TRANSCEIVER WITH 3-STATE OUTPUTS SCBS678B – SEPTEMBER 1996 – REVISED JULY 1997 D D D D D D D DGG OR DL PACKAGE (TOP VIEW) Member of the Texas Instruments Widebus Family State-of-the-Art Advanced Low-Voltage BiCMOS (ALB) Technology Design for 3.3-V Operation Schottky Diodes on All Inputs to Eliminate Overshoot and Undershoot Industry Standard ’16245 Pinout Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise Flow-Through Architecture Optimizes PCB Layout Package Options Include Plastic 300-mil Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages 1DIR 1B1 1B2 GND 1B3 1B4 VCC 1B5 1B6 GND 1B7 1B8 2B1 2B2 GND 2B3 2B4 VCC 2B5 2B6 GND 2B7 2B8 2DIR description The SN74ALB16245 is a 16-bit transceiver designed for high-speed, low-voltage (3.3-V) VCC operation. This device is intended to replace the conventional transceiver in any speed-critical path. The small propagation delay is achieved using a unity gain amplifier on the input and feedback resistors from input to output, which allows the output to track the input with a small offset voltage. 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 32 18 31 19 30 20 29 21 28 22 27 23 26 24 25 1OE 1A1 1A2 GND 1A3 1A4 VCC 1A5 1A6 GND 1A7 1A8 2A1 2A2 GND 2A3 2A4 VCC 2A5 2A6 GND 2A7 2A8 2OE This device can be used as two 8-bit transceivers or one 16-bit transceiver. It allows data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so that the buses are effectively isolated. The SN74ALB16245 is characterized for operation from –40°C to 85°C. FUNCTION TABLE (each 8-bit section) INPUTS OE DIR OPERATION L L B data to A bus L H A data to B bus H X Isolation Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus is a trademark of Texas Instruments Incorporated. Copyright 1997, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN74ALB16245 3.3-V ALB 16-BIT TRANSCEIVER WITH 3-STATE OUTPUTS SCBS678B – SEPTEMBER 1996 – REVISED JULY 1997 logic symbol† 48 1OE 1DIR G3 1 3 EN1 [BA] 3 EN2 [AB] 25 2OE 2DIR G6 24 6 EN4 [BA] 6 EN5 [AB] 1A1 47 2 1 1B1 2 1A2 1A3 1A4 1A5 1A6 1A7 1A8 2A1 2A2 2A3 2A4 2A5 2A6 2A7 2A8 46 3 44 5 43 6 41 8 40 9 38 11 37 12 36 13 4 5 35 14 33 16 32 17 30 19 29 20 27 22 26 23 1B2 1B3 1B4 1B5 1B6 1B7 1B8 2B1 2B2 2B3 2B4 2B5 2B6 2B7 2B8 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. logic diagram (positive logic) 1DIR 1 2DIR 48 1A1 25 1OE 47 2A1 2 24 36 13 1B1 To Seven Other Channels 2 POST OFFICE BOX 655303 2OE To Seven Other Channels • DALLAS, TEXAS 75265 2B1 SN74ALB16245 3.3-V ALB 16-BIT TRANSCEIVER WITH 3-STATE OUTPUTS SCBS678B – SEPTEMBER 1996 – REVISED JULY 1997 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Input voltage range, VI: Except I/O ports (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V I/O ports (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current through each VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA Package thermal impedance, θJA (see Note 3): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89°C/W DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This value is limited to 4.6 V maximum. 3. The package thermal impedance is calculated in accordance with JESD 51. recommended operating conditions VCC IOH‡ Supply voltage IOL‡ ∆t/∆v Low-level output current MIN MAX 3 3.6 V –25 mA High-level output current Input transition rise or fall rate 25 mA 5 ns/V 85 °C Outputs enabled TA Operating free-air temperature ‡ Refer to Figures 1 and 2 for typical I/O ranges. –40 UNIT electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK II TEST CONDITIONS A or B ports VCC = 3 V II = 18 mA II = –18 mA Control inputs VCC = 3.6 V, VI = VCC or GND TYP§ 3.7 –0.9 OE low VI = VCC A or B ports MIN 0.4 OE high VCC = 3 3.6 6V OE low VI = 0 –0.7 OE high IOZH IOZL VCC = 3.6 V, VCC = 3.6 V, VO = 3 V VO = 0.5 V ICC/buffer ICCZ VCC = 3.6 V, VCC = 3.6 V, IO = 0, VI = VCC or GND Control inputs = VCC or GND ∆ICC¶ VCC = 3 V to 3.6 V, One input at VCC – 0.6 V, Other inputs at VCC or GND Ci VI = 3 V or 0 VO = 3 V or 0 MAX UNIT VCC+1.2 –1.2 V ±10 µA 0.6 mA 25 µA –1 mA –60 µA 0.7 20 µA –0.2 –50 µA 3.7 5.6 mA 0.8 mA 600 µA 3.5 pF Cio 7.5 § All typical values are at VCC = 3.3 V, TA = 25°C. ¶ This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND. pF POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN74ALB16245 3.3-V ALB 16-BIT TRANSCEIVER WITH 3-STATE OUTPUTS SCBS678B – SEPTEMBER 1996 – REVISED JULY 1997 switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 3) VCC = 3.3 V ± 0.3 V MIN TYP† MAX PARAMETER FROM (INPUT) TO (OUTPUT) tpd A or B B or A 0.6 1.3 2 ns ten OE A or B 1.5 3.2 6 ns tdis OE † All typical values are at VCC = 3.3 V, TA = 25°C. A or B 1.8 2.8 4.2 ns 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 UNIT SN74ALB16245 3.3-V ALB 16-BIT TRANSCEIVER WITH 3-STATE OUTPUTS SCBS678B – SEPTEMBER 1996 – REVISED JULY 1997 OUTPUT VOLTAGE HIGH vs INPUT VOLTAGE VOH – Output Voltage – V 3.5 3 2.5 –100 µA –25 mA –6 mA 2 1.5 1.5 2 2.5 3 3.5 4 VI – Input Voltage – V Figure 1. VOH Over Recommended Free-Air Temperature Range OUTPUT VOLTAGE LOW vs INPUT VOLTAGE 2 VOL – Output Voltage – V 1.5 25 mA 1 100 µA 0.5 6 mA 0 0 0.5 1 1.5 2 VI – Input Voltage – V Figure 2. VOL Over Recommended Free-Air Temperature Range POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN74ALB16245 3.3-V ALB 16-BIT TRANSCEIVER WITH 3-STATE OUTPUTS SCBS678B – SEPTEMBER 1996 – REVISED JULY 1997 PARAMETER MEASUREMENT INFORMATION 6V S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND LOAD CIRCUIT tw 3V 3V Timing Input 0V 0V VOLTAGE WAVEFORMS PULSE DURATION th 3V Data Input 1.5 V 1.5 V 0V 3V Output Control (low-level enabling) VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 1.5 V 1.5 V 1.5 V 0V tPZL 3V 1.5 V 0V tPLH Output 1.5 V 1.5 V tsu Input 1.5 V Input Output Waveform 1 S1 at 6 V (see Note B) 3V 1.5 V VOL + 0.3 V tPZH tPHL VOH 1.5 V tPLZ 1.5 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VOL tPHZ Output Waveform 2 S1 at GND (see Note B) 1.5 V VOH VOH – 0.3 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 Ω, tr 2.5 ns, tf 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. v Figure 3. Load Circuit and Voltage Waveforms 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 v v IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. 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