TI SN74ALVCHG162280

SN74ALVCHG162280
16-BIT TO 32-BIT REGISTERED BUS EXCHANGER
WITH BYTE MASKS AND 3-STATE OUTPUTS
SCES093C – FEBRUARY 1997 – REVISED JUNE 1999
D
D
D
D
D
D
D
DBB PACKAGE
(TOP VIEW)
Member of the Texas Instruments
Widebus  Family
EPIC  (Enhanced-Performance Implanted
CMOS) Sub-Micron Process
A-Port Outputs Have Equivalent 50-Ω
Series Resistors and B-Port Outputs Have
Equivalent 20-Ω Series Resistors, So No
External Resistors Are Required
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
Latch-Up Performance Exceeds 250 mA Per
JESD 17
Bus-Hold On Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
Packaged in Thin Very Small-Outline
Package
VCC
GND
2B7
1B7
2B6
GND
1B6
2B5
1B5
VCC
2B4
1B4
2B3
1B3
GND
2B2
1B2
2B1
1B1
VCC
GND
2D2
1D2
2D1
1D1
VCC
C1
C2
A1
GND
A2
A3
A4
VCC
A5
A6
A7
GND
CLK
SEL
NOTE: For order entry:
The DBB package is abbreviated to G.
For tape and reel:
The DBBR package is abbreviated to GR.
description
The SN74ALVCHG162280 is a 16-bit to 32-bit
registered bus exchanger. This device is intended
for use in applications where data must be
transferred from a narrow high-speed bus to a
wide lower-frequency bus. It is designed
specifically for low-voltage (3.3-V) VCC operation.
The device provides synchronous data exchange
between the two ports, A and B. Data is stored in
the internal registers on the low-to-high transition
of the clock (CLK) input. For data transfer in the
B-to-A direction, the select (SEL) input selects 1B
or 2B data for the A outputs.
For data transfer in the A-to-B direction, a
two-stage pipeline is provided in the 1B path, with
a single storage register in the 2B path. Data flow
is controlled by the active-low output-enable (OE)
and direction-control (DIR) inputs. DIR is
registered to synchronize the bus direction
changes with the clock.
1
80
2
79
3
78
4
77
5
76
6
75
7
74
8
73
9
72
10
71
11
70
12
69
13
68
14
67
15
66
16
65
17
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
51
31
50
32
49
33
48
34
47
35
46
36
45
37
44
38
43
39
42
40
41
VCC
GND
1B8
2B8
1B9
GND
2B9
1B10
2B10
VCC
1B11
2B11
1B12
2B12
GND
1B13
2B13
1B14
2B14
VCC
GND
1B15
2B15
1B16
2B16
VCC
A16
A15
A14
GND
A13
A12
A11
VCC
A10
A9
A8
GND
OE
DIR
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus and EPIC are trademarks of Texas Instruments Incorporated.
Copyright  1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
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1
SN74ALVCHG162280
16-BIT TO 32-BIT REGISTERED BUS EXCHANGER
WITH BYTE MASKS AND 3-STATE OUTPUTS
SCES093C – FEBRUARY 1997 – REVISED JUNE 1999
description (continued)
Two mask bits are provided for both data bytes. The data (D) outputs are controlled by OE.
The A-port N-channel output transistors are sized at 450 µm and the P-channel output transistors are sized at
700 µm. All A-port outputs have equivalent 50-Ω series resistors. The B-port N-channel output transistors are
sized at 225 µm, and the P-channel output transistors are sized at 560 µm. All B-port outputs have equivalent
20-Ω series resistors.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The switching characteristics are based on 25-pF (A port) and 80-pF (B and D ports) loads, but are tested with
the standard 50-pF load.
The SN74ALVCHG162280 is characterized for operation from 0°C to 70°C.
2
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SN74ALVCHG162280
16-BIT TO 32-BIT REGISTERED BUS EXCHANGER
WITH BYTE MASKS AND 3-STATE OUTPUTS
SCES093C – FEBRUARY 1997 – REVISED JUNE 1999
Function Tables
A-TO-B STORAGE
(OE = L, DIR = H)
OUTPUTS
INPUTS
SEL
CLK
A
1B
2B
H
X
X
L
↑
L
1B0†
L‡
2B0†
L
↑
H
H‡
H
† Output
level
before
indicated
steady-state input conditions were
established
‡ Two CLK edges are needed to propagate
the data.
L
B-TO-A STORAGE
(OE = L, DIR = L)
INPUTS
OUTPUT
A
CLK
SEL
1B
2B
↑
H
X
L
↑
H
X
H
↑
L
L
X
L
↑
L
H
X
H
L§
H§
§ Two CLK edges are needed to propagate the
data. The data is loaded in the first register
when SEL is low and propagates to the
second register when SEL is high.
C-TO-D STORAGE
(OE = L)
OUTPUTS
INPUTS
SEL
CLK
C
1D
2D
H
X
X
L
↑
L
1D0†
L‡
2D0†
L
↑
H
H‡
H
† Output
level
before
indicated
steady-state input conditions were
established
‡ Two CLK edges are needed to propagate
the data.
L
OUTPUT ENABLE
INPUTS
CLK
OE
↑
↑
↑
OUTPUTS
DIR
A
H
X
Z
Z
Z
L
H
Z
Active
Active
L
L
Active
Z
Active
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1B, 2B
1D, 2D
• DALLAS, TEXAS 75265
3
SN74ALVCHG162280
16-BIT TO 32-BIT REGISTERED BUS EXCHANGER
WITH BYTE MASKS AND 3-STATE OUTPUTS
SCES093C – FEBRUARY 1997 – REVISED JUNE 1999
logic diagram, A and B ports (positive logic)
CLK
SEL
OE
39
40
42
CE
C1
DIR
41
1D
19
1 of 16 Channels
1B1
G1
CE
C1
A1
29
1
1D
C1
1D
1
CE
C1
C1
1D
1D
CE
C1
1D
4
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• DALLAS, TEXAS 75265
18
2B1
SN74ALVCHG162280
16-BIT TO 32-BIT REGISTERED BUS EXCHANGER
WITH BYTE MASKS AND 3-STATE OUTPUTS
SCES093C – FEBRUARY 1997 – REVISED JUNE 1999
logic diagram, C and D ports (positive logic)
CLK
SEL
OE
39
40
42
CE
C1
C1
27
1D
C1
1D
25
1D1
CE
C1
1D
24
2D1
CE
C1
C2
28
1D
C1
1D
23
1D2
CE
C1
1D
22
2D2
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Input voltage range, VI: Except I/O ports (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
I/O ports (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Package thermal impedance, θJA (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 4.6 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51.
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5
SN74ALVCHG162280
16-BIT TO 32-BIT REGISTERED BUS EXCHANGER
WITH BYTE MASKS AND 3-STATE OUTPUTS
SCES093C – FEBRUARY 1997 – REVISED JUNE 1999
recommended operating conditions (see Note 4)
MIN
MAX
3
3.6
VCC
VIH
Supply voltage
VIL
VI
Low-level input voltage
Input voltage
0
VO
Output voltage
0
High-level input voltage
IOH
High level output current
High-level
IOL
Low level output current
Low-level
∆t/∆v
Input transition rise or fall rate
VCC = 3 V to 3.6 V
VCC = 3 V to 3.6 V
A to B
B to A
A to B
B to A
2
UNIT
V
V
0.8
V
VCC
VCC
V
VCC = 3 V
VCC = 3 V
8
VCC = 3 V
VCC = 3 V
8
6
6
10
V
mA
mA
ns/V
TA
Operating free-air temperature
0
70
°C
NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VOH
VOL
A to B
TEST CONDITIONS
B to A
IOH = –6 mA
IOL = 100 µA
A to B
IOL = 8 mA
IOL = 6 mA
B to A
II
3V
3V
VI = VCC or GND
VI = 0.8 V
IOZ§
ICC
VO = VCC or GND
VI = VCC or GND,
∆ICC
One input at VCC – 0.6 V,
C port
Co
D port
Cio
A or B ports
TYP†
IO = 0
Other inputs at VCC or GND
MAX
UNIT
V
2
0.2
3V
0.8
3V
0.8
±5
3.6 V
VI = 2 V
VI = 0 to 3.6 V‡
Control inputs
MIN
VCC–0.2
2
3 V to 3.6 V
II(hold)
(
)
Ci
VCC
3 V to 3.6 V
IOH = –100 µA
IOH = –8 mA
3V
75
3V
–75
V
µA
µA
3.6 V
±500
3.6 V
±10
µA
3.6 V
40
µA
3 V to 3.6 V
750
µA
4
VI = VCC or GND
33V
3.3
VO = VCC or GND
VO = VCC or GND
3.3 V
7
3.3 V
8.5
8.5
pF
pF
pF
† All typical values are at VCC = 3.3 V, TA = 25°C.
‡ This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another.
§ For I/O ports, the parameter IOZ includes the input leakage current.
6
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SN74ALVCHG162280
16-BIT TO 32-BIT REGISTERED BUS EXCHANGER
WITH BYTE MASKS AND 3-STATE OUTPUTS
SCES093C – FEBRUARY 1997 – REVISED JUNE 1999
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 1)
VCC = 3.3 V
± 0.3 V
MIN
fclock
tw
tsu
th
Clock frequency
160
Pulse duration, CLK high or low
2.3
Setup time, high or low
Hold time, high or low
A data before CLK↑
1.4
B data before CLK↑
2
C data before CLK↑
1.3
DIR before CLK↑
2
SEL before CLK↑
2
A data after CLK↑
0.3
B data after CLK↑
0.3
C data after CLK↑
0.3
DIR after CLK↑
0.3
SEL after CLK↑
0.3
UNIT
MAX
MHz
ns
ns
ns
switching characteristics over recommended operating free-air temperature range,
CL = 25 pF (A port), 80 pF (B and D ports) (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
fmax
tpd
VCC = 3.3 V
± 0.3 V
MIN
160
CLK
CLK
ten
OE
CLK
tdis
OE
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UNIT
MAX
MHz
A
1.5
5
B
1.5
7.4
D
1.5
7.2
A
1.5
6.2
B
1.5
9.4
A
1.5
6
B
1.5
9.5
D
1.5
7.9
A
1.5
6.4
B
1.5
7.8
A
1.5
5
B
1.5
7.6
D
1.5
6.7
ns
ns
ns
7
SN74ALVCHG162280
16-BIT TO 32-BIT REGISTERED BUS EXCHANGER
WITH BYTE MASKS AND 3-STATE OUTPUTS
SCES093C – FEBRUARY 1997 – REVISED JUNE 1999
PARAMETER MEASUREMENT INFORMATION
6V
S1
500 Ω
From Output
Under Test
Open
GND
CL = 50 pF
(see Note A)
500 Ω
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
6V
GND
LOAD CIRCUIT
tw
2.7 V
2.7 V
Timing
Input
1.5 V
1.5 V
1.5 V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
1.5 V
Output
Control
(low-level
enabling)
2.7 V
1.5 V
1.5 V
0V
tPLH
Output
Waveform 1
S1 at 6 V
(see Note B)
tPLZ
VOH
1.5 V
3V
1.5 V
tPZH
tPHL
1.5 V
VOL
1.5 V
0V
tPZL
2.7 V
Output
VOLTAGE WAVEFORMS
PULSE DURATION
th
2.7 V
Data
Input
1.5 V
0V
0V
tsu
Input
1.5 V
Input
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.3 V
VOL
tPHZ
1.5 V
VOH
VOH – 0.3 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The output is measured with one input transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
8
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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
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Copyright  1999, Texas Instruments Incorporated