ETC PE4140

PRODUCT SPECIFICATION
PE4140
Ultra-High Linearity Broadband
Quad MOSFET Array
Product Description
The PE4140 is an ultra-high linearity, passive broadband
Quad MOSFET array with high dynamic range performance
capable of operation beyond 6.0 GHz. This quad array
operates with differential signals at all ports (RF, LO, IF),
allowing mixers to be built that use LO powers from -7 dBm
to +20 dBm. Typical applications range from frequency
up/down-conversion to phase detection for Cellular/PCS
Base Stations, Wireless Broadband Communications and
STB/Cable modems.
Features
• Ultimate Quad MOSFET array
• Ultra-high linearity, broadband
performance beyond 6.0 GHz
• Ideal for mixer applications
• Up/down conversion
• Low conversion loss
• High LO Isolation
• Packaged in small 3x3mm MLPM
The PE4140 is manufactured in Peregrine’s patented Ultra
Thin Silicon (UTSi) CMOS process, offering the
performance of GaAs with the economy and integration of
conventional CMOS.
Figure 1. Functional Schematic Diagram
Figure 2. Package Type
1
LO
2
IF
6
6-lead
MLPM
5
3 x 3 mm
3
4
RF
Table 1. AC and DC Electrical Specifications @ +25 °C
Symbol
Characteristics
1
FTYP
Operating Frequency Range
VDS
Drain-Source Voltage
VDS Match
Drain-Source Voltage Match
VT
Threshold Voltage
R DS
Drain-Source ‘ON’ Resistance
Min
Typ
Max
Units
DC
6.0
260
320
380
mV
12
40
mV
GHz
-100
6.5
7.75
Test Conditions
mV
9.5
Ω
VGS = +3V, IDS = 40 mA
VDS = 0.1V; per ASTM F617-00
VGS = +3V, IDS = 40 mA
Note 1: Typical untested operating frequency range of Quad MOSFET transistors.
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PE4140
Product Specification
Figure 3. Pin Configuration
IF1
1
RF1
2
Exposed
Solder Pad
(bottom side)
6
IF2
5
LO1
This MOSFET device has minimally protected
inputs and is highly susceptible to ESD damage.
When handling this UTSi device, observe the same
precautions that you would use with other ESDsensitive devices.
Latch-Up Avoidance
3
RF2
Electrostatic Discharge (ESD) Precautions
4
Unlike conventional CMOS devices, UTSi CMOS
devices are immune to latch-up.
LO2
Device Description
Table 2. Pin Descriptions
Pin
No.
Pin
Name
The PE4140 passive broadband Quad MOSFET
array is designed for use in up-conversion and
down-conversion applications for high performance
systems such as cellular infrastructure equipment
and STB/CATV systems.
Description
1
IF1
IF Output Connection (Drain)
2
RF1
RF Input Connection (Source)
3
RF2
RF Input Connection (Source)
4
LO2
LO Input Connection (Gate)
5
LO1
LO Input Connection (Gate)
6
IF2
IF Output Connection (Drain)
The PE4140 is an ideal mixer core for a wide range
of mixer products, including module level solutions
that incorporate baluns or other single-ended
matching structures enabling three-port operation.
Table 3. Absolute Maximum Ratings
Symbol
Parameter/Conditions
Min
Max
Units
TST
Storage temperature
range
-65
150
°C
TOP
Operating temperature
range
-40
85
°C
VDC + AC
Maximum DC plus peak
AC voltage across DrainSource
±3.3
V
VDC+AC
Maximum DC plus peak
AC voltage across GateDrain or Gate-Source
±4.2
V
ESD Sensitive Device
250
V
VESD
Copyright  Peregrine Semiconductor Corp. 2003
Page 2 of 8
The performance level of this passive mixer is
made possible by the very high linearity afforded by
Peregrine’s UTSi CMOS process.
Marking
Packaged devices are marked with part number
“4140”, date code and lot code.
File No. 70/0089~03B
| UTSi  CMOS RFIC SOLUTIONS
PE4140
Product Specification
Figure 4. Typical Schematic for a PCS Application
J3
LO Input
T1
M/A Com
ETC1.6-4-2-3
4
3
R2
1.2 nH
2
5
1
R12
1.2 nH
T2
M/A Com
ETC1.6-4-2-3
1
5
R3
2.7 nH
4
3
5 PE4140
6
2
2
1
3
R16
3 pF
J4
RF Input
4
R8
2.7 nH
2
3
4
1
5
T3
TOKO
617DB-1024
J6
IF Out
Table 4. Typical Performance in a PCS Application @ +25 °C
Parameter
Frequency Range**
LO
RF
IF
Minimum
Typical
Maximum
Units
1630
1700
--70
2130
2200
MHz
MHz
MHz
Conversion Loss**
(Includes balun losses)
8.5
dB
Isolation**
LO-RF
LO-IF
36
26
dB
dB
Input IP3**
32
dBm
Input 1 dB Compression**
22
dBm
** Data taken on an Evaluation Board narrow-band tuned to cover the PCS band, IF = 73MHz low-side, LO drive = 17dBm.
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PE4140
Product Specification
Typical Performance Plots in a PCS Application @ +25 °C (LO=17dBm, IF=73MHz Low-side)
Figure 5. IIP3 vs. Frequency
Figure 6. Conversion Loss vs. Frequency
40
10
Conversion Loss (dB) @ 17dBm Lo
IF=73Mhz Low-side
35
IIP3 (dBm) @ 17dBm Lo
30
25
20
15
10
9
8
Conversion Loss
7
6
5
0
1700
1750
1800
1850
1900
1950
2000
2050
2100
5
1700
1750
1800
Frequency (MHz)
1850
1900
1950
2000
2050
2100
Frequency (MHz)
Figure 7. LO-RF & LO-IF Isolation
0
-5
Isolation (dB)
-10
-15
-20
LO-IF
-25
LO-RF
-30
-35
-40
1700
1750
1800
1850
1900
1950
2000
2050
2100
Frequency (MHz)
Copyright  Peregrine Semiconductor Corp. 2003
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File No. 70/0089~03B
| UTSi  CMOS RFIC SOLUTIONS
PE4140
Product Specification
Figure 8. Typical Schematic for a CATV Application
(Reference Designators Refer to locations on Evaluation Board: 101/0090~00A)
4.7nH
L1
J3
LO Input
1
ETC1.6-4-2-3
T2
ETC1.6-4-2-3
4 T1
3
U1
4
5
6
2
5
1
1
3
2
1
3
2
5
J4
1
2
RF Input
MLP6-3X3
L2
4.7nH
R16
3.0pF
3
4
1
(Cut short between pads)
4
5
T3
ETC1-1-13
1
J6
IF Out
Note: L1 and L2 provide LO port matching for optimum performance. Typical gate capacitance is approximately 2.5 pF.
Table 5. Typical Performance in a CATV Application @ +25 °C
Parameter
Frequency Range**
LO
RF
IF
Minimum
Typical
Maximum
Units
1116
54
--1062
1926
864
MHz
MHz
MHz
Conversion Loss**
(Includes balun losses)
6.5
dB
Isolation**
LO-RF
LO-IF
40
28
dB
dB
Input IP3**
23
dBm
Input 1 dB Compression**
13
dBm
** Data taken on an Evaluation Board tuned for a broadband CATV application, IF = 1062MHz, RF drive = -5dBm, LO drive = 10dBm.
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PE4140
Product Specification
Typical Performance Plots in a CATV Application @ +25 °C
Figure 9. IIP3 vs. Frequency
Figure 10. Conversion Loss vs. Frequency
10
30
Conversion Loss (dB) @10dBm LO
IIP3 (dBm) @10dBm LO
25
20
15
10
5
0
8
6
4
2
0
0
200
400
600
800
1000
0
200
Frequency (MHz)
400
600
800
1000
Frequency (MHz)
Figure 11. LO-RF & LO-IF Isolation
0
-10
Isolation (dB)
-20
LO-IF
-30
-40
-50
-60
1000
LO-RF
1200
1400
1600
1800
2000
Frequency (MHz)
Copyright  Peregrine Semiconductor Corp. 2003
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File No. 70/0089~03B
| UTSi  CMOS RFIC SOLUTIONS
PE4140
Product Specification
Figure 12. Package Drawing
6-lead MLPM
-A-
3.00
6
5
-B-
CL
4
0.125
CL
3.00
PIN 1
MARK
0.10 C
4
1
2
3
0.10 C
4
0.125
10°+2°
-10°
DETAIL C
TOP VIEW
0.025
±0.025
0.100 C
0.70 ± 0.05
0.90 ±0.10
0.080 C
3
0.20 ±0.05
SEATING
PLANE
SIDE VIEW
0.025±0.025
SEE DETAIL B
0.95
EXPOSED PAD
1
CL
0.35 +0.08
-0.02
0.10
0.05
C
0.17 MIN.
SEE DETAIL A
0.24 +0.20
-0.08
C A B
0.29 +0.16
-0.09
3
2
DETAIL B
-C-
0.17
0.30
R0.127 TYP
R 0.15 TYP
1.21 ±0.10
0.605 ±0.05
EXPOSED
(2X)
0.125
EXPOSED SLUG/
HEAT SINK
6
3
4
5
THIS FEATURE
APPLIES TO
BOTH ENDS OF
THE PKG.
0.20 MIN.
EXPOSED METALIZED
FEATURE
DETAIL A
EDGE OF PLASTIC BODY
1.05±0.05
2.01±0.10
BOTTOM VIEW
1. DIMENSIONS AND TOLERANCES ARE PER ANSi Y14.5
2. DIMENSIONS ARE IN MILLIMETERS, ANGLES ARE IN DEGREES.
3
COPLANARITY APPLIES TO EXPOSED HEAT SLUG AS WELL AS THE TERMINALS.
4
PROFILE TOLERANCE APPLIES TO PLASTIC BODY ONLY.
Table 6. Ordering Information
Order
Code
Part Marking
Description
Package
Shipping
Method
PE4140-01
4140
PE4140-06MLP3x3-12800F
6-lead 3x3 MLPM
12800 units / Canister
PE4140-02
4140
PE4140-06MLP3x3-3000C
6-lead 3x3 MLPM
3000 units / T&R
PE4140-00
PE4140-EK
PE4140-06MLP3x3-EK
Evaluation Kit
1 / box
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Copyright  Peregrine Semiconductor Corp. 2003
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PE4140
Product Specification
Sales Offices
United States
Japan
Peregrine Semiconductor Corp.
Peregrine Semiconductor K.K.
6175 Nancy Ridge Drive
San Diego, CA 92121
Tel 1-858-455-0660
Fax 1-858-455-0770
5A-5, 5F Imperial Tower
1-1-1 Uchisaiwaicho, Chiyoda-ku
Tokyo 100-0011 Japan
Tel: 03-3507-5755
Fax: 03-3507-5601
Europe
Peregrine Semiconductor Europe
Bâtiment Maine
13-15 rue des Quatre Vents
F- 92380 Garches
Tel 33-1-47-41-91-73
Fax 33-1-47-41-91-73
For a list of representatives in your area, please refer to our Web site at: http://www.peregrine-semi.com
Data Sheet Identification
Advance Information
The information in this data sheet is believed to be reliable. However,
The product is in a formative or design stage. The data sheet
contains design target specifications for product
development. Specifications and features may change in any
manner without notice.
Preliminary Specification
Peregrine assumes no liability for the use of this information. Use
shall be entirely at the user’s own risk.
No patent rights or licenses to any circuits described in this
data sheet are implied or granted to any third party.
Peregrine’s products are not designed or intended for use in devices
The data sheet contains preliminary data. Additional data
may be added at a later date. Peregrine reserves the right to
change specifications at any time without notice in order to
supply the best possible product.
or systems intended for surgical implant, or in other applications
intended to support or sustain life, or in any application in which the
failure of the Peregrine product could create a situation in which
personal injury or death might occur. Peregrine assumes no liability
for damages, including consequential or incidental damages, arising
Product Specification
out of the use of its products in such applications.
The data sheet contains final data. In the event Peregrine
decides to change the specifications, Peregrine will notify
customers of the intended changes by issuing a PCN
(Product Change Notice).
Peregrine products are protected under one or more of the following
U.S. patents: 6,090,648; 6,057,555; 5,973,382; 5,973,363; 5,930,638;
5,920,233; 5,895,957; 5,883,396; 5,864,162; 5,863,823; 5,861,336;
5,663,570; 5,610,790; 5,600,169; 5,596,205; 5,572,040; 5,492,857;
5,416,043. Other patents are pending.
Peregrine, the Peregrine logotype, Peregrine Semiconductor Corp.,
and UTSi are registered trademarks of Peregrine Semiconductor Corporation.
Copyright © 2003 Peregrine Semiconductor Corp. All rights reserved.
Copyright  Peregrine Semiconductor Corp. 2003
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File No. 70/0089~03B
| UTSi  CMOS RFIC SOLUTIONS