19-3279; Rev 5; 3/11 KIT ATION EVALU E L B AVAILA Low-Voltage DDR Linear Regulators Features The MAX1510/MAX17510 DDR linear regulators source and sink up to 3A peak (typ) using internal n-channel MOSFETs. These linear regulators deliver an accurate 0.5V to 1.5V output from a low-voltage power input (VIN = 1.1V to 3.6V). The MAX1510/MAX17510 use a separate 3.3V bias supply to power the control circuitry and drive the internal n-channel MOSFETs. The MAX1510/MAX17510 provide current and thermal limits to prevent damage to the linear regulator. Additionally, the MAX1510/MAX17510 generate a power-good (PGOOD) signal to indicate that the output is in regulation. During startup, PGOOD remains low until the output is in regulation for 2ms (typ). The internal soft-start limits the input surge current. The MAX1510/MAX17510 power the active-DDR termination bus that requires a tracking input reference. The MAX1510/MAX17510 can also be used in low-power chipsets and graphics processor cores that require dynamically adjustable output voltages. The MAX1510/MAX17510 are available in a 10-pin, 3mm x 3mm thin DFN package. o Internal Power MOSFETs with Current Limit (3A typ) o Fast Load-Transient Response o External Reference Input with Reference Output Buffer o 1.1V to 3.6V Power Input o ±15mV (max) Load-Regulation Error o Thermal-Fault Protection o Shutdown Input o Power-Good Window Comparator with 2ms (typ) Delay o Small, Low-Profile 10-Pin, 3mm x 3mm TDFN Package o Ceramic or Polymer Output Capacitors Ordering Information TEMP RANGE PINPACKAGE TOP MARK -40°C to +85°C 10 TDFN-EP* ARD MAX1510ETB+ -40°C to +85°C 10 TDFN-EP* ABD MAX1510ATB/V+ -40°C to +85°C 10 TDFN-EP* AWD MAX17510ATB+ -40°C to +125°C 10 TDFN-EP* AWQ DDR Memory Termination MAX17510ATB/V+ -40°C to +125°C 10 TDFN-EP* AWQ Active Termination Buses +Denotes a lead(Pb)-free and RoHS-compliant package. *EP = Exposed pad. /V denotes an automotive qualified part. Applications Notebook/Desktop Computers Graphics Processor Core Supplies PART MAX1510ETB Chipset/RAM Supplies as Low as 0.5V Typical Operating Circuit Pin Configuration VIN (1.1V TO 3.6V) IN OUT PGND SHDN OUTS TOP VIEW 10 9 8 7 6 IN MAX1510 MAX17510 3 4 5 REFOUT VCC AGND REFIN PGOOD + 2 TDFN 3mm x 3mm VOUT = VTT OUTS MAX1510 MAX17510 VBIAS (2.7V TO 3.6V) 1 OUT VCC PGND SHDN AGND PGOOD VDDQ (2.5V OR 1.8V) VREFOUT = VTTR REFIN REFOUT A "+" SIGN WILL REPLACE THE FIRST PIN INDICATOR ON LEAD-FREE PACKAGES. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX1510/MAX17510 General Description MAX1510/MAX17510 Low-Voltage DDR Linear Regulators ABSOLUTE MAXIMUM RATINGS IN to PGND............................................................-0.3V to +4.3V OUT to PGND ..............................................-0.3V to (VIN + 0.3V) OUTS to AGND ............................................-0.3V to (VIN + 0.3V) VCC to AGND.........................................................-0.3V to +4.3V REFIN, REFOUT, SHDN, PGOOD to AGND ..-0.3V to (VCC + 0.3V) PGND to AGND .....................................................-0.3V to +0.3V REFOUT Short Circuit to AGND .................................Continuous OUT Continuous RMS Current: 100s ..................................±1.6A 1s......................................±2.5A Continuous Power Dissipation (TA = +70°C) 10-Pin 3mm x 3mm Thin DFN (derated 24.4mW/°C above +70°C)...........................1951mW Operating Temperature Range MAX1510ETB...................................................-40°C to +85°C MAX17510ATB ..............................................-40°C to +125°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Soldering Temperature (reflow) Lead(Pb)-free packages..............................................+260°C Packages containing lead(Pb).....................................+240°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VIN = 1.8V, VCC = 3.3V, VREFIN = VOUTS = 1.25V, SHDN = VCC, circuit of Figure 1, TJ = TA = -40°C to +85°C for MAX1510ETB, TJ = TA = -40°C to +125°C for MAX17510ATB, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS VIN Power input 1.1 3.6 VCC Bias supply 2.7 3.6 Quiescent Supply Current (VCC) ICC Load = 0, VREFIN > 0.45V 0.7 Shutdown Supply Current (VCC) ICC(SHDN) SHDN = GND, VREFIN > 0.45V 350 600 SHDN = GND, REFIN = GND 50 100 Quiescent Supply Current (VIN) IIN Load = 0 0.4 10 mA Shutdown Supply Current (VIN) IIN(SHDN) 0.1 10 µA 0 +4 Input-Voltage Range Feedback-Voltage Error VOUTS SHDN = GND REFIN to OUTS IOUT = ±200mA TA = +25°C -4 TA = -40°C to +125°C -6 Load-Regulation Error -1A ≤ IOUT ≤ +1A Line-Regulation Error 1.4V ≤ VIN ≤ 3.3V, IOUT = ±100mA OUTS Input-Bias Current IOUTS 1.3 +6 -15 +15 1 V mA µA mV mV mV -1 +1 µA 0.5 1.5 V OUTPUT Output Adjust Range OUT On-Resistance Output Current Slew Rate OUT Power-Supply Rejection Ratio PSRR OUT-to-OUTS Resistance ROUTS Discharge MOSFET On-Resistance 2 High-side MOSFET (source) (IOUT = 0.1A) 0.14 0.25 Low-side MOSFET (sink) (IOUT = -0.1A) 0.14 0.25 Ω COUT = 100µF, IOUT = 0.1A to 2A 3 A/µs 10Hz < f < 10kHz, IOUT = 200mA, COUT = 100µF 80 dB 12 kΩ 8 Ω RDISCHARGE SHDN = GND _______________________________________________________________________________________ Low-Voltage DDR Linear Regulators (VIN = 1.8V, VCC = 3.3V, VREFIN = VOUTS = 1.25V, SHDN = VCC, circuit of Figure 1, TJ = TA = -40°C to +85°C for MAX1510ETB, TJ = TA = -40°C to +125°C for MAX17510ATB, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS REFERENCE REFIN Voltage Range VREFIN REFIN Input-Bias Current IREFIN REFIN Undervoltage-Lockout Voltage REFOUT Voltage 0.5 1.5 V -1 +1 µA 0.35 0.45 V VREFIN VREFIN + 0.01 V +20 mV Rising edge, hysteresis = 50mV VREFOUT REFOUT Load Regulation TA = +25°C ΔVREFOUT VCC = 3.3V, IREFOUT = 0V IREFOUT = ±5mA VREFIN - 0.01 -20 FAULT DETECTION Thermal-Shutdown Threshold TSHDN Rising edge, hysteresis = 15°C VCC Undervoltage-Lockout Threshold VUVLO Rising edge, hysteresis = 100mV IN Undervoltage-Lockout Threshold Current-Limit Threshold Soft-Start Current-Limit Time +165 2.45 Rising edge, hysteresis = 55mV ILIMIT °C 2.55 2.65 V 0.9 1.1 V TA = -40°C to +85°C 1.8 3 4.2 TA = -40°C to +125°C 1.5 3 4.2 tSS 200 A µs INPUTS AND OUTPUTS PGOOD Lower Trip Threshold With respect to feedback threshold, hysteresis = 12mV -200 -150 -100 mV PGOOD Upper Trip Threshold With respect to feedback threshold, hysteresis = 12mV 100 150 200 mV OUTS forced 25mV beyond PGOOD trip threshold 5 10 35 µs PGOOD Startup Delay Startup rising edge, OUTS within ±100mV of the feedback threshold 1 2 3.5 ms PGOOD Output Low Voltage ISINK = 4mA 0.3 V 1 µA 2.0 V +1 µA PGOOD Propagation Delay PGOOD Leakage Current SHDN Logic Input Threshold SHDN Logic Input Current tPGOOD IPGOOD OUTS = REFIN (PGOOD high impedance), PGOOD = VCC + 0.3V, TA = +25°C Logic-high Logic-low 0.8 SHDN = VCC or GND, TA = +25°C -1 V Note 1: Limits are 100% production tested at TA = +25°C. Limits over the operating temperature range are guaranteed through correlation using statistical-quality-control (SQC) methods. _______________________________________________________________________________________ 3 MAX1510/MAX17510 ELECTRICAL CHARACTERISTICS (continued) Typical Operating Characteristics (Circuit of Figure 1. TA = +25°C, unless otherwise noted.) 1.275 0.90 VIN = 1.8V 1.250 0.88 1.225 VIN = 1.2V 0.86 0.84 -2 -1 0 1 2 3 0 -3 -2 -1 0 1 2 1.0 3 1.5 2.0 2.5 3.0 BIAS CURRENT (ICC) vs. LOAD CURRENT (IOUT) 0.9 0.8 VOUT = 1.25V 0.7 0.6 VIN = 1.5V 1.2 1.0 ICC (mA) ICC (mA) 1.4 MAX1510/MAX17510 toc05 MAX1510/MAX17510 toc04 1.0 0.5 0.4 100 0.3 INPUT UVLO 0 1.0 1.5 2.0 2.5 3.0 0 3.5 VOUT = 0.90V 0.6 ENTERING DROPOUT 0.2 0.1 0 VOUT = 1.25V 0.8 0.4 DROPOUT 0.2 50 0.5 1.0 1.5 0 2.0 2.5 3.0 -2 3.5 -1 0 IOUT (A) POWER GROUND CURRENT (IPGND) vs. SOURCE LOAD CURRENT (IOUT) INPUT CURRENT (IIN) vs. SINK LOAD CURRENT (IOUT) DROPOUT VOLTAGE vs. OUTPUT CURRENT ENTERING DROPOUT VOUT = 1.25V 5 4 VOUT = 0.90V 3 VOUT = 1.25V 2 VOUT = 0.90V 0 0.5 1.0 IOUT (A) 1.5 2.0 0.5 VOUT = 1.25V 0.4 0.3 0.2 VOUT = 0.9V 0.1 1 0 0.6 MAX1510/MAX17510 toc09 6 IIN (mA) 0.15 VIN = 1.5V DROPOUT VOLTAGE (V) MAX1510/MAX17510 toc07 0.20 7 MAX1510/MAX17510 toc08 VIN (V) VIN = 1.5V 2 1 VIN (V) 0.25 0 DROPOUT VOLTAGE LIMITED 0.5 BIAS CURRENT (ICC) vs. INPUT VOLTAGE (VIN) VOUT = 0.90V 0.05 THERMALLY LIMITED 1.0 INPUT CURRENT (IIN) vs. INPUT VOLTAGE (VIN) 150 0.10 1.5 INPUT VOLTAGE (V) 200 0.5 2.0 IOUT (A) VOUT = 1.25V 0 VOUT = 1.25V 2.5 IOUT (A) 250 4 VOUT = 0.9V 1.200 -3 IIN (μA) VIN = 1.5V 3.0 MAX1510/MAX17510 toc06 VOUT (V) VIN = 1.5V VREFIN = 1.25V MAXIMUM OUTPUT CURRENT (A) 0.92 MAX1510/MAX17510 toc02 VREFIN = 0.9V 0.94 VOUT (V) 1.300 MAX1510/MAX17510 toc01 0.96 MAXIMUM OUTPUT CURRENT vs. INPUT VOLTAGE OUTPUT LOAD REGULATION MAX1510/MAX17510 toc03 OUTPUT LOAD REGULATION IPGND (mA) MAX1510/MAX17510 Low-Voltage DDR Linear Regulators 0 -2.0 -1.5 -1.0 IOUT (A) -0.5 0.0 0 0.5 1.0 1.5 2.0 OUTPUT CURRENT (A) _______________________________________________________________________________________ 2.5 3.0 Low-Voltage DDR Linear Regulators REFOUT VOLTAGE ERROR vs. REFOUT LOAD CURRENT STARTUP WAVEFORM MAX1510/MAX17510 toc10 15 REFOUT VOLTAGE ERROR (mV) SHUTDOWN WAVEFORM MAX1510/MAX17510 toc11 20 10 MAX1510/MAX17510 toc12 5V SHDN 0V RLOAD = 100Ω 5V SHDN 0V 2V 1.25V 5 0 -5 VOUT 0V 1V VOUT 0V 4V 4V -10 PGOOD PGOOD -15 0V 0V -20 -10 -5 0 5 500μs/div 10 100μs/div REFOUT LOAD CURRENT (mA) SOURCE/SINK LOAD TRANSIENT SOURCE LOAD TRANSIENT MAX1510/MAX17510 toc14 MAX1510/MAX17510 toc13 VOUT AC-COUPLED 5mV/div VOUT AC-COUPLED 1mV/div 1A +1.5A IOUT IOUT -1.5A 0A 4.00μs/div 20.0μs/div LINE TRANSIENT DYNAMIC OUTPUT-VOLTAGE TRANSIENT MAX1510/MAX17510 toc15 MAX1510/MAX17510 toc16 VIN = 1.5V 3.3V 2.5V VDDQ 1.8V VIN (1V/div) 1.5V 1.2V VREFOUT VOUT (10mV/div) AC-COUPLED 0.9V 0.9V 1.2V VOUT 0.9V IOUT = 100mA 40μs/div 20.0μs/div _______________________________________________________________________________________ 5 MAX1510/MAX17510 Typical Operating Characteristics (continued) (Circuit of Figure 1. TA = +25°C, unless otherwise noted.) Typical Operating Characteristics (continued) (Circuit of Figure 1. TA = +25°C, unless otherwise noted.) 50 SAMPLE SIZE = 200 VDDQ 1.8V 1.2V VREFOUT 0.9V 1.2V SAMPLE PERCENTAGE (%) 2.5V VOUT +25°C +85°C 40 50 MAX1510/MAX17510 toc18 VIN = 1.8V SAMPLE SIZE = 200 SAMPLE PERCENTAGE (%) MAX1510/MAX17510 toc17 SOURCE CURRENT-LIMIT DISTRIBUTION 30 20 10 +25°C +85°C 40 MAX1510/MAX17510 toc19 SINK CURRENT-LIMIT DISTRIBUTION DYNAMIC OUTPUT-VOLTAGE TRANSIENT 30 20 10 0.9V 0 0 -3.0 -2.0 -2.5 2.0 2.5 SINK CURRENT LIMIT (A) 3.90 3.60 3.30 3.00 2.70 -2.20 -2.00 -2.40 -2.60 -3.00 -2.80 -3.20 -3.40 -3.60 0 -3.80 0 2.40 20 10 SINK LOAD REGULATION DISTRIBUTION IOUT = -1A, TA = +125°C SINK CURRENT-LIMIT DISTRIBUTION TA = +125°C 30 20 10 50 SAMPLE PERCENTAGE (%) SAMPLE SIZE = 200 MAX1510/MAX17510 toc20 SOURCE CURRENT LIMIT (A) MAX1510/MAX17510 toc22 SINK CURRENT LIMIT (A) 40 SAMPLE SIZE = 200 40 30 20 SINK LOAD REGULATION (mV) 10 11 0 -2.00 9 -2.20 8 -2.40 7 -2.60 6 -3.00 5 -2.80 4 -3.20 3 -3.40 2 -3.60 1 -3.80 10 -4.00 0 MAX1510/MAX17510 toc21 30 10 50 6 40 2.10 20 SAMPLE SIZE = 200 1.80 30 SOURCE CURRENT-LIMIT DISTRIBUTION TA = +125°C 1.50 40 50 SAMPLE PERCENTAGE (%) MAX1510/MAX17510 toc20 SAMPLE SIZE = 200 -4.00 SAMPLE PERCENTAGE (%) 50 SINK CURRENT-LIMIT DISTRIBUTION TA = +125°C 3.0 3.5 SOURCE CURRENT LIMIT (A) 4.50 -3.5 4.20 -4.0 20.0μs/div SAMPLE PERCENTAGE (%) MAX1510/MAX17510 Low-Voltage DDR Linear Regulators SINK CURRENT LIMIT (A) _______________________________________________________________________________________ 4.0 Low-Voltage DDR Linear Regulators PIN NAME FUNCTION 1 REFOUT 2 VCC 3 AGND Analog Ground. Connect the backside pad to AGND. 4 REFIN External Reference Input. REFIN sets the output regulation voltage (VOUTS = VREFIN). 5 PGOOD 6 OUTS Output Sense Input. The OUTS regulation level is set by the voltage at REFIN. Connect OUTS to the remote DDR termination bypass capacitors. OUTS is internally connected to OUT through a 12kΩ resistor. 7 SHDN Shutdown Control Input. Connect to VCC for normal operation. Connect to analog ground to shut down the linear regulator. The reference buffer remains active in shutdown. 8 PGND Power Ground. Internally connected to the output sink MOSFET. Buffered Reference Output. The output of the unity-gain reference input buffer sources and sinks over 5mA. Bypass REFOUT to AGND with a 0.33µF or greater ceramic capacitor. Analog Supply Input. Connect to the system supply voltage (+3.3V). Bypass VCC to AGND with a 1µF or greater ceramic capacitor. Open-Drain Power-Good Output. PGOOD is low when the output voltage is more than 150mV (typ) above or below the regulation point, during soft-start, and when shut down. 2ms after the output reaches the regulation voltage during startup, PGOOD becomes high impedance. 9 OUT 10 IN Power Input. Internally connected to the output source MOSFET. Output of the Linear Regulator — EP Exposed Pad. Internally connected to AGND. Connect EP to AGND PCB ground plane to maximize thermal performance. Not intended as an electrical connection point. Detailed Description The MAX1510/MAX17510 are low-voltage, low-dropout DDR termination linear regulators with an external bias supply input and a buffered reference output (see Figures 1 and 2). VCC is powered by a 2.7V to 3.6V supply that is commonly available in laptop and desktop computers. The 3.3V bias supply drives the gate of the internal pass transistor, while a lower voltage input at the drain of the transistor (IN) is regulated to provide VOUT. By using separate bias and power inputs, the MAX1510/MAX17510 can drive an n-channel high-side MOSFET and use a lower input voltage to provide better efficiency. The MAX1510/MAX17510 regulate their output voltage to the voltage at REFIN. When used in DDR applications as a termination supply, the MAX1510/MAX17510 deliver 1.25V or 0.9V at 3A peak (typ) from an input voltage of 1.1V to 3.6V. The MAX1510/MAX17510 sink up to 3A peak (typ) as required in a termination supply. The MAX1510/MAX17510 provide shoot-through protection, ensuring that the source and sink MOSFETs do not conduct at the same time, yet produce a fast source-to-sink load transient. VOUT = VTT = VDDQ/2 VIN = 1.1V TO 3.6V IN OUT COUT1 100μF CIN2 10μF MAX1510 MAX17510 3.3V BIAS SUPPLY VCC R3 100kΩ C1 1.0μF PGND AGND POWER-GOOD PGOOD OUTS ON OFF SHDN R1 10kΩ VDDQ REFIN R2 10kΩ CREFIN 1000pF REFOUT VREFOUT = VTTR CREFOUT 0.33μF Figure 1. Standard Application Circuit _______________________________________________________________________________________ 7 MAX1510/MAX17510 Pin Description MAX1510/MAX17510 Low-Voltage DDR Linear Regulators 3.3V BIAS SUPPLY VCC IN EN UVLO OFF ON INPUT 1.1V TO 3.6V SOFTSTART SHDN THERMAL SHDN REFIN VDDQ OUT Gm PGND VTTR 12kΩ REFOUT OUTS AGND REFIN +150mV EN 8Ω REFIN -150mV POWERGOOD PGOOD MAX1510 MAX17510 DELAY LOGIC Figure 2. Functional Diagram 8 _______________________________________________________________________________________ VTT Low-Voltage DDR Linear Regulators 3.3V Bias Supply (VCC) The VCC input powers the control circuitry and provides the gate drive to the pass transistor. This improves efficiency by allowing VIN to be powered from a lower supply voltage. Power V CC from a well-regulated 3.3V supply. Current drawn from the VCC supply remains relatively constant with variations in VIN and load current. Bypass VCC with a 1µF or greater ceramic capacitor as close to the device as possible. VCC Undervoltage Lockout (UVLO) The VCC input undervoltage-lockout (UVLO) circuitry ensures that the regulator starts up with adequate voltage for the gate-drive circuitry to bias the internal pass transistor. The UVLO threshold is 2.55V (typ). VCC must remain above this level for proper operation. Power-Supply Input (IN) IN provides the source current for the linear regulator’s output, OUT. IN connects to the drain of the internal nchannel power MOSFET. IN can be as low as 1.1V, minimizing power dissipation. The input UVLO prohibits operation below 0.8V (typ). Bypass IN with a 10µF or greater capacitor as close to the device as possible. Reference Input (REFIN) The MAX1510/MAX17510 regulate OUTS to the voltage set at REFIN, making the MAX1510/MAX17510 ideal for memory applications where the termination supply must track the supply voltage. Typically, REFIN is set by an external resistive voltage-divider connected to the memory supply (VDDQ) as shown in Figure 1. The maximum output voltage of 1.5V is limited by the gate-drive voltage of the internal n-channel power transistor. Buffered Reference Output (REFOUT) REFOUT is a unity-gain transconductance amplifier that generates the DDR reference supply. It sources and sinks greater than 5mA. The reference buffer is typically connected to ceramic bypass capacitors (0.33µF to 1.0µF). REFOUT is active when VREFIN > 0.45V and V CC is above V UVLO . REFOUT is independent of SHDN. Shutdown Drive SHDN low to disable the error amplifier, gatedrive circuitry, and pass transistor (Figure 2). In shutdown, OUT is terminated to GND with an 8Ω MOSFET. REFOUT is independent of SHDN. Connect SHDN to VCC for normal operation. Current Limit The MAX1510/MAX17510 feature source and sink current limits to protect the internal n-channel MOSFETs. The source and sink MOSFETs have a typical 3A current limit (1.8A min). This current limit prevents damage to the internal power transistors, but the device can enter thermal shutdown if the power dissipation increases the die temperature above +165°C (see the Thermal-Overload Protection section). Soft-Start Current Limit Soft-start gradually increases the internal source current limit to reduce input surge currents at startup. Fullsource current limit is available after the 200µs soft-start timer has expired. The soft-start current limit is given by: I × t ILIMIT(SS) = LIMIT t SS where I LIMIT and t SS are from the Electrical Characteristics. Thermal-Overload Protection Thermal-overload protection prevents the linear regulator from overheating. When the junction temperature exceeds +165°C, the linear regulator and reference buffer are disabled, allowing the device to cool. Normal operation resumes once the junction temperature cools by 15°C. Continuous short-circuit conditions result in a pulsed output until the overload is removed. A continuous thermal-overload condition results in a pulsed output. For continuous operation, do not exceed the absolute maximum junction-temperature rating of +150°C. _______________________________________________________________________________________ 9 MAX1510/MAX17510 The MAX1510/MAX17510 feature an open-drain PGOOD output that transitions high 2ms after the output initially reaches regulation. PGOOD goes low within 10µs of when the output goes out of regulation by ±150mV. The MAX1510/MAX17510 feature current- and thermal-limiting circuitry to prevent damage during fault conditions. MAX1510/MAX17510 Low-Voltage DDR Linear Regulators SHDN 200μs CURRENT LIMIT OUTPUT OVERLOAD CONDITION POWER-GOOD WINDOW OUT 2ms STARTUP DELAY PGOOD 10μs PROPAGATION DELAY 10μs PROPAGATION DELAY Figure 3. MAX1510/MAX17510 PGOOD and Soft-Start Waveforms Power-Good (PGOOD) The MAX1510/MAX17510 provide an open-drain PGOOD output that goes high 2ms (typ) after the output initially reaches regulation during startup as shown in Figure 3. PGOOD transitions low 10µs after the output goes out of regulation by ±150mV, or when the device enters shutdown. Connect a pullup resistor from PGOOD to VCC for a logic-level output. Use a 100kΩ resistor to minimize current consumption. REFERENCE VOLTAGE (VREF) R1 Applications Information REFIN Dynamic Output-Voltage Transitions By changing the voltage at REFIN, the MAX1510/ MAX17510 can be used in applications that require dynamic output-voltage changes between two set points (graphics processors). Figure 4 shows a dynamically adjustable resistive voltage-divider network at REFIN. Using an external signal MOSFET, a resistor can be switched in and out of the REFIN resistordivider, changing the voltage at REFIN. The two output voltages are determined by the following equations: R2 VOUT(LOW) VOUT(HIGH) VOUT(LOW) = VREF ⎛ R2 ⎞ VOUT(LOW) = VREF ⎜ ⎟ ⎝ R1 + R2 ⎠ ⎡ (R2 + R3) ⎤ VOUT(HIGH) = VREF ⎢ ⎥ ⎢⎣ R1 + (R2 + R3) ⎥⎦ 10 MAX1510 MAX17510 CREFIN R3 ( ) VOUT(HIGH) = VREF R2 R1 + R2 (R2 + R3) R1 + (R2 + R3) Figure 4. Dynamic Output-Voltage Change ______________________________________________________________________________________ Low-Voltage DDR Linear Regulators PDIS(MAX) = TJ(MAX) - TA θJC + θCA where TJ(MAX) is the maximum junction temperature (+150°C), TA is the ambient temperature, θJC is the thermal resistance from the die junction to the package case, and θCA is the thermal resistance from the case through the PCB, copper traces, and other materials to the surrounding air. For optimum power dissipation, use a large ground plane with good thermal contact to the backside pad, and use wide input and output traces. When 1 square inch of copper is connected to the device, the maximum allowable power dissipation of a 10-pin DFN package is 1951mW. The maximum power dissipation is derated by 24.4mW/°C above TA = +70°C. Extra copper on the PCB increases thermal mass and reduces thermal resistance of the board. Refer to the MAX1510 evaluation kit for a layout example. The MAX1510/MAX17510 deliver up to 3A and operates with input voltages up to 3.6V, but not simultaneously. High output currents can only be achieved when the input-output differential voltages are low (Figure 5). Dropout Operation A regulator’s minimum input-to-output voltage differential (dropout voltage) determines the lowest usable supply voltage. Because the MAX1510/MAX17510 use an n-channel pass transistor, the dropout voltage is a function of the drain-to-source on-resistance (RDS(ON) = 0.25Ω max) multiplied by the load current (see the Typical Operating Characteristics): MAXIMUM OUTPUT CURRENT (A) Operating Region and Power Dissipation The maximum power dissipation of the MAX1510/ MAX17510 depends on the thermal resistance of the 10pin TDFN package and the circuit board, the temperature difference between the die and ambient air, and the rate of airflow. The power dissipated in the device is: PSRC = ISRC x (VIN – VOUT) PSINK = ISINK x VOUT The resulting maximum power dissipation is: SAFE OPERATING REGION 3.5 DROPOUT VOLTAGE LIMITED MAXIMUM CURRENT LIMIT 3.0 1s RMS LIMIT 2.5 TA = 0°C TO +70°C 2.0 100s RMS LIMIT 1.5 VIN(MAX) - VOUT(MIN) 1.0 0.5 TA = +100°C 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 INPUT-OUTPUT DIFFERENTIAL VOLTAGE (V) Figure 5. Power Operating Region—Maximum Output Current vs. Input-Output Differential Voltage VDROPOUT = RDS(ON) x IOUT For low output-voltage applications, the sink current is limited by the output voltage and the RDS(ON) of the MOSFET. Input Capacitor Selection Bypass IN to PGND with a 10µF or greater ceramic capacitor. Bypass VCC to AGND with a 1µF ceramic capacitor for normal operation in most applications. Typically, the LDO is powered from the output of a step-down controller (memory supply) that has additional bulk capacitance (polymer or tantalum) and distributed ceramic capacitors. Output Capacitor Selection The MAX1510/MAX17510 output stability is independent of the output capacitance for COUT from 10µF to 220µF. Capacitor ESR between 2mΩ and 50mΩ is needed to maintain stability. Within the recommended capacitance and ESR limits, the output capacitor should be chosen to provide good transient response: ΔIOUT(P-P) x ESR = ΔVOUT(P-P) where ΔIOUT(P-P) is the maximum peak-to-peak loadcurrent step (typically equal to the maximum source load plus the maximum sink load), and ΔVOUT(P-P) is the allowable peak-to-peak voltage tolerance. Using larger output capacitance can improve efficiency in applications where the source and sink currents change rapidly. The capacitor acts as a reservoir for the rapid source and sink currents, so no extra current is supplied by the MAX1510/MAX17510 or discharged to ground, improving efficiency. ______________________________________________________________________________________ 11 MAX1510/MAX17510 For a step voltage change at REFIN, the rate of change of the output voltage is limited by the total output capacitance, the current limit, and the load during the transition. Adding a capacitor across REFIN and AGND filters noise and controls the rate of change of the REFIN voltage during dynamic transitions. With the additional capacitance, the REFIN voltage slews between the two set points with a time constant given by REQ x CREFIN, where REQ is the equivalent parallel resistance seen by the slew capacitor. MAX1510/MAX17510 Low-Voltage DDR Linear Regulators Noise, PSRR, and Transient Response PCB Layout Guidelines The MAX1510/MAX17510 operate with low-dropout voltage and low quiescent current in notebook computers while maintaining good noise, transient response, and AC rejection specifications. Improved supply-noise rejection and transient response can be achieved by increasing the values of the input and output capacitors. Use passive filtering techniques when operating from noisy sources. The MAX1510/MAX17510 load-transient response graphs (see the Typical Operating Characteristics) show two components of the output response: a DC shift from the output impedance due to the load-current change and the transient response. A typical transient response for a step change in the load current from -1.5A to +1.5A is 10mV. Increasing the output capacitor’s value and decreasing the ESR attenuate the overshoot. The MAX1510/MAX17510 require proper layout to achieve the intended output power level and low noise. Proper layout involves the use of a ground plane, appropriate component placement, and correct routing of traces using appropriate trace widths. Refer to the MAX1510 evaluation kit for a layout example: • Minimize high-current ground loops. Connect the ground of the device, the input capacitor, and the output capacitor together at one point. • To optimize performance, a ground plane is essential. Use all available copper layers in applications where the device is located on a multilayer board. • Connect the input filter capacitor less than 10mm from IN. The connecting copper trace carries large currents and must be at least 2mm wide, preferably 5mm wide. • Connect the backside pad to a large ground plane. Use as much copper as necessary to decrease the thermal resistance of the device. In general, more copper provides better heatsinking capabilities. Chip Information PROCESS: BiCMOS Package Information For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. 12 PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO. 10 TDFN T1033+1 21-0137 90-0003 ______________________________________________________________________________________ Low-Voltage DDR Linear Regulators REVISION NUMBER REVISION DATE 0 5/04 Initial release 1 1/05 Raised Absolute Maximum rating 2 8/05 Added MAX1510ETB 3 4/09 Added automotive-qualified part MAX1510ETB/V+ 4 7/09 Added MAX17510 to data sheet; added temperature grades for MAX1510ATB+ and MAX1510ATB/V+; minor edits 5 3/11 Added MAX17510 automotive qualified part DESCRIPTION PAGES CHANGED — 1, 14 1 1, 2, 7, 12, 13 1, 2, 3, 6, 7, 12, 13 1 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 13 © 2011 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc. MAX1510/MAX17510 Revision History