February 1997 NDS352AP P-Channel Logic Level Enhancement Mode Field Effect Transistor General Description Features These P -Channel logic level enhancement mode power field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. These devices are particularly suited for low voltage applications such as notebook computer power management, portable electronics, and other battery powered circuits where fast high-side switching, and low in-line power loss are needed in a very small outline surface mount package. -0.9 A, -30 V. RDS(ON) = 0.5 Ω @ VGS = -4.5 V RDS(ON) = 0.3 Ω @ VGS = -10 V. Industry standard outline SOT-23 surface mount package using proprietary SuperSOTTM-3 design for superior thermal and electrical capabilities. High density cell design for extremely low RDS(ON). Exceptional on-resistance and maximum DC current capability. ________________________________________________________________________________ D S G Absolute Maximum Ratings Symbol Parameter VDSS VGSS ID T A = 25°C unless otherwise noted NDS352AP Units Drain-Source Voltage -30 V Gate-Source Voltage - Continuous ±20 V Maximum Drain Current - Continuous ±0.9 A (Note 1a) - Pulsed PD TJ,TSTG Maximum Power Dissipation ±10 (Note 1a) 0.5 (Note 1b) 0.46 Operating and Storage Temperature Range W -55 to 150 °C THERMAL CHARACTERISTICS RθJA Thermal Resistance, Junction-to-Ambient (Note 1a) 250 °C/W RθJC Thermal Resistance, Junction-to-Case (Note 1) 75 °C/W © 1997 Fairchild Semiconductor Corporation NDS352AP Rev.D Electrical Characteristics (TA = 25°C unless otherwise noted) Symbol Parameter Conditions Min -30 Typ Max Units -1 µA -10 µA OFF CHARACTERISTICS BVDSS Drain-Source Breakdown Voltage VGS = 0 V, ID = -250 µA IDSS Zero Gate Voltage Drain Current VDS = -24 V, VGS = 0 V V TJ =125°C IGSSF Gate - Body Leakage, Forward VGS = 20 V, VDS = 0 V 100 nA IGSSR Gate - Body Leakage, Reverse VGS = -20 V, VDS = 0 V -100 nA -1.7 -2.5 V ON CHARACTERISTICS (Note 2) VGS(th) Gate Threshold Voltage RDS(ON) Static Drain-Source On-Resistance -0.8 VDS = VGS, ID = -250 µA TJ =125°C -0.5 VGS = -4.5 V, ID = -0.9 A TJ =125°C VGS = -10 V, ID = -1 A -1.4 -2.2 0.45 0.5 0.65 0.7 0.25 0.3 -2 Ω ID(ON) On-State Drain Current VGS = -4.5 V, VDS = -5 V gFS Forward Transconductance VDS = -5 V, ID = -0.9 A 1.9 A VDS = -15 V, VGS = 0 V, f = 1.0 MHz 135 pF 88 pF 40 pF S DYNAMIC CHARACTERISTICS Ciss Input Capacitance Coss Output Capacitance Crss Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2) td(on) Turn - On Delay Time tr Turn - On Rise Time td(off) Turn - Off Delay Time tf Turn - Off Fall Time td(on) Turn - On Delay Time VDD = -6 V, ID = -1 A, VGS = -4.5 V, RGEN = 6 Ω VDD = -10 V, ID = -1 A, VGS = -10 V, RGEN = 50 Ω 5 10 ns 17 30 ns 35 70 ns 30 60 ns 8 15 ns tr Turn - On Rise Time 16 30 ns td(off) Turn - Off Delay Time 35 90 ns tf Turn - Off Fall Time 30 90 ns Qg Total Gate Charge 2 3 nC Qgs Gate-Source Charge Qgd Gate-Drain Charge VDS = -10 V, ID = -0.9 A, VGS = -4.5 V 0.5 nC 1 nC NDS352AP Rev.D Electrical Characteristics (TA = 25°C unless otherwise noted) Symbol Parameter Conditions Min Typ Max Units -0.42 A -10 A -1.2 V DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS IS Maximum Continuous Source Current ISM Maximum Pulsed Drain-Source Diode Forward Current VSD Drain-Source Diode Forward Voltage VGS = 0 V, IS = -0.42 (Note 2) -0.8 Notes: 1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RθJC is guaranteed by design while RθCA is determined by the user's board design. PD (t) = T J −T A R θJA(t) = T J −T A R θJC +R θCA(t) = I 2D (t) × R DS(ON)@T J Typical RθJA using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment: a. 250oC/W when mounted on a 0.02 in2 pad of 2oz copper. b. 270oC/W when mounted on a 0.001 in2 pad of 2oz copper. 1a 1b Scale 1 : 1 on letter size paper 2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%. NDS352AP Rev.D Typical Electrical Characteristics 1.6 VGS = -10V -7.0 -6.0 -5.5 -4 R DS(on), NORMALIZED -5.0 -4.5 -3 -4.0 -2 -3.5 -1 0 -3.0 DRAIN-SOURCE ON-RESISTANCE I D , DRAIN-SOURCE CURRENT (A) -5 V GS = -3.5 V 1.4 1.2 -1 -2 V DS -3 -4 -4.5 -5.0 1 -5.5 -6.0 0.8 -7.0 -10 0.6 0.4 0 -4.0 -5 0 -4 -5 R DS(on), NORMALIZED V GS = -4.5V 1.4 1.2 1 0.8 0.6 -50 -25 0 25 50 75 100 T J , JUNCTION TEMPERATURE (°C) 125 DRAIN-SOURCE ON-RESISTANCE 1.6 I D = -0.9A TJ = 125°C 1.4 1.2 25°C 1 0.8 -55°C 0.6 0.4 V GS = -4.5V 0.2 150 0 T = -55°C J GATE-SOURCE THRESHOLD VOLTAGE -4 V DS = -10V 25 -3.2 125 -2.4 -1.6 -0.8 -1 -2 -3 -4 -5 V GS , GATE TO SOURCE VOLTAGE (V) Figure 5. Transfer Characteristics. -1 -2 I D , DRAIN CURRENT (A) -3 -4 Figure 4. On-Resistance Variation with Drain Current and Temperature. Figure 3. On-Resistance Variation with Temperature. D R DS(ON), NORMALIZED 1.6 DRAIN-SOURCE ON-RESISTANCE -2 -3 I D , DRAIN CURRENT (A) Figure 2. On-Resistance Variation with Drain Current and Gate Voltage. Figure 1. On-Region Characteristics. I , DRAIN CURRENT (A) -1 , DRAIN-SOURCE VOLTAGE (V) -6 1.2 1.1 1 0.9 0.8 0.7 -50 -25 0 25 50 75 100 125 150 T , JUNCTION TEMPERATURE (°C) Figure 6. Gate Threshold Variation with Temperature. NDS352AP Rev.C Typical Electrical Characteristics (continued) 4 VGS = 0V -I , REVERSE DRAIN CURRENT (A) ID = -250µA 1.08 1.06 1.04 1.02 1 0.98 1 T J = 125°C 0.1 0.96 0.94 -50 -25 0 25 50 75 100 T J , JUNCTION TEMPERATURE (°C) 125 150 Figure 7. Breakdown Voltage Variation with Temperature. -55°C 0.01 0.001 0.0001 0 0.2 0.4 0.6 0.8 1 1.2 -V SD , BODY DIODE FORWARD VOLTAGE (V) 1.4 Figure 8. Body Diode Forward Voltage Variation with Source Current and Temperature. 400 10 200 Ciss Coss 100 50 Crss 20 0 .1 0 .2 -10 -15 6 4 2 -V V GS = 0 V VDS = -5V 8 GS f = 1 MHz 30 ID = -0.9A , GATE-SOURCE VOLTAGE (V) 300 CAPACITANCE (pF) 25°C S BV DSS , NORMALIZED DRAIN-SOURCE BREAKDOWN VOLTAGE 1.1 -V 0 .5 1 2 5 10 , DRAIN TO SOURCE VOLTAGE (V) 20 0 30 0 1 3 4 5 , GATE CHARGE (nC) ton VDD t d(on) t off tr RL VIN g Figure 10. Gate Charge Characteristics. Figure 9. Capacitance Characteristics. t d(off) tf 90% 90% V OUT D VGS 2 Q DS VOUT R GEN 10% 10% DUT G 90% S V IN 50% 50% 10% PULSE WIDTH Figure 11. Switching Test Circuit. INVERTED Figure 12. Switching Waveforms. NDS352Ap Rev.C 20 3 V DS = - 5V 1m s 10 -I D , DRAIN CURRENT (A) 2.5 TJ = -55°C 2 25°C 1.5 125°C 1 5 2 RD g 0 -1 -2 -3 -4 -5 0.05 0.01 0.1 0.8 1a 1b 0.4 4.5"x5" FR-4 Board o TA = 25 C Still Air 0 0.2 0m s s 10s DC 0.2 0.5 1 2 5 10 20 30 50 0.3 Figure 14. Maximum Safe Operating Area. -ID , STEADY-STATE DRAIN CURRENT (A) STEADY-STATE POWER DISSIPATION (W) 1 0.1 10 VGS = -4.5V SINGLE PULSE RθJA = See Note 1b A T = 25°C A 0.1 D 0 10m - VDS , DRAIN-SOURCE VOLTAGE (V) Figure 13. Transconductance Variation with Drain Current and Temperature. 0.2 LI 1s I , DRAIN CURRENT (A) 0.6 N) 0.5 0.5 0 S(O T MI 1 FS , TRANSCONDUCTANCE (SIEMENS) Typical Electrical Characteristics (continued) 1.2 1.1 1 0.9 1a 0.8 1b 4.5"x5" FR-4 Board o TA = 25 C Still Air VGS = -4.5V 0.7 0.6 0.4 0 0.1 2oz COPPER MOUNTING PAD AREA (in2 ) 0.2 0.3 0.4 2 2oz COPPER MOUNTING PAD AREA (in ) Figure 16. Maximum Steady-State Drain Current versus Copper Mounting Pad Area. Figue 15. SuperSOTTM _ 3 Maximum Steady-State Power Dissipation versus Copper Mounting Pad Area. r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE 1 0.5 0.2 D = 0.5 R θJA (t) = r(t) * R θJA R θJA = See Note 1b 0.2 0.1 0.1 0.05 0.05 0.02 0.01 0.005 P(pk) 0.02 t1 0.01 t2 TJ - TA = P * R θJA (t) Single Pulse Duty Cycle, D = t1 /t2 0.002 0.001 0.0001 0.001 0.01 0.1 t 1 , TIME (sec) 1 10 100 300 Figure 17. Transient Thermal Response Curve. Note : Characterization performed using the conditions described in note 1b. Transient thermal response will change depending on the circuit board design. NDS352Ap Rev.C