May 1997 NDH853N N-Channel Enhancement Mode Field Effect Transistor General Description Features These N-Channel enhancement mode power field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance and provide superior switching performance. These devices are particularly suited for low voltage applications such as battery powered circuits or portable electronics where fast switching, low in-line power loss, and resistance to transients are needed. 7.6 A, 30 V. RDS(ON) = 0.017 Ω @ VGS = 10 V RDS(ON) = 0.025 Ω @ VGS = 4.5 V. High density cell design for extremely low RDS(ON). Proprietary SuperSOTTM-8 small outline surface mount package with high power and current handling capability. ___________________________________________________________________________________________ 5 4 6 3 7 2 8 1 Absolute Maximum Ratings T A = 25°C unless otherwise noted Symbol Parameter NDH853N Units VDSS Drain-Source Voltage 30 V VGSS Gate-Source Voltage ±20 V ID Drain Current - Continuous 7.6 A (Note 1a) - Pulsed PD TJ,TSTG 23 Maximum Power Dissipation (Note 1a) 1.8 (Note 1b) 1 (Note 1c) 0.9 Operating and Storage Temperature Range W -55 to 150 °C THERMAL CHARACTERISTICS RθJA Thermal Resistance, Junction-to-Ambient (Note 1a) 70 °C/W RθJC Thermal Resistance, Junction-to-Case (Note 1) 20 °C/W © 1997 Fairchild Semiconductor Corporation NDH853N Rev. C ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted) Symbol Parameter Conditions Min Typ Max Units 1 µA OFF CHARACTERISTICS BVDSS Drain-Source Breakdown Voltage VGS = 0 V, ID = 250 µA IDSS Zero Gate Voltage Drain Current VDS = 24 V, VGS = 0 V 30 V 10 µA IGSSF Gate - Body Leakage, Forward VGS = 20 V, VDS = 0 V 100 nA IGSSR Gate - Body Leakage, Reverse VGS = -20 V, VDS= 0 V -100 nA V TJ= 55°C ON CHARACTERISTICS (Note 2) VGS(th) Gate Threshold Voltage VDS = VGS, ID = 250 µA TJ= 125°C RDS(ON) Static Drain-Source On-Resistance 1 1.5 2 0.7 1 1.6 0.014 0.017 0.02 0.031 0.021 0.025 VGS = 10 V, ID = 7.6 A TJ= 125°C VGS = 4.5 V, ID = 6.7 A 23 Ω ID(on) On-State Drain Current VGS = 10 V, VDS = 5 V A gFS Forward Transconductance VDS = 10 V, ID = 7.6 A 18 S VDS = 15 V, VGS = 0 V, f = 1.0 MHz 1140 pF 630 pF 210 pF DYNAMIC CHARACTERISTICS Ciss Input Capacitance Coss Output Capacitance Crss Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2) tD(on) Turn - On Delay Time tr Turn - On Rise Time tD(off) Turn - Off Delay Time tf Turn - Off Fall Time Qg Total Gate Charge Qgs Gate-Source Charge Qgd Gate-Drain Charge VDD = 10 V, ID = 1 A, VGEN = 10 V, RGEN = 6 Ω VDS = 15 V, ID = 7.6 A, VGS = 10 V 14 30 ns 24 50 ns 73 120 ns 48 80 ns 38 50 nC 2.8 nC 12.7 nC NDH853N Rev. C ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted) Symbol Parameter Conditions Min Typ Max Units 1.5 A 1.2 V DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS IS Maximum Continuous Drain-Source Diode Forward Current VSD Drain-Source Diode Forward Voltage VGS = 0 V, IS = 1.5 A 0.72 (Note 2) Notes: 1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RθJC is guaranteed by design while RθCA is determined by the user's board design. PD (t) = T J −T A R θJA (t) = T J −T A R θJC +R θCA (t) = I 2D(t) × R DS(ON)@T J Typical RθJA using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment: a. 70oC/W when mounted on a 1 in2 pad of 2oz cpper. b. 125oC/W when mounted on a 0.026 in2 pad of 2oz copper. c. 135oC/W when mounted on a 0.005 in2 pad of 2oz copper. 1a 1b 1c Scale 1 : 1 on letter size paper 2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%. NDH853N Rev. C Typical Electrical Characteristics 3 30 6.0 25 4.0 4.5 R DS(on) , NORMALIZED 3.5 20 15 10 3.0 5 DRAIN-SOURCE ON-RESISTANCE I D , DRAIN-SOURCE CURRENT (A) VGS =10V V GS = 3.5V 2.5 2 4.0 4.5 5.0 1.5 6.0 10 1 2.5 0 0.5 0 0.5 1 1.5 2 VDS , DRAIN-SOURCE VOLTAGE (V) 2.5 3 0 5 Figure 1. On-Region Characteristics. 1.4 R DS(on) , NORMALIZED V GS = 10V 1.2 1 0.8 -25 0 25 50 75 100 T J , JUNCTION TEMPERATURE (°C) 125 DRAIN-SOURCE ON-RESISTANCE R DS(ON), NORMALIZED DRAIN-SOURCE ON-RESISTANCE 30 1.8 I D = 7.6A 0.6 -50 V G S = 10 V 1.6 TJ = 125°C 1.4 1.2 25°C 1 -55°C 0.8 0.6 150 0 5 10 I D , DRAIN CURRENT (A) 15 20 Figure 4. On-Resistance Variation with Drain Current and Temperature. Figure 3. On-Resistance Variation with Temperature. 30 T = -55°C J 125°C 25°C 20 15 10 5 1 1.5 2 2.5 3 3.5 V GS , GATE TO SOURCE VOLTAGE (V) Figure 5. Transfer Characteristics. 4 4.5 V th, NORMALIZED 25 GATE-SOURCE THRESHOLD VOLTAGE 1.2 V DS = 10V ID , DRAIN CURRENT (A) 25 Figure 2. On-Resistance Variation withDrain Current and Gate Voltage. 1.6 0 0.5 10 15 20 I D , DRAIN CURRENT (A) V DS = V GS I D = 250µA 1.1 1 0.9 0.8 0.7 0.6 0.5 -50 -25 0 25 50 75 100 T J , JUNCTION TEMPERATURE (°C) 125 150 Figure 6. Gate Threshold Variation with Temperature. NDH853N Rev. C 30 1.1 I D = 250µA 1.08 1.06 1.04 1.02 1 0.98 0.96 0.94 -50 1 25°C 0.001 0.0001 -25 0 25 50 75 100 TJ , JUNCTION TEMPERATURE (°C) 125 0 150 0.2 0.4 0.6 0.8 1 VSD , BODY DIODE FORWARD VOLTAGE (V) 10 V DS = 10V I D = 7.6A VGS , GATE-SOURCE VOLTAGE (V) C iss 1000 C oss 500 300 C rss f = 1 MHz V GS = 0 V 0 .2 V DS 0 .5 1 2 5 10 , DRAIN TO SOURCE VOLTAGE (V) 20 30 20V 8 15V 6 4 2 0 0 10 t d(on) 40 t off tr RL t d(off) tf 90% 90% V OUT D VOUT R GEN 30 t on VDD V IN 20 Q g , GATE CHARGE (nC) Figure 10. Gate Charge Characteristics. Figure 9. Capacitance Characteristics. VGS 1.2 Figure 8. Body Diode Forward Voltage Variation with Source Current and Temperature. 2000 CAPACITANCE (pF) -55°C 0.01 3000 100 0 .1 TJ = 125°C 0.1 Figure 7. Breakdown Voltage Variation with Temperature. 200 V GS = 0V 10 I S , REVERSE DRAIN CURRENT (A) BV DSS , NORMALIZED DRAIN-SOURCE BREAKDOWN VOLTAGE Typical Electrical Characteristics (continued) 10% 10% DUT G INVERTED 90% S V IN 50% 50% 10% PULSE WIDTH Figure 11. Switching Test Circuit. Figure 12. Switching Waveforms. NDH853N Rev. C Typical Electrical and Thermal Characteristics (continued) 2.5 35 30 25°C 25 20 125°C 15 10 5 g FS , TRANSCONDUCTANCE (SIEMENS) STEADY-STATE POWER DISSIPATION (W) T J = -55°C V DS =10V 0 0 5 10 15 20 I D , DRAIN CURRENT (A) 25 1a 1.5 1b 1 1c 0.5 4.5"x5" FR-4 Board o TA = 2 5 C Still Air 0 0 30 0.2 0.4 0.6 0.8 2oz COPPER MOUNTING PAD AREA (in 2 ) 9 50 30 8 10 RD S(O N) LIM IT 10 I D, DRAIN CURRENT (A) 1a 7 6 1b 1c 4.5"x5" FR-4 Board 5 1 Figure 14. SOT-8 Maximum Steady-State Power Dissipation versus Copper Mounting Pad Area. Figure 13. Transconductance Variation with Drain Current and Temperature. I D , STEADY-STATE DRAIN CURRENT (A) 2 0m s 10 s DC VGS = 1 0 V 0.03 s ms 1s 0.3 o Still Air 10 10 1 TA = 2 5 C s 1m 3 0.1 0u SINGLE PULSE R θ J A =See Note1c TA = 25°C VG S = 1 0 V 4 0 0.2 0.4 0.6 0.8 2 2oz COPPER MOUNTING PAD AREA (in ) Figure 15. Maximum Steady-State Drain Current versus Copper Mounting Pad Area. 1 0.01 0.1 0.2 0.5 V DS 1 2 5 10 , DRAIN-SOURCE VOLTAGE (V) 30 50 Figure 16. Maximum Safe Operating Area. TRANSIENT THERMAL RESISTANCE r(t), NORMALIZED EFFECTIVE 1 0.5 D = 0.5 R JA (t) = r(t) * R JA θ θ R JA = See Note 1c θ 0.3 0.2 0.1 0.2 0.1 P(pk) 0.05 t1 0.05 0.02 0.03 0.02 0.01 0.0001 t2 TJ - T = P * R JA (t) θ Duty Cycle, D = t 1 / t 2 0.01 A Single Pulse 0.001 0.01 0.1 t 1 , TIME (sec) 1 10 100 300 Figure 17. Transient Thermal Response Curve. Note: Thermal characterization performed using the conditions described in note 1c. Transient thermal response will change depending on the circuit board design. NDH853N Rev. C