May 1997 NDH8303N Dual N-Channel Enhancement Mode Field Effect Transistor General Description Features SuperSOTTM-8 N-Channel enhancement mode power field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. These devices are particularly suited for low voltage applications such as notebook computer power management, and other battery powered circuits where fast switching, and low in-line power loss are needed in a very small outline surface mount package. 3.8 A, 20 V. RDS(ON) = 0.035 Ω @ VGS = 4.5 V RDS(ON) = 0.045 Ω @ VGS = 2.7 V. Proprietary SuperSOTTM-8 package design using copper lead frame for superior thermal and electrical capabilities. High density cell design for extremely low RDS(ON). Exceptional on-resistance and maximum DC current capability. ____________________________________________________________________________________________ 5 4 6 3 7 2 8 1 Absolute Maximum Ratings T A = 25°C unless otherwise noted Symbol Parameter VDSS Drain-Source Voltage VGSS Gate-Source Voltage ID Drain Current - Continuous PD Maximum Power Dissipation TJ,TSTG Operating and Storage Temperature Range NDH8303N Units 20 V ±8 V (Note 1) 3.8 A (Note 1) 0.8 W -55 to 150 °C - Pulsed 15 THERMAL CHARACTERISTICS RθJA Thermal Resistance, Junction-to-Ambient (Note 1) 156 °C/W RθJC Thermal Resistance, Junction-to-Case (Note 1) 40 °C/W © 1997 Fairchild Semiconductor Corporation NDH8303N Rev.C ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted) Symbol Parameter Conditions Min Typ Max Units 1 µA OFF CHARACTERISTICS BVDSS Drain-Source Breakdown Voltage VGS = 0 V, ID = 250 µA IDSS Zero Gate Voltage Drain Current VDS = 16 V, VGS = 0 V 20 V TJ = 55oC 10 µA IGSSF Gate - Body Leakage, Forward VGS = 8 V, VDS = 0 V 100 nA IGSSR Gate - Body Leakage, Reverse VGS = -8 V, VDS= 0 V -100 nA V ON CHARACTERISTICS (Note 2) VGS(th) Gate Threshold Voltage VDS = VGS, ID = 250 µA TJ = 125oC RDS(ON) Static Drain-Source On-Resistance 0.4 0.7 1 0.3 0.45 0.8 0.029 0.035 0.043 0.063 0.036 0.045 VGS = 4.5 V, ID = 3.8 A TJ = 125oC VGS = 2.7 V, ID = 3.3 A ID(on) gFS On-State Drain Current Forward Transconductance VGS = 4.5 V, VDS = 5 V 15 VGS = 2.7 V, VDS = 5 V 5 Ω A VDS = 5 V, ID = 3.8 A 15 S VDS = 10 V, VGS = 0 V, f = 1.0 MHz 700 pF 370 pF 145 pF DYNAMIC CHARACTERISTICS Ciss Input Capacitance Coss Output Capacitance Crss Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2) tD(on) Turn - On Delay Time tr Turn - On Rise Time tD(off) Turn - Off Delay Time tf Turn - Off Fall Time Qg Total Gate Charge Qgs Gate-Source Charge Qgd Gate-Drain Charge VDD = 5 V, ID = 1 A, VGS = 4.5 V, RGEN = 6 Ω VDS = 10 V, ID = 3.8 A, VGS = 4.5 V 8 15 ns 22 40 ns 48 90 ns 23 40 ns 19.6 nC 2.5 nC 6.5 nC NDH8303N Rev.C ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted) Symbol Parameter Conditions Min Typ Max Units 0.67 A 1.2 V DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS IS Maximum Continuous Drain-Source Diode Forward Current VSD Drain-Source Diode Forward Voltage VGS = 0 V, IS = 0.67 A (Note 2) 0.65 Notes: 1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RθJC is guaranteed by design while RθCA is determined by the user's board design. P D (t ) = T J− TA R θJA(t ) = T J−TA R θJC+RθCA(t ) = I 2D (t ) × RDS (ON ) TJ Typical RθJA for single device operation using the board layout shown below on 4.5"x5" FR-4 PCB in a still air environment: 156oC/W when mounted on a 0.0025 in2 pad of 2oz copper. Scale 1 : 1 on letter size paper. 2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%. NDH8303N Rev.C Typical Electrical Characteristics 20 V GS 2 = 4.5V 2.5 2.7 R DS(on), NORMALIZED 2.0 DRAIN-SOURCE ON-RESISTANCE I D , DRAIN-SOURCE CURRENT (A) 3.0 16 12 8 1.5 4 0 0 0.5 1 DS 1.5 2 2.5 VGS = 2.0V 1 .6 1 .4 2.5 2.7 3.0 1 .2 3.5 4.0 4.5 1 0 .8 3 0 4 8 , DRAIN-SOURCE VOLTAGE (V) 16 20 Figure 1. On-Region Characteristics. Figure 2. On-Resistance Variation with Gate Voltage and Drain Current. 1 .8 2 V GS = 4.5 V I D = 3.8A 1 .6 R DS(on), NORMALIZED V GS = 4.5V 1 .4 1 .2 1 0 .8 0 .6 -50 -25 0 25 50 75 100 125 TJ = 125°C 1.5 25°C 1 -55°C 0.5 0 150 0 4 TJ , JUNCTION TEMPERATURE (°C) I D 8 12 , DRAIN CURRENT (A) 16 20 Figure 4. On-Resistance Variation with Drain Current and Temperature. Figure 3. On-Resistance Variation with Temperature. T = -55°C J 25°C VDS = 5V 125°C V th, NORMALIZED 12 9 6 3 0 0 0.5 1 1.5 2 V GS , GATE TO SOURCE VOLTAGE (V) Figure 5. Transfer Characteristics. 2.5 GATE-SOURCE THRESHOLD VOLTAGE 1.3 15 I D , DRAIN CURRENT (A) 12 I D , DRAIN CURRENT (A) DRAIN-SOURCE ON-RESISTANCE R DS(ON) , NORMALIZED DRAIN-SOURCE ON-RESISTANCE V 1 .8 VDS = VGS 1.2 I D = 250µA 1.1 1 0.9 0.8 0.7 0.6 0.5 -50 -25 0 25 50 75 100 T , JUNCTION TEMPERATURE (°C) 125 150 J Figure 6. Gate Threshold Variation with Temperature. NDH8303N Rev.C Typical Electrical Characteristics 15 1.1 1.05 1 0.95 0.9 -50 -25 0 T 25 50 75 100 , JUNCTION TEMPERATURE (°C) J 125 150 25°C -55°C 0 .1 0 .0 1 0 .0 0 1 0 .0 0 0 1 0 0 .2 0 .4 0.6 0 .8 1 V SD , BODY DIODE FORWARD VOLTAGE (V) 1 .2 Figure 8. Body Diode Forward Voltage Variation with Current and Temperature. 5 2500 2000 VDS = 5V I D = 3.8A , GATE-SOURCE VOLTAGE (V) 1500 1000 Ciss 500 Coss 300 f = 1 MHz Crss 15V 3 2 1 V V GS = 0 V 10V 4 GS CAPACITANCE (pF) TJ = 125°C 1 0 .5 Figure 7. Breakdown Voltage Variation with Temperature. 200 VGS =0V 5 ID = 250µA I S, REVERSE DRAIN CURRENT (A) BV DSS , NORMALIZED DRAIN-SOURCE BREAKDOWN VOLTAGE 1.15 100 0 .1 0 0 .2 V DS 0 .5 1 3 5 , DRAIN TO SOURCE VOLTAGE (V) 10 0 20 5 t d(on) t d(off) tf 90% 90% V OUT VOUT 10% 10% INVERTED DUT G 25 t off tr RL D R GEN 20 t on VDD VGS 15 Figure 10. Gate Charge Characteristics. Figure 9. Capacitance Characteristics. V IN 10 Q g , GATE CHARGE (nC) 90% S V IN 50% 50% 10% PULSE WIDTH Figure 11. Switching Test Circuit. Figure 12. Switching Waveforms. NDH8303N Rev.C Typical Electrical and Thermal Characteristics 30 30 TJ = -55°C 10 25 RD I D , DRAIN CURRENT (A) 25°C 20 125°C 15 10 S( ) ON LIM 10 0u s 1m s IT 10 3 10 1 ms 0m s 1s 10 0.3 VGS = 4.5V R θJ A s DC SINGLE PULSE 0.1 5 = See Note 1c T A = 25°C 0.03 g FS , TRANSCONDUCTANCE (SIEMENS) V DS = 5V 0 0 4 I D 8 12 , DRAIN CURRENT (A) 16 Figure 13. Transconductance Variation with Drain Current and Temperature. 20 0.01 0.1 0.2 0.5 1 2 5 10 VDS , DRAIN-SOURCE VOLTAGE (V) 20 30 Figure 14. Maximum Safe Operating Area. r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE 1 D = 0.5 0.1 R θJA (t) = r(t) * R θJA R JA = See Note 1 θ 0.2 0.1 0.05 P(pk) 0.02 0.01 t1 0.01 0.001 0.0001 0.001 t2 TJ - T = P * R (t) A θJA Duty Cycle, D = t 1 / t 2 Single Pulse 0.01 0.1 t 1 , TIME (sec) 1 10 100 300 Figure 15. Transient Thermal Response Curve. Note: Thermal characterization performed using the conditions described in note1. Transient thermal response will change depending on the circuit board design. NDH8303N Rev.C