PHILIPS BUK3F00

BUK3F00-50WDxx
Controller for TrenchPLUS FETs
Rev. 04 — 4 September 2008
Product data sheet
1. Introduction
This data sheet describes a family of integrated circuits which provide direct digital control
of multiple power switches (TrenchPLUS FETs) for use in automotive applications, and
which are available in various configurations.
2. General description
Eight channel high-side switch controller in a leaded plastic quad flat package, with digital
control and diagnostics, and load current measurement.
Specific configurations are denoted by the last 2 letters in the type number.
3. Features
n
n
n
n
n
n
n
n
n
n
n
n
n
n
Standby mode with very low power consumption
Programmable drain current tripping
Serial Peripheral Interface (SPI) communications
Outputs controllable via SPI-bus or direct input
Diagnostic status reporting via SPI-bus
Analog and digital drain current measurement
Watchdog for invalid commands or inactive SPI, with programmable time-out
Programmable interrupt generator
Overtemperature protection
Pulse-width modulation with programmable frequency and duty cycle
ESD protection on all pins
Protection for battery transient overvoltage and reversed polarity battery connection
Open-circuit detection
Configurable fail-safe channel control options
4. Applications
n Automotive applications such as DC and pulse-width modulation control in body
control clusters, etc.
BUK3F00-50WDxx
NXP Semiconductors
Controller for TrenchPLUS FETs
5. Quick reference data
Table 1.
Quick reference data
Symbol
Parameter
Conditions
battery supply voltage
VBAT
operating
junction temperature
Tj
Min
Typ
Max
Unit
[1]
5.5
13
52
V
[2]
−40
-
+150
°C
[1]
When VBAT < 9 V, the charge pump cannot be guaranteed to drive the external MOSFETs to achieve their specified RDSon.
[2]
When Tj > 125 °C, the device will function, but electrical parameters may deviate from the specified values.
6. Ordering information
Table 2.
Ordering information
Type number
Package
Name
Description
Version
BUK3F00-50WDFE QFP64 plastic quad flat package; 64 leads (lead length 1.6 mm); body 14 × 14 × 2.7 mm SOT393-1
BUK3F00-50WDFM
BUK3F00-50WDFY
6.1 Ordering options
Table 3.
Type number differences
Type number
Description
BUK3F00-50WDFE
channel 4 has analog trip ratio of 3 × Imeas(ADC)(fs)[1]
BUK3F00-50WDFM
-
BUK3F00-50WDFY
-
[1]
Imeas(ADC)(fs) = full-scale ADC measure current.
User-accessible registers; see Table 5.
Protected settings; see Table 19.
Additional metal mask options; see Table 35.
BUK3F00-50WDXX_4
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 04 — 4 September 2008
2 of 52
BUK3F00-50WDxx
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Controller for TrenchPLUS FETs
7. Block diagram
VBAT
VBAT
VBAT(CP)
7
VCC(MOD)
VCC(LOG)EXT
VCC(DIGC)
GND(DIGC)
VCC(MEASC)
10
44
38
37
6
GND 1,
16,
33,
48
IREFCURR 8
IREFTEMP 9
WDEN
WDTON
SCSN
SDI
SDO
SCLK
EN
IN0
IN1
IN2
IN3
INP
PWMMON
INTN
42
46
39
43
SUPPLIES
CHARGE
PUMP
POWER AND
REFERENCE
SUPPLIES
REFERENCE
SUPPLIES
gate
0 to 7
SPI
WATCHDOG
SERIAL
PERIPHERAL
INTERFACE (SPI)
TrenchPLUS
FET
INTERFACE
(8×)
EXTERNAL
TrenchPLUS
FET
SWITCHES
(8×)
sense
0 to 7
CURRENT
SENSE
DIGITAL
CONTROL
kelvin
0 to 7
PULSE-WIDTH
MODULATION
(PWM)
cathode
0 to 7
INTERRUPT
CONTROL LOGIC
IMEAS
TEMPERATURE
SENSE
BUK3F00-50WDxx
11
3
4
13
12
14
47
CPP CT GND(CP)
40
anode
0 to 7
15
2
35
36
45
34
CPN
41
5
CURRENT
MEASUREMENT
001aaf047
Fig 1.
Block diagram
BUK3F00-50WDXX_4
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 04 — 4 September 2008
3 of 52
BUK3F00-50WDxx
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Controller for TrenchPLUS FETs
8. Pinning information
49 KELVIN3
50 ANODE3
51 SENSE3
52 GATE3
53 KELVIN2
54 ANODE2
55 SENSE2
56 GATE2
57 KELVIN1
58 ANODE1
59 SENSE1
60 GATE1
61 KELVIN0
62 ANODE0
63 SENSE0
64 GATE0
8.1 Pinning
GND
1
48 GND
WDTON
2
47 PWMMON
IN0
3
46 INTN
IN1
4
45 SDO
IMEAS
5
VCC(MEASC)
6
44 VCC(LOG)EXT
43 GND(CP)
VBAT
7
IREFCURR
8
IREFTEMP
9
42 VBAT(CP)
41 CPN
BUK3F00-50WDxx
40 CPP
VCC(MOD) 10
39 CT
EN 11
IN3 12
38 VCC(DIGC)
37 GND(DIGC)
IN2 13
36 SDI
INP 14
35 SCSN
WDEN 15
34 SCLK
GND 16
Fig 2.
GATE4 32
SENSE4 31
ANODE4 30
KELVIN4 29
GATE5 28
SENSE5 27
ANODE5 26
KELVIN5 25
GATE6 24
SENSE6 23
ANODE6 22
KELVIN6 21
GATE7 20
SENSE7 19
ANODE7 18
KELVIN7 17
33 GND
001aaf048
Pin configuration
8.2 Pin description
Table 4.
Pin description
Symbol
Pin
Description
VBAT
7
battery supply voltage
GND
1, 16, 33, 48
battery ground
VBAT(CP)
42
charge pump battery supply voltage
Supplies
GND(CP)
43
charge pump ground
VCC(DIGC)
38
digital core supply voltage
GND(DIGC)
37
digital core ground
VCC(MOD)
10
module supply voltage
VCC(LOG)EXT
44
external logic supply voltage for PWMMON and SDO outputs
VCC(MEASC)
6
measurement circuit supply voltage
BUK3F00-50WDXX_4
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 04 — 4 September 2008
4 of 52
BUK3F00-50WDxx
NXP Semiconductors
Controller for TrenchPLUS FETs
Table 4.
Pin description …continued
Symbol
Pin
Description
Charge pump capacitors
CPP
40
positive connection to external pump capacitor
CPN
41
negative connection to external pump capacitor
CT
39
connection to external storage capacitor
EN
11
enable input; internal pull-down resistor
INTN
46
interrupt output; open-drain output
WDEN
15
watchdog enable input; internal pull-up resistor
WDTON
2
watchdog timed output; open-drain output
PWMMON
47
PWM frequency monitor output
Digital
Serial peripheral interface
SCLK
34
SPI clock input; internal pull-down resistor
SCSN
35
SPI chip select input; internal pull-up resistor
SDI
36
SPI data input; internal pull-down resistor
SDO
45
SPI data output; 3-state when inactive
IREFCURR
8
set reference for current measurement (with external resistor)
IREFTEMP
9
set reference for temperature sense (with external resistor)
IMEAS
5
analog current measurement output (for selected channel)
Analog
Direct input pins
IN0
3
direct input 0; internal pull-down resistor
IN1
4
direct input 1; internal pull-down resistor
IN2
13
direct input 2; internal pull-down resistor
IN3
12
direct input 3; internal pull-down resistor
INP
14
PWM input; internal pull-down resistor
Connections for external TrenchPLUS switches
Channel 0
GATE0
64
gate
KELVIN0
61
source kelvin
SENSE0
63
current sense
ANODE0
62
anode of temperature sense diode
GATE1
60
gate
KELVIN1
57
source kelvin
SENSE1
59
current sense
ANODE1
58
anode of temperature sense diode
GATE2
56
gate
KELVIN2
53
source kelvin
SENSE2
55
current sense
ANODE2
54
anode of temperature sense diode
Channel 1
Channel 2
BUK3F00-50WDXX_4
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 04 — 4 September 2008
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BUK3F00-50WDxx
NXP Semiconductors
Controller for TrenchPLUS FETs
Table 4.
Symbol
Pin description …continued
Pin
Description
GATE3
52
gate
KELVIN3
49
source kelvin
SENSE3
51
current sense
ANODE3
50
anode of temperature sense diode
32
gate
Channel 3
Channel 4
GATE4
KELVIN4
29
source kelvin
SENSE4
31
current sense
ANODE4
30
anode of temperature sense diode
GATE5
28
gate
KELVIN5
25
source kelvin
SENSE5
27
current sense
ANODE5
26
anode of temperature sense diode
GATE6
24
gate
KELVIN6
21
source kelvin
SENSE6
23
current sense
ANODE6
22
anode of temperature sense diode
GATE7
20
gate
KELVIN7
17
source kelvin
SENSE7
19
current sense
ANODE7
18
anode of temperature sense diode
Channel 5
Channel 6
Channel 7
BUK3F00-50WDXX_4
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 04 — 4 September 2008
6 of 52
BUK3F00-50WDxx
NXP Semiconductors
Controller for TrenchPLUS FETs
9. Functional description
The main functions of the device are:
•
•
•
•
•
Power and reference supplies
Charge pump
Control logic
Current measurement
TrenchPLUS FET interface (8×)
9.1 Power and reference supplies
The main battery supplies power to the device and the eight TrenchPLUS FET switches.
This device is intended for vehicle system applications that operate at a battery voltage of
12 V, 24 V or 42 V. The device has several different supply connections to ensure correct
operation of the device within the application module.
9.1.1 Battery supply: pins VBAT and GND
Pins VBAT and GND are the direct supply connections of the device to the battery.
Low battery voltage is detected on the charge pump supply pin VBAT(CP). Channels are
switched off during extended low battery supply conditions and switched on when normal
battery conditions return.
Extended low battery voltage occurs when the battery supply voltage VBAT goes below:
• the battery undervoltage threshold (Vth(uv)bat) for longer than the battery low time
(tlow(bat))
• the battery low threshold voltage (Vth(low)bat)
Transient low battery voltage occurs when the battery supply voltage VBAT goes below
Vth(uv)bat for less than tlow(bat), but remains above Vth(low)bat. Transient low battery voltage
conditions affect the overcurrent protection; for details see Section 9.5.2 “Overcurrent
protection”.
Normal battery voltage occurs when the battery supply voltage exceeds Vth(uv)bat for
more than the battery high time (thigh(bat)).
Hysteresis on detection reduces the possibility of repeated switching when the battery
supply voltage is close to the threshold values.
The supply circuit has an internal overvoltage clamp to protect the control IC from
overvoltage transients and is also protected against ESD. All four GND pins must be
connected together to ground.
If this supply is connected to a reverse polarity battery voltage then the FET switches are
turned on to protect against conduction through the source-drain diode. This protection
operates whether the device is enabled or not.
BUK3F00-50WDXX_4
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 04 — 4 September 2008
7 of 52
BUK3F00-50WDxx
NXP Semiconductors
Controller for TrenchPLUS FETs
9.1.2 Module supply: pins VCC(MOD) and GND
Pins VCC(MOD) and GND supply power to the circuits in the device that need to be kept
functioning when the main battery supply dips below its normal operating limit. It is
anticipated that the connection will be to the protected supply of the application module
control circuits. This can be created using a suitable diode and storage capacitor from the
battery supply. The connection should be decoupled close to the device.
Low module voltage causes the device to go through a Power-On Reset (POR). This
condition is detected when the module supply voltage goes below the module
undervoltage threshold voltage (Vth(uv)mod). The power-on reset is triggered when the
supply voltage recovers and exceeds Vth(uv)mod. Hysteresis on this detection reduces the
possibility of repeated resetting when the module supply is close to the threshold value.
The supply circuit has an internal overvoltage clamp to protect the control chip from
overvoltage transients and is also protected against ESD. This supply should be protected
against reverse battery connection in the application circuit.
9.1.3 External logic supply: pins VCC(LOG)EXT and GND
The external logic supply provides power for the SDO and PWMMON output pins. Pin
VCC(LOG)EXT should be connected to the same supply (3.3 V or 5 V) used by the circuits
that monitor these outputs.
9.1.4 Analog measurement supply: pins VCC(MEASC) and GND
This supply provides power for the IMEAS analog current measurement output. Pin
VCC(MEASC) should be connected to the same supply (3.3 V or 5 V) used by the circuit that
uses this output.
If this output is not needed, then pins VCC(MEASC) and IMEAS should be grounded.
9.1.5 Digital supply: pins VCC(DIGC) and GND(DIGC)
This supplies power to the internal regulator for the digital core and should be connected
to the same potential as VCC(MOD) and GND. It is not internally connected to the module
supply, ensuring that digital noise does not affect the measurement circuits. The
connection should be decoupled close to the device.
The digital supply circuit has an internal overvoltage clamp to protect the
BUK3F00-50WDxx from overvoltage transients and is also protected against ESD.
9.1.6 Reference supplies: pins IREFCURR and IREFTEMP
An internal band gap reference is used to ensure stable voltage and current references:
• Measured current reference pin IREFCURR: The full-scale analog output
measurement current and the full-scale measurement current through the ADC are
both set by connecting an external resistor between pins IREFCURR and GND.
• Temperature reference pin IREFTEMP: The forward current for the temperature
sensing diodes in the TrenchPLUS FETs is set by connecting an external resistor
between pins IREFTEMP and GND.
BUK3F00-50WDXX_4
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 04 — 4 September 2008
8 of 52
BUK3F00-50WDxx
NXP Semiconductors
Controller for TrenchPLUS FETs
9.2 Charge pump
The controller has an internal charge pump circuit to supply the gate voltage required to
operate the high-side FET switches. The charge pump uses an internal oscillator and
internal switches with external pump and storage capacitors.
9.2.1 Charge pump supply: pins VBAT(CP) and GND(CP)
Pins VBAT(CP) and GND(CP) supply power to the internal charge pump. This is derived
from the VBAT supply either via an internal resistor between pins VBAT and VBAT(CP) or by
linking these pins externally. Pin GND(CP) should be connected to pin GND; the grounds
are not internally connected to ensure any charge pump noise does not affect the
measurement circuit. The connections should be decoupled close to the device.
The charge pump supply circuit has an internal overvoltage clamp to protect the
BUK3F00-50WDxx from overvoltage transients and is also protected against ESD.
If connected to a reverse polarity battery voltage, the charge pump supply is protected by
the internal resistor connection to VBAT.
9.2.2 Charge pump boost mode
To ensure fast start-up, the charge pump has a boost mode that operates for a set time.
This mode is triggered at power-on reset and when the charge pump voltage falls below
the charge pump fault threshold or the battery voltage stays below the undervoltage
threshold. If the charge pump voltage is below the fault threshold after the charge pump
boost is completed, then no further boost is possible until the charge pump fault is
cleared.
9.3 Control logic
The control logic is responsible for switching the individual FET channels on and off,
depending on user settings and the implementation of protection methods. It contains
registers used for storing the user settings for channel configurations, current reference
and measurement, diagnostic and watchdog modes. Communication with a controller is
via the SPI-bus.
The digital block is designed to support 8 channels; unused channels should be
programmed off at all times.
9.3.1 Digital control
The device is enabled by pin EN. When pin EN is LOW, the device is in Standby mode and
all FETs are held off by an active switch with a standby resistance between pins GATE
and KELVIN. When pin EN is HIGH, the device is enabled for normal operation. Pin EN
can be used as the reset signal by a controller for the control logic. When pin EN is reset
to HIGH, the device goes through a power-on reset, registers are loaded with their default
values and channels are switched on or off according to the mapping for the individual
device type.
Digital control consists of a number of registers that control the functions. The default
value is loaded during power-on reset and, if the WRITE_PROTECT option is enabled, for
defined registers, when the SPI watchdog times out. For some registers the default setting
can be programmed by metal mask options.
BUK3F00-50WDXX_4
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 04 — 4 September 2008
9 of 52
BUK3F00-50WDxx
NXP Semiconductors
Controller for TrenchPLUS FETs
Table 5.
User-accessible registers
Register[1]
Name
Description
Mask Version default value[2]
option FE
FM
FY
channels select: on/off; see Section 9.5.7
N
00h
00h
00h
21h
10h
1Ch
Read/write registers[3]
01h
CHAN_ONOFF
02h
IN02_MAP
direct input pins IN0 and IN2 mapping;
see Section 9.5.8
Y[4]
03h
IN13_MAP
direct input pins IN1 and IN3 mapping;
see Section 9.5.8
Y[4]
84h
40h
01h
04h
INP_MAP
PWM input pin INP mapping;
see Section 9.5.8
Y[4]
10h
08h
00h
05h
ANDOR_MAP
direct input pin AND/OR operation;
see Section 9.5.8
Y[4]
00h
00h
00h
06h
CURR_MEAS
channel select analog current measurement;
see Section 9.4.2
N
00h
00h
00h
07h
SEL_CURR_TRIP_
CHAN
select current tripping channel;
see Section 9.5.2
Y[4]
00h
00h
00h
08h
CHAN_OT_FAULT_CLR
channel set overtemperature fault clear;
see Section 9.5.1
Y[4]
00h
00h
00h
09h
PWM_SYNC
channel PWM synchronization;
see Section 9.3.4
N
00h
00h
00h
0Ah
PWM_SAM_BEGINEND
channel PWM sample point begin or end;
see Section 9.3.4
N
FFh
FFh
FFh
0Ch
CHAN_WD_MAP
select channel watchdog behavior;
see Section 9.3.3
Y[4]
21h
58h
1Dh
0Dh
WD_TO
watchdog time-out period setting;
see Section 9.3.3
Y[4]
3Fh
3Fh
3Fh
0Eh
CTRL_SET
controller settings; see Section 9.5.5
Y[4]
08h
08h
08h
0Fh
INT_PWM_FREQ
internal PWM frequency setting;
see Section 9.3.4
Y[4]
B6h
BBh
B1h
10h
PWM_DC_CH0
internal PWM duty cycle setting for channel 0
Y[4][5]
FFh
FFh
FFh
Y[4][5]
FFh
FFh
FFh
11h
PWM_DC_CH1
internal PWM duty cycle setting for channel 1;
see Section 9.3.4
12h
PWM_DC_CH2
internal PWM duty cycle setting for channel 2; Y[4][5]
see Section 9.3.4
FFh
FFh
FFh
13h
PWM_DC_CH3
internal PWM duty cycle setting for channel 3; Y[4][5]
see Section 9.3.4
FFh
FFh
FFh
14h
PWM_DC_CH4
internal PWM duty cycle setting for channel 4; Y[4][5]
see Section 9.3.4
FFh
FFh
FFh
15h
PWM_DC_CH5
internal PWM duty cycle setting for channel 5; Y[4][5]
see Section 9.3.4
FFh
FFh
FFh
16h
PWM_DC_CH6
internal PWM duty cycle setting for channel 6; Y[4][5]
see Section 9.3.4
FFh
FFh
FFh
17h
PWM_DC_CH7
internal PWM duty cycle setting for channel 7; Y[4][5]
see Section 9.3.4
FFh
FFh
FFh
18h
OT_TRIPLEV_CH30
overtemperature trip level channels 3 to 0;
see Section 9.5.1
AAh
AAh
AAh
BUK3F00-50WDXX_4
Product data sheet
Y[4]
© NXP B.V. 2008. All rights reserved.
Rev. 04 — 4 September 2008
10 of 52
BUK3F00-50WDxx
NXP Semiconductors
Controller for TrenchPLUS FETs
Table 5.
User-accessible registers …continued
Register[1]
Name
Description
Mask Version default value[2]
option FE
FM
FY
19h
OT_TRIPLEV_CH74
overtemperature trip level channels 7 to 4;
see Section 9.5.1
Y[4]
AAh
AAh
AAh
1Ah
IFSC_CH30
full-scale reference current channels 3 to 0;
see Section 9.5.2
Y[4]
AAh
FFh
FFh
1Bh
IFSC_CH74
full-scale reference current channels 7 to 4;
see Section 9.5.2
Y[4]
AAh
FFh
FFh
1Ch
CURR_TRIPLEV_CH0
current trip level for channel 0;
see Section 9.5.2
N[4]
FFh
FFh
FFh
1Dh
CURR_TRIPLEV_CH1
current trip level for channel 1;
see Section 9.5.2
N[4]
FFh
FFh
FFh
1Eh
CURR_TRIPLEV_CH2
current trip level for channel 2;
see Section 9.5.2
N[4]
FFh
FFh
FFh
1Fh
CURR_TRIPLEV_CH3
current trip level for channel 3;
see Section 9.5.2
N[4]
FFh
FFh
FFh
20h
CURR_TRIPLEV_CH4
current trip level for channel 4;
see Section 9.5.2
N[4]
FFh
FFh
FFh
21h
CURR_TRIPLEV_CH5
current trip level for channel 5;
see Section 9.5.2
N[4]
FFh
FFh
FFh
22h
CURR_TRIPLEV_CH6
current trip level for channel 6;
see Section 9.5.2
N[4]
FFh
FFh
FFh
23h
CURR_TRIPLEV_CH7
current trip level for channel 7;
see Section 9.5.2
N[4]
FFh
FFh
FFh
24h
IRQ_MAP
interrupt request mapping; see Section 9.5.2
Y[4]
04h
19h
00h
25h
CURR_TRIP_
BLANKTIME
current trip blanking time; see Section 9.5.2
Y[4]
2Fh
2Fh
2Fh
26h
OLDET_ONOFF
off-state open-circuit detection;
see Section 9.5.6
N
FFh
FFh
FFh
27h
READBACK
register and diagnostic read back;
see Section 9.3.2
N
30h
30h
30h
28h
IRQ_CHAN_MAP
interrupt generating channels;
see Section 9.3.5
N[4]
FFh
FFh
FFh
Write-only registers[6]
29h
CLEAR_CHAN_INTN
clear channels and interrupt; see Section 11.1
2Ah
CLEAR_WD
clear watchdog state; see Section 11.1
Read-only
registers[7]
30h
DIAG_BASIC
basic diagnostics; see Section 11.2
31h
DIAG_CTRL
controller diagnostics; see Section 11.2
32h
ISR
interrupt status register; see Section 11.2
33h
VERSION
device version number; see Section 11.2
34h
DIAG_CHAN_01
VOUTHIGH and VOUTLOW states[8];
see Section 11.2
35h
DIAG_CHAN_02
TSNSOPEN signal state[9]; see Section 11.2
38h
DIAG_DETAIL_CH0
detail diagnostics; channel 0; see Section 11.2
39h
DIAG_DETAIL_CH1
detail diagnostics; channel 1; see Section 11.2
BUK3F00-50WDXX_4
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 04 — 4 September 2008
11 of 52
BUK3F00-50WDxx
NXP Semiconductors
Controller for TrenchPLUS FETs
Table 5.
User-accessible registers …continued
Register[1]
Name
Description
3Ah
DIAG_DETAIL_CH2
detail diagnostics; channel 2; see Section 11.2
3Bh
DIAG_DETAIL_CH3
detail diagnostics; channel 3; see Section 11.2
3Ch
DIAG_DETAIL_CH4
detail diagnostics; channel 4; see Section 11.2
3Dh
DIAG_DETAIL_CH5
detail diagnostics; channel 5; see Section 11.2
3Eh
DIAG_DETAIL_CH6
detail diagnostics; channel 6; see Section 11.2
3Fh
DIAG_DETAIL_CH7
detail diagnostics; channel 7; see Section 11.2
Mask Version default value[2]
option FE
FM
FY
[1]
This column denotes either the address used to write to the indicated register, or the data sent to register READBACK (27h) to read
back from the indicated register.
[2]
Default values for read/write registers are either fixed or programmable as mask options for individual types.
[3]
8-bit read/write registers store settings that control the behavior of the device. Default values are stored at power-on reset and data can
be changed via SPI-bus communication. To help provide security of operation these registers can also be read back.
[4]
Another metal mask option is available, which means that WRITE_PROTECT is set. CHAN_WD_MAP and WD_TO registers are
write-protected by this option. The other registers indicated will be reloaded with default values if an SPI watchdog time-out occurs.
[5]
Only bit 7 is mask programmable.
[6]
8-bit write-only registers clear tripped channels, interrupt and watchdog states when data is written. The values are not stored and
cannot be read back.
[7]
16-bit read-only registers contain data about the state of the device for diagnostic use. Data cannot be written to these registers.
[8]
VOUTHIGH: high-side FET is in on-state for overcurrent protection (> Vth(on)(bat-KEL)).
VOUTLOW: high-side FET output voltage is below the voltage required for open-circuit detection (< Vdet(oc)off).
[9]
TSNSOPEN: temperature sensor open-circuit.
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9.3.2 Serial Peripheral Interface (SPI)
The SPI is used for communication with a controller and provides control and diagnostic
functions. The device is configured as an SPI slave.
The interface consists of SPI Chip Select (SCSN), Serial Clock (SCLK), Serial Data In
(SDI) and Serial Data Out (SDO). SPI communication is enabled when SCSN is set LOW.
Data is shifted out to pin SDO on the SCLK rising edge. The data shifted out depends on
which register is addressed by register READBACK (27h). Data is shifted in from pin SDI
on the SCLK falling edge.
The controller can be timed to send data to SDI on the SCLK rising edge with data valid
on the falling edge. Data is valid for reading on the falling edge. For full timing
requirements; see Table 25 “Recommended operating conditions” and Figure 9 “SPI
timing definitions”.
SPI communication uses 16-bit words; see Figure 3. The most significant byte, the
register address byte, is transferred first. The 2 most significant bits of the register address
byte are not used, they must always be logic 0. The 6 least significant bits form the actual
register address.
MSB
0
SPI communication word
high byte
low byte
LSB MSB
0 A A A A A A D D D D D D D D
address
Fig 3.
LSB
data
001aae996
SPI communication format; full 16-bit operation
When SCSN is set HIGH after a 16-bit valid communication, then the SDO output
becomes inactive and goes to high-impedance. The data in the low byte is then
transferred to the address given in the high byte. After this is completed the SPI shift
register is refreshed with the latest contents of the register addressed by the entry in
register READBACK. When 8-bit registers are read, the least significant byte is padded
with 55h.
Data is checked for validity after SCSN goes HIGH. It is valid if the count of SCLK
negative edges is a multiple of 8 and the address part (high byte) of the 16-bit message
contains a valid address. An invalid address will result in a value of 00h being sent on
SDO. To allow time for validity checking, writing data and refreshing the shift register,
SCSN must be disabled (HIGH) for a period tw(SCSN).
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SCSN
SCLK
SDI
MSB
LSB MSB
LSB
SDO
MSB
LSB MSB
LSB
high byte
low byte
001aaf575
Fig 4.
SPI communication frame: full 16-bit operation
To support 8-bit microcontrollers an 8-bit operation is possible; see Figure 5. In this
operation, SCSN is taken HIGH between the 8-bit bytes. SDO is taken HIGH before the
SCLK of the low byte to indicate that the low byte is to be sent.
SCSN
SCLK
SDI
MSB
LSB
MSB
LSB
SDO
MSB
LSB
MSB
LSB
high byte
low byte
001aaf576
Fig 5.
SPI communication frame: 8-bit operation
A number of devices can be daisy chained by connecting the SDO of the first device to the
SDI of the next device and so on; see Figure 6.
All devices have their SCSN inputs connected to the same controller chip select so that
they can be selected together. When n devices are daisy chained, then n SPI 16-bit word
cycles must be executed to program all devices. Daisy chaining cannot be used with 8-bit
SPI operation.
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MCSN
SCSN
SLAVE1
SDI
SDO
MASTER
SCSN
SLAVE2
SDI
SCSN
SLAVE3
SDO
SDI
SDO
MDO
MDI
Fig 6.
001aag750
Daisy chain connection of three ASICs (requires three SPI 16-bit word cycles)
9.3.3 SPI watchdog
The SPI watchdog detects if there is a breakdown in the SPI communication with the
controller. A timer is activated that resets when a valid communication is received. If no
valid SPI communications are received within the specified time-out period, the watchdog
will signal this to the control logic.
The SPI watchdog is enabled either by setting pin WDEN = HIGH or by enabling
watchdog active with bit WD_TO[5]. FET channels can be turned either on or off when a
watchdog time-out occurs as set by register CHAN_WD_MAP. Pin WDTON is set LOW for
a selectable period when a watchdog time-out occurs and can be used as a reset for the
controller. An interrupt on pin INTN can also be set when a watchdog time-out occurs.
Other functions of the device are not changed in Watchdog mode. In particular, if the SPI
fault that caused the condition is resolved, SPI communication would work and
diagnostics could be performed.
See Section 11.1 “Reset for interrupt and SPI watchdog” for details of clearing watchdog
states.
Table 6.
Select channel watchdog behavior register (address 0Ch) bit description
Address
Register
Bit
0Ch
CHAN_WD_MAP[1]
7 to 0 behavior when watchdog time-out occurs in individual
channels 7 to 0:
Description
1 = turn selected channel on[2]
0 = turn selected channel off
[1]
A metal mask option WRITE_PROTECT is available, which means that registers are write protected.
[2]
Provided channel is not mapped to a direct input pin. If channel is mapped to a direct input pin, then the
channel will only turn on if the direct input pin is HIGH.
Table 7.
Watchdog time-out period setting register (address 0Dh) bit description
Address
Register
Bit
Description
0Dh
WD_TO
7 to 6
not used
5
enable watchdog
4 to 0
watchdog time-out period; see Table 8
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Table 8.
Watchdog time-out period
Given times are valid for nominal master clock frequency.
Time-out period
Value
Time
Value
Time
Value
Time
Value
Time
00h
1.0 ms
08h
4.1 ms
10h
16 ms
18h
66 ms
01h
1.3 ms
09h
5.1 ms
11h
20 ms
19h
82 ms
02h
1.5 ms
0Ah
6.1 ms
12h
25 ms
1Ah
98 ms
03h
1.8 ms
0Bh
7.2 ms
13h
29 ms
1Bh
115 ms
04h
2.0 ms
0Ch
8.2 ms
14h
33 ms
1Ch
131 ms
05h
2.6 ms
0Dh
10 ms
15h
41 ms
1Dh
164 ms
06h
3.1 ms
0Eh
12 ms
16h
49 ms
1Eh
197 ms
07h
3.6 ms
0Fh
14 ms
17h
57 ms
1Fh
229 ms
9.3.4 Pulse-Width Modulation (PWM)
PWM can be implemented on selected channels by either an internally generated signal
or an externally connected signal.
For the internally generated signal, it is possible to select frequency and duty cycle and to
synchronize the selected channels. The internally generated signal is used when the duty
cycle is set to less than 100 %. For both internal and external PWM signals it is possible to
specify the point at which the FET current is sampled in the PWM period.
An external PWM signal can be connected to the input pin INP (intended for normal PWM
operation) or pins IN0 to IN3 (intended for fail-safe operation). The required channels are
then mapped accordingly.
Table 9.
PWM setting registers (addresses 09h, 0Ah, 0Fh, 10h to 17h) bit description
Address
Register
Bit
09h
PWM_SYNC[1]
Description
7 to 0 PWM synchronization in individual channels 7 to 0:
1 = selected channel synchronized to previous channel in this mode
0 = selected channel one eighth of internal PWM cycle out of phase
0Ah
PWM_SAM_
BEGINEND
7 to 0 PWM sample begin or end in individual channels 7 to 0[2]:
1 = selected channel set to end
0 = selected channel set to start
INT_PWM_FREQ[3]
0Fh
7 to 0 internal PWM frequency setting for all channels:
00h to 3Fh: f = {code + 01h} × 0.125 Hz, from 0.125 Hz to 8.0 Hz in 0.125 Hz
steps
40h to 7Fh: f = {code − 3Fh} × 0.5 Hz, from 0.5 Hz to 32.0 Hz, in 0.5 Hz steps
80h to BFh: f = {code − 7Fh} × 2.0 Hz, from 2.0 Hz to 128.0 Hz, in 2.0 Hz steps
C0h to FFh: f = {code − BFh} × 8.0 Hz, from 8.0 Hz to 512.0 Hz, in 8.0 Hz steps
10h to 17h
PWM_DC_CHn[3]
7 to 0 internal PWM duty cycle for specified channel 7 to 0; duty cycle δ = (n + 1) / 256,
where n = decimal number set in register
[1]
If channels are run out-of-phase each will be staggered by one eighth of a PWM cycle. When more than one channel is selected by this
command then the master signal is the channel with the lowest number. This does not apply to the external PWM signal on pin INP.
[2]
Controls the point of the on-time at which the current is sampled for digital current measurement. Only operates when duty cycle is set
to < 100 % or channel is mapped to pin INP.
[3]
A metal mask option WRITE_PROTECT is available which means that this register is reloaded with the default value if an SPI watchdog
time-out occurs.
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The PWM frequency can be monitored by making this an output on pin PWMMON. This is
a controller setting; see Section 9.5.5 “Controller settings”.
9.3.5 Interrupt
An interrupt can be generated to notify a controller of an error condition. An interrupt will
set pin INTN = LOW. Register settings define which faults can generate an interrupt and
which FET channels can generate an interrupt for these faults.
Table 10.
Interrupt setting registers (addresses 24h, 28h) bit description
Address
Register
24h
IRQ_MAP[1]
Bit
Description
interrupt request mapping; for each bit:
1 = INTN active
0 = INTN not active
28h
IRQ_CHAN_MAP[1]
7
invalid SPI communication
6
open-circuit
5
controller fault (charge pump fault or VBAT low)
4
temperature sensor diode open-circuit
3
watchdog time-out
2
channel overcurrent (threshold reached or exceeded)
1
channel overtemperature (threshold exceeded)
0
channel tripped under fault condition
7 to 0
interrupt generation in individual channels 7 to 0:
1 = selected channel can generate interrupt
0 = selected channel cannot generate interrupt
[1]
A metal mask option WRITE_PROTECT is available, which means that this register is reloaded with the
default value if an SPI watchdog time-out occurs.
When an interrupt is generated, data in the interrupt status register will indicate the cause.
See Section 11.1 “Reset for interrupt and SPI watchdog” for details of reading and
clearing interrupt data.
9.4 Current measurement
The current measurement is able to monitor the current from the sense connections of the
TrenchPLUS FETs. This is achieved by using one current measurement circuit for each
channel. The current measurement circuits control conditions at the sense pin of each
FET channel and can produce either an analog or digital measurement output. The digital
output can be read by a controller.
The current measurement circuit monitors the sense current according to the sense ratio
of the TrenchPLUS FET. This ratio is only valid when the sense and main FETs of the
TrenchPLUS device are fully active with VGS at about 4 V or greater, and with the same
VGS.
9.4.1 Current measurement circuits
For FET channels configured as high-side switches, the sense current is pulled from the
sense connection. This current is adjusted until the voltage measured at the FET pin
kelvin is the same as that measured at the FET pin sense. Since the main and sense
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devices have common drain connections, the VDS of the two devices are equal, and the
correct sense current is being pulled. Current measurement is only possible when the
voltage on pin KELVIN is above the Vth(on)(bat-KEL) threshold.
9.4.2 Analog current measurement output
An analog current can be output on pin IMEAS that is proportional to the sense current
measured on a selected FET channel. Any single channel can be multiplexed to this
output at a time.
The accuracy and resolution of analog current measurement is determined by the voltage
across the RIMEAS resistor with the measurement output current and the measurement
range used. The measurement current is given by Imeas = (ISENSE / Imeas(ADC)(fs)) × 100 µA,
where ISENSE is the FET sense current and Imeas(ADC)(fs) is the set full-scale current for the
measurement range. For reliable current measurement, the voltage on pin IMEAS must
be less than the measurement supply voltage on pin VCC(MEASC). A resistor value giving
high resolution at low measurement output current (for example, up to Imeas(ADC)(fs)) may
not provide the range for high measurement output current (for example, up to
8 × Imeas(ADC)(fs)). Conversely, a value giving the range for high measurement current will
give less resolution for low measurement current.
When the selected channel uses PWM, the analog measurement is able to follow the
switched waveform, except when the duty cycle is very low, and high-side FETs are in the
turn-on state. The voltage on pin IMEAS is limited just below the measurement supply
voltage.
Table 11.
Analog current channel selection register (address 06h) bit description
Address
Register
Bit
Description
06h
CURR_MEAS
7 to 4
not used; must be set to logic 0
3
current measurement setting:
1 = enables current measurement in selected channel
0 = disables current measurement in all channels
2 to 0
selects measurement channel; binary value corresponds
to channel number (0 to 7)
9.4.3 Digital current measurement output
8-bit successive approximation ADCs are used to measure the sense currents of the FET
channels. The measured values are only considered valid when the FET has been on for
the full conversion cycle. Digital measurements are stored and can be read by a controller.
The reading from the ADC may not indicate zero if the channel is requested off. If PWM is
not selected, the values are stored every ADC cycle. For PWM the digital measurement
can be sampled at the start or end of the on time.
The ADC reading, up to the maximum 255 bits, is given by:
reading = 255 × (ISENSE / Imeas(ADC)(fs)) × (50 µA / IIREFCURR), where IIREFCURR is the
current through the current reference resistor (RIREFCURR). At IIREFCURR = 50 µA this
equation simplifies to give a direct relationship with the analog measurement current.
9.4.4 Low battery supply voltage conditions
The current measurement interface operates at voltages very near the battery voltage. To
permit reasonable headroom in the circuit, the current measurement interface is powered
from the charge pump. The circuit cannot operate correctly when it is close to ground, as
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occurs in very low battery conditions. The current measurement interface may be
non-functional, or may have degraded accuracy under low (out-of-specification) charge
pump conditions.
9.5 TrenchPLUS FET interface
The FET interface provides channel switching (on and off) and protection with the
following features, described in priority order.
9.5.1 Overtemperature protection
Overtemperature protection is adjusted by selecting the trip level of the temperature
sense diode for each channel. To relate this to actual trip temperature, refer to the
specification of the specific TrenchPLUS FET devices. Overtemperature protection can
also be set to auto-reset with hysteresis (to reduce the possibility of repeated resets when
the temperature remains high) or to latch on fault. The device also detects and reports a
fault if the connection to a temperature sense diode is open-circuit.
Table 12.
Overtemperature protection setting registers (addresses 08h, 18h, 19h) bit
description
Address
Register
08h
CHAN_OT_FAULT_ 7 to 0
CLR[1]
overtemperature fault clear in channels 3 to 0:
OT_TRIPLEV_
CH30[1]
set overtemperature trip level in channels 3 to 0 to one
of four voltage trip levels[2]:
Bit
Description
1 = selected channel set to auto reset with hysteresis
0 = selected channel set to latches on fault
18h
00 = 2.31 V
01 = 2.25 V
10 = 2.16 V
11 = 2.00 V
19h
7, 6
channel 3 temperature sense diode threshold voltage
5, 4
channel 2 temperature sense diode threshold voltage
3, 2
channel 1 temperature sense diode threshold voltage
1, 0
channel 0 temperature sense diode threshold voltage
set overtemperature trip level in channels 7 to 4 to one
of four voltage trip levels[2]:
OT_TRIPLEV_
CH74[1]
00 = 2.31 V
01 = 2.25 V
10 = 2.16 V
11 = 2.00 V
7, 6
channel 7 temperature sense diode threshold voltage
5, 4
channel 6 temperature sense diode threshold voltage
3, 2
channel 5 temperature sense diode threshold voltage
1, 0
channel 4 temperature sense diode threshold voltage
[1]
A metal mask option WRITE_PROTECT is available which means that this register is reloaded with the
default value if an SPI watchdog time-out occurs.
[2]
Nominal trip voltages quoted for each trip level. Refer to data sheet for TrenchPLUS FET devices for
equivalent temperature measurement.
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9.5.2 Overcurrent protection
The overcurrent protection on each channel allows for high inrush currents. This
protection also allows for turn-on or transient low battery conditions that can occur with
the configuration of high-side FET switches. Delay time in operating overcurrent protection
is determined by the actual FET.
For high-side switches, FET turn-on is determined when the sense voltage exceeds the
low sense threshold voltage (Vth(sense)low), within 40 µs (nominal), and when the
battery-to-kelvin voltage exceeds the on-state threshold voltage between battery and pin
KELVIN (Vth(on)(bat-KEL)).
The following overcurrent protection is available:
Turn-on overcurrent trip (TONOCH) — For channels configured as high-side switches.
Operates during FET turn-on or transient low battery conditions. The threshold level is a
set multiple of Imeas(ADC)(fs) × (IIREFCURR / 50 µA). This is simplified when IIREFCURR =
50 µA. For low current sense voltage (< 2.5 V) the trip level is below the specified multiple
of Imeas(ADC)(fs). This protection cannot be disabled.
Overcurrent high trip (OCH) — For channels configured as high-side switches. This
does not operate during FET turn-on or transient low battery conditions. The threshold
level is a set multiple of Imeas(ADC)(fs) × (IIREFCURR / 50 µA). This is simplified when
IIREFCURR = 50 µA. This protection cannot be disabled or delayed.
Overcurrent low trip (OCL) — Operates at set currents of the ADC output up to
Imeas(ADC)(fs) with the ADC measurement accuracy. The threshold level is set by register
CURR_TRIPLEV_CHn. This protection can be disabled or delayed.
Table 13.
FET channel protection setting registers (addresses 07h, 1Ah to 23h, 25h) bit
description
Address
Register
Bit
07h
SEL_CURR_TRIP_CHAN[1]
7 to 0 select current tripping for OCL in individual
channels 7 to 0:
Description
1 = selected
0 = not selected
1Ah
IFSC_CH30[1]
set Imeas(ADC)(fs) data bits in channels 3 to 0 to
one of four current trip levels:
00 = 0.5 mA
01 = 1.0 mA
10 = 1.5 mA
11 = 2.0 mA
7, 6
set channel 3 full-scale current bits 1 and 0
5, 4
set channel 2 full-scale current bits 1 and 0
3, 2
set channel 1 full-scale current bits 1 and 0
1, 0
set channel 0 full-scale current bits 1 and 0
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Table 13.
FET channel protection setting registers (addresses 07h, 1Ah to 23h, 25h) bit
description …continued
Address
Register
1Bh
IFSC_CH74[1]
Bit
Description
set Imeas(ADC)(fs) data bits in channels 7 to 4 to
one of four current trip levels:
00 = 0.5 mA
01 = 1.0 mA
10 = 1.5 mA
11 = 2.0 mA
7, 6
set channel 7 full-scale current bits 1 and 0
5, 4
set channel 6 full-scale current bits 1 and 0
3, 2
set channel 5 full-scale current bits 1 and 0
1, 0
set channel 4 full-scale current bits 1 and 0
1Ch to
23h
CURR_TRIPLEV_CHn[1]
7 to 0 overcurrent trip threshold in channels 7 to 0;
each bit represents Imeas(ADC)(fs) / 255
25h
CURR_TRIP_BLANKTIME
7, 6
not used: must be set to logic 0
5 to 0 set overcurrent trip blanking time; see Table 14
[1]
A metal mask option WRITE_PROTECT is available, which means that this register is reloaded with the
default value if an SPI watchdog time-out occurs.
Table 14.
Overcurrent low trip blanking time
Blanking
Value
Time
Value
Time
Value
Time
Value
Time
00h
0 ms
0Ch
0.51 ms
18h
4.1 ms
24h
33 ms
01h
0.08 ms
0Dh
0.64 ms
19h
5.1 ms
25h
41 ms
02h
0.10 ms
0Eh
0.77 ms
1Ah
6.1 ms
26h
49 ms
03h
0.11 ms
0Fh
0.90 ms
1Bh
7.2 ms
27h
57 ms
04h
0.13 ms
10h
1.0 ms
1Ch
8.2 ms
28h
66 ms
05h
0.16 ms
11h
1.3 ms
1Dh
10 ms
29h
82 ms
06h
0.19 ms
12h
1.5 ms
1Eh
12 ms
2Ah
98 ms
07h
0.22 ms
13h
1.8 ms
1Fh
14 ms
2Bh
115 ms
08h
0.26 ms
14h
2.0 ms
20h
16 ms
2Ch
131 ms
09h
0.32 ms
15h
2.6 ms
21h
20 ms
2Dh
164 ms
0Ah
0.38 ms
16h
3.1 ms
22h
25 ms
2Eh
197 ms
0Bh
0.45 ms
17h
3.6 ms
23h
29 ms
2Fh
229 ms
9.5.3 Gate inductive ring-off clamp
For high-side switches an inductive ring-off clamp can provide gate-source voltage to
allow conduction through the FET. This protects the FET by reducing the possibility of high
drain-source voltages when turning off current to an inductive load. The gate is initially set
to the source voltage to turn the FET off. During turn-off an inductive load will force the
source voltage negative and the gate will follow this until the voltage between gate and
ground reaches the inductive ring-off clamping voltage VCL. As the source voltage
continues negative, the gate-to-source voltage will increase, turning the FET on and
allowing conduction through the FET and preventing excessive voltage between drain and
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source. The negative voltage on the source then forces current in the inductive load to
reduce rapidly to zero. As the source voltage returns to ground, the gate-source voltage
becomes zero and the FET is turned off.
9.5.4 Loss-of-ground protection
A loss-of-ground condition can occur if the ground connection for the circuit is
disconnected with the load ground still connected. With the FET off, it is possible for the
ground voltage to drift up to battery voltage with the FET source voltage still held at
ground. A resistance between pins GATE and KELVIN will hold the FET off provided the
inductive ring-off clamping voltage VCL between gate and ground is not exceeded,
otherwise the FET will start to turn on. Hence, loss of ground protection can only be
guaranteed when VBAT < |VCL|.
9.5.5 Controller settings
It is possible to select a low switching rate for high-side switches at the beginning of
turn-on and at the end of turn-off. This switching option improves EMC in the high-side
switching application.
The PWM frequency can be monitored on pin PWMMON. This output has a 50 % duty
cycle.
Table 15.
Controller settings register (address 0Eh) bit description
Address
Register
Bit
Description
0Eh
CTRL_SET[1]
7 to 4
not applicable; set to logic 0
3
sets switching rate of turn-on and turn-off:
1 = low switching rate[2]
0 = high switching rate
2
PWM signal on pin PWMMON:
1 = available
0 = not available[3]
1 to 0
not used; must be set to logic 0
[1]
A metal mask option WRITE_PROTECT is available which means that this register is reloaded with the
default value if an SPI watchdog time-out occurs.
[2]
If the FIXED_GATE_SLEW_RATE setting is not set, the low switching rate is only set at the start of turn-on
and turn-off; see Section 10 “Fixed functional settings”.
[3]
When signal not available, this pin goes to 0 V.
9.5.6 Open-circuit detection
Open-circuit is normally detected when switches are in the on-state. The ADC checks that
at least a minimal current is flowing through the sense circuit. The threshold level is
determined by the setting DIG_OLTH[3:0] and is a mask option.
For high-side switches it is possible to detect an open-circuit in the off-state. The FET
kelvin source voltage is monitored with a current Idet(oc)off and an open-circuit is reported if
the threshold voltage Vdet(oc)off is exceeded after a nominal 192 µs delay. This off-state
open-circuit detection is independent of on-state open-circuit detection. For high-side
switches in the off-state, it is also possible to detect when the voltage between pin KELVIN
and VBAT is less than Vth(on)(bat-KEL) (a short-circuit).
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Controller for TrenchPLUS FETs
Table 16.
Off-state open-circuit detection register (address 26h) bit description
Address Register
Bit
Description
OLDET_ONOFF 7 to 0 off-state open-circuit detection[1] in individual channels 7 to 0:
26h
1 = off-state open-circuit detection enabled in selected
channel
0 = off-state open-circuit detection disabled in selected
channel
[1]
For high-side switches only.
9.5.7 Channel selection
Channel selection allows the FET channels to be switched on directly.
Table 17.
Channel selection register (address 01h) bit description
Address
Register
Bit
Description
01h
CHAN_ONOFF
7 to 0
direct switch-on of individual channels 7 to 0:
1 = selected channel on
0 = selected channel off
9.5.8 Mapping channels for direct channel control and PWM
Channels can be mapped to the input pin INP (intended for an external PWM signal) or to
pins IN0 to IN3 for direct control (intended for fail-safe channel control by connection to
VCC(LOG)EXT and GND, or an external PWM signal). All channels (0 to 7) can be mapped
to pin INP. Channels 0 to 3 can be mapped to pins IN0 and IN1. Channels 4 to 7 can be
mapped to pins IN2 and IN3. Input pins IN0 plus IN1 and IN2 plus IN3 are combined
according to the AND/OR operation. If a channel is switched on (by register
CHAN_ONOFF), the channel is switched on irrespective of the state on the direct input
pins IN0 to IN3; see Section 9.5.7.
Table 18.
Channel selection and pin mapping register (addresses 02h to 05h) bit
description
Address
Register
02h
IN02_MAP[1][2]
Bit
Description
direct input pins IN0 and IN2 mapping:
1 = mapped
0 = not mapped
03h
7 to 4
map individual channels 7 to 4 to pin IN2
3 to 0
map individual channels 3 to 0 to pin IN0
IN13_MAP[1][2]
direct input pins IN1 and IN3 mapping:
1 = mapped
0 = not mapped
7 to 4
04h
INP_MAP[2]
map individual channels 7 to 4 to pin IN3
3 to 0
map individual channels 3 to 0 to pin IN1
7 to 0
direct input pin INP map channels 7 to 0:
1 = mapped
0 = not mapped
BUK3F00-50WDXX_4
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Controller for TrenchPLUS FETs
Table 18.
Channel selection and pin mapping register (addresses 02h to 05h) bit
description …continued
Address
Register
05h
ANDOR_MAP[1]
Bit
Description
direct input pin AND/OR operation
7 to 4
direct input AND/OR operation for individual
channels 7 to 4:
1 = pin IN2 AND pin IN3
0 = pin IN2 OR pin IN3
3 to 0
direct input AND/OR operation for individual
channels 3 to 0:
1 = pin IN0 AND pin IN1
0 = pin IN0 OR pin IN1
[1]
A metal mask option WRITE_PROTECT is available, which means that these registers are reloaded with
the default value if an SPI watchdog time-out occurs.
[2]
In Watchdog mode; pins IN0 to IN3 reset channel faults (such as short-circuit) when the pin is set to LOW;
Pin INP does not reset channel faults. Hence, it is not recommended that an external PWM signal is
connected to pins IN0 to IN3 for normal operation.
9.5.9 FET channel on/off control
Each FET channel can be switched by a request from different sources, the logical
relationship between these sources is shown in Figure 7.
watchdog
timeout
CHAN_ONOFFn
PWM_DC_CHn
IN02_MAPn
IN0,IN2
1
IN13_MAPn
IN1,IN3
0
0
DIAG_DETAIL_CH0
ONn
1
ANDOR_MAPn
INP_MAPn
INP
CHAN_WD_MAPn
Fig 7.
001aaf053
FET channel on/off request logic
9.5.10 Power dissipation
The FET interface comprises a significant part of the BUK3F00-50WD thermal budget.
The dissipation is caused by the regulation of the SENSE pin voltage while sinking the
sense current. The dissipation, per channel, can be estimated from the product of ISENSE
and VBAT. Special care should be taken at high battery voltages that the power dissipation
does not cause the device to overheat.
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Controller for TrenchPLUS FETs
9.5.11 Trip and retry
This automatically handles short duration OCH, TONOCH and OCL faults. However,
switching into a short-circuit imposes considerable stress on the MOSFET and may
reduce its life. The user must ensure that the effects are fully evaluated before
implementation. If there is any doubt, then trip and retry should not be used.
If trip and retry is used and a channel still trips off, then the channel should not be turned
on again before the fault has been removed. This may require a lock-out feature in the
controlling software.
The settings for trip and retry are given in Table 19 “Protected settings”.
9.5.12 Trip-latch
The faults listed will trip-latch a channel: this will not allow the channel to turn on unless
the latch is cleared.
Overtemperature — with auto-reset turned off.
Analog overcurrent — with no retries allowed.
Turn-on overcurrent HIGH — (high-side switches only) with no retries allowed.
Overcurrent LOW — with no retries allowed and OCL tripping enabled.
To clear a channel trip-latch condition; see Section 11.1 “Reset for interrupt and SPI
watchdog”.
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Controller for TrenchPLUS FETs
10. Fixed functional settings
A number of settings are fixed mask options. These settings do not have a register
address and cannot be read or changed by the user.
Table 19.
Protected settings
Name
Bit
DIG_OLTH
Description
open-circuit threshold level; 8-bit register
7 to 4
not applicable
3 to 0
high side: (0000) b3, b2, b1, b0
DIG_FET
channel tripping behavior and filter times
8, 7
Version setting
values
FE
FM
FY
23h
23h
23h
0C1h 0C1h 0C1h
tlow(bat) setting:
00/11 = 128 µs (min) to 144 µs (max)
01 = 256 µs (min) to 288 µs (max)
10 = 512 µs (min) to 576 µs (max)
6, 5
thigh(bat) setting:
00/11 = 16 µs (min) to 20 µs (max)
01 = 32 µs (min) to 40 µs (max)
10 = 64 µs (min) to 80 µs (max)
4
high-side channels on low VBAT:
1 = no trip
0 = trip
3, 2
trip channel output filter time:
00 = immediate
1, 0
TONOCH filter time (in turn-on state):
00 = immediate
01 = 1.0 µs
10 = 1.5 µs
11 = 2.0 µs (min) to 3.0 µs (max)
CHAN_ALLOW_RETRY
7 to 0 allow trip and retry after OCH, TONOCH or OCL faults select
channels 7 to 0:
FFh
FFh
FFh
1Bh
1Bh
1Bh
1b
1b
1b
1 = allowed
0 = not allowed
RETRY_SETTINGS
trip retry delay and number of retries
4, 3
wait time before retry:
00 = 64 µs (min) to 128 µs (max)
01 = 192 µs (min) to 256 µs (max)
10 = 320 µs (min) to 384 µs (max)
11 = 448 µs (min) to 512 µs (max)
2 to 0 number of retries, set binary number
WRITE_PROTECT
0
write protect (registers WD_TO and CHAN_WD_MAP)[1]:
1 = no write access
0 = write access
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Controller for TrenchPLUS FETs
Table 19.
Protected settings …continued
Name
WDPN_LOW_TIME
VSBATLOW_DEB_EN
Bit
Description
Version setting
values
7 to 0 watchdog time-out LOW time pulse (on pin WDTON)
0
00h = 1.0 ms
0Bh = 7.2 ms
16h = 49 ms
01h = 1.3 ms
0Ch = 8.2 ms
17h = 57 ms
02h = 1.5 ms
0Dh = 10 ms
18h = 66 ms
03h = 1.8 ms
0Eh = 12 ms
19h = 82 ms
04h = 2.0 ms
0Fh = 14 ms
1Ah = 98 ms
05h = 2.6 ms
10h = 16 ms
1Bh = 115 ms
06h = 3.1 ms
11h = 20 ms
1Ch = 131 ms
07h = 3.6 ms
12h = 25 ms
1Dh = 164 ms
08h = 4.1 ms
13h = 29 ms
1Eh = 197 ms
09h = 5.1 ms
14h = 33 ms
1Fh = 229 ms
0Ah = 6.1 ms
15h = 41 ms
debounce on VBAT low signal:
FE
FM
FY
00h
00h
00h
0b
0b
0b
1 = debounce enabled
0 = debounce disabled
NXIFSC_CH0
-
channel 0: ratio OCH and TONOCH trip level to Imeas(ADC)(fs)
6
6
6
NXIFSC_CH1
-
channel 1: ratio OCH and TONOCH trip level to Imeas(ADC)(fs)
6
6
6
NXIFSC_CH2
-
channel 2: ratio OCH and TONOCH trip level to Imeas(ADC)(fs)
6
6
6
NXIFSC_CH3
-
channel 3: ratio OCH and TONOCH trip level to Imeas(ADC)(fs)
6
6
6
NXIFSC_CH4
-
channel 4: ratio OCH and TONOCH trip level to Imeas(ADC)(fs)
3
6
6
NXIFSC_CH5
-
channel 5: ratio OCH and TONOCH trip level to Imeas(ADC)(fs)
6
6
6
NXIFSC_CH6
-
channel 6: ratio OCH and TONOCH trip level to Imeas(ADC)(fs)
6
6
6
NXIFSC_CH7
-
channel 7: ratio OCH and TONOCH trip level to Imeas(ADC)(fs)
6
6
6
HL_CH0 to HL_CH7
-
channel 0 to 7: FET configuration (high or low side)
high
high
high
FIXED_GATE_SLEW_RATE
-
rising and falling slew rates have fixed values during gate
turn-on
no
yes
yes
[1]
Also sets default register reload for watchdog time-out.
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Controller for TrenchPLUS FETs
11. Diagnostic functions
11.1 Reset for interrupt and SPI watchdog
An interrupt or SPI watchdog time-out can be reset by writing to the relevant write-only
register. Values are not stored and cannot be read back.
Table 20.
Write-only (for reset) registers (addresses 29h, 2Ah) bit description
Address
Register
29h
CLEAR_CHAN_INTN 7 to 0 clears all channels (7 to 0) and interrupt:
Bit
Description
writing any value other than 00h to this register
clears the interrupt and ISR register
writing a logic 1 to any bit in this register clears the
interrupt and ISR register AND clears the trip latch
(resetting the retry register) for that specific channel
2Ah
CLEAR_WD
7 to 0 clear watchdog state:
writing any value to this register clears SPI Watchdog
mode
11.2 Diagnostic data
Diagnostic data can be obtained by reading data from the relevant 16-bit read-only
registers. Send the register address as data to register READBACK (27h).
Table 21.
Read-only (for diagnostic data) registers (addresses 30h to 35h, 38h to 3Fh) bit description
Address
Register
30h
DIAG_BASIC
31h
Bit
Description
basic diagnostics
15, 14
channel 7 basic diagnostics
13, 12
channel 6 basic diagnostics
11, 10
channel 5 basic diagnostics
9, 8
channel 4 basic diagnostics
7, 6
channel 3 basic diagnostics
5, 4
channel 2 basic diagnostics
3, 2
channel 1 basic diagnostics
1, 0
channel 0 basic diagnostics
DIAG_CTRL
Bit latches
[1]
controller diagnostics
15
SPI error: wrong number of bits
yes[2]
14
VBAT low
yes[3][4]
13
SPI error: invalid address
yes[2]
12
charge pump fault
yes[3][4]
11
not used
10
logic reset has occurred
yes[3]
9
watchdog time-out has occurred
yes[3]
8
watchdog is enabled
7 to 0
channel configuration:
1 = high side
0 = low side
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Controller for TrenchPLUS FETs
Table 21.
Read-only (for diagnostic data) registers (addresses 30h to 35h, 38h to 3Fh) bit description …continued
Address
Register
32h
ISR
Bit
14
yes
[8]
yes
[8][12]
yes
channel tripped by controller (low battery)
VBAT too low
[8]
yes
charge pump fault
[8]
yes
watchdog time-out
[9]
yes
yes
9
wrong number of bits in SPI communication
[10]
8
invalid address in SPI communication
[10]
yes
[6]
yes
[6][11][12]
yes
[6][7]
yes
7 to 5
4
channel index generating interrupt (binary number)
channel tripped by overcurrent
3
channel tripped by overtemperature
2
channel overcurrent
[6][11][13]
yes
channel open-circuit
[6][14]
yes
channel temperature sensor diode open-circuit
[6][15]
yes
1
0
VERSION
device version number
15 to 8
main version
[16]
7 to 0
sub-version code
[17]
DIAG_CHAN_01
high-side FET on-state and open-circuit detection
15 to 8
high-side FET in on-state for channels 7 to 0
[18]
7 to 0
high-side FET open-circuit detected on channels 7
to 0
[18]
DIAG_CHAN_02
38h to 3Fh
logic reset has occurred
[6][7]
12
10
35h
channel overtemperature
13
11
34h
Bit latches
[5]
interrupt status
15
33h
Description
TSNSOPEN and overtemperature detection states
15 to 8
value of TSNSOPEN signal for channels 7 to 0
7 to 0
not used
DIAG_DETAIL_CHn
detail diagnostics channels 7 to 0
15 to 8
digital current measurement
7
channel temperature sensor open-circuit
[18]
yes
6
open-circuit load detected
[18]
yes
5
not used
4
channel overcurrent
[13][18]
yes
yes
3
channel overtemperature
[18]
2
channel tripped by controller (low battery)
[18]
yes
1
shorted output to VBAT
[18]
yes
0
channel requested by user
[1]
Values for each channel are (in priority order):
00 = no controller fault.
10 = channel selected (normal or PWM). Applies during the PWM period when the channel and PWM are both selected.
01 = channel not selected but controller fault (low battery). This is latched, only cleared by reading DIAG_CTRL or selecting channel.
11 = channel selected but tripped off. Applies when the channel is selected but tripped by overcurrent or overtemperature.
[2]
Bit is cleared when register is read or by writing to CLEAR_CHAN_INTN (provided SPI fault is mapped to INTN).
[3]
Bit is cleared when register is read or by writing to CLEAR_CHAN_INTN (provided controller fault is mapped to INTN).
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Controller for TrenchPLUS FETs
[4]
When bit is cleared, value 01 in DIAG_BASIC is also cleared.
[5]
The bits in this register latch when an interrupt is generated by the given source, once captured no new data is latched. The register is
cleared by writing to CLEAR_CHAN_INTN.
[6]
Requires specific channel mapped in IRQ_CHAN_MAP.
[7]
Requires channel overtemperature to be mapped in IRQ_MAP.
[8]
Requires controller fault to be mapped in IRQ_MAP.
[9]
Requires watchdog time-out to be mapped in IRQ_MAP.
[10] Requires SPI error to be mapped in IRQ_MAP.
[11] Requires channel overcurrent to be mapped in IRQ_MAP.
[12] Mapping channel tripped in IRQ_MAP also enables this bit.
[13] If OCL protection is disabled and current exceeds the OCL level, the register bit is still set and an interrupt generated (provided channel
overcurrent is mapped in IRQ_MAP). This is also true if OCL is delayed and the current exceeds the OCL level during the delay period.
[14] Requires open-circuit detected to be mapped in IRQ_MAP.
[15] Requires temperature sensor diode open-circuit to be mapped in IRQ_MAP.
[16] Denotes main product version:
50WDFE: 0Ah
Other types: 0Bh
[17] Denotes type or mask version:
50WDFE: 02
50WDFM: 01
50WDFY: 02
Versions may change if mask changes occur during production.
[18] Bit is cleared when register is read or by writing to CLEAR_CHAN_INTN.
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Controller for TrenchPLUS FETs
12. Application design-in information
VBAT
Crf
Cflt(CP)
Cstg
VOLTAGE
REGULATOR
Rflt(CP)
VBAT
CPN
CPP
CT
Rflt
VBAT(CP)
Cp
Cmod
supply
Cflt(CP)
ANODE
VCC(MOD)
VCC(DIGC)
GATE
Cflt
TrenchPLUS
FET (8×)
Cgate(comp)
VCC(LOG)EXT
SENSE
RINTN
WDEN
WDTON
ENABLE
TIMEOUT
MICROCONTROLLER RESET
EN
INTN
INTERRUPT
serial
periheral
interface
RWDTON
ENABLE
CLOCK
DATA OUT
DATA IN
SCSN
SCLK
SDI
SDO
SUPPLY
MEASURE
VCC(MEASC)
KELVIN
BUK3F0050WDxx
RL
IREFCURR
IREFTEMP
PWMMON
RIREFTEMP
RIREFCURR
RIMEAS
GND
ground
GND(CP)
IMEAS
GND(DIGC)
A/D
Crf
ensure potential
between grounds < 0.5 V
001aaf240
Fig 8.
Application schematic
The charge pump pin VBAT(CP) can be connected in any one of the following ways:
• Connected directly to pin VBAT and the battery supply.
• Connected through the internal resistor to pin VBAT and the battery supply.
• Connected through the internal resistor to pin VBAT and a filter circuit to the battery
supply (as shown in Figure 8).
The method used depends on how important reducing the effect of charge pump noise is
for the application circuit.
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Controller for TrenchPLUS FETs
Table 22.
External component requirements
Component Remark
Value
Charge pump capacitors
Cp
non-electrolytic; connect between pins CPP and CPN
20 nF (min)
Cstg
non-electrolytic; connect between pins VBAT(CP) and CT
1 µF (min)
Current reference and measurement resistors
connect between pins IREFTEMP and GND
[1]
24.9 kΩ ± 1 %
RIREFCURR
connect between pins IREFCURR and GND
[2]
24.9 kΩ ± 1 %
RIMEAS
connect between pins IMEAS and GND
for sense currents up to 3 × Imeas(ADC)(fs)
[3]
10 kΩ ± 2 %
for sense currents up to 8 × Imeas(ADC)(fs)
[3]
4.7 kΩ ± 2 %
RIREFTEMP
Digital output pull-up resistors
RINTN
connect between pins INTN and VCC(LOG)EXT
3.3 kΩ (min); 10 kΩ (typ); 100 kΩ (max)
RWDTON
connect between pins WDTON and VCC(LOG)EXT
3.3 kΩ (min); 10 kΩ (typ); 100 kΩ (max)
TrenchPLUS FET sense
Rsense
resistance[4]
Imeas(ADC)(fs) = 0.5 mA
100 Ω (min); 700 Ω (max)
Imeas(ADC)(fs) = 1.0 mA
50 Ω (min); 350 Ω (max)
Imeas(ADC)(fs) = 1.5 mA
33.3 Ω (min); 233.3 Ω (max)
Imeas(ADC)(fs) = 2.0 mA
25 Ω (min); 125 Ω (max)
Module supply decoupling
Cmod
Rflt
Cflt
100 µF ± 20 %
electrolytic
connect between pins VCC(MOD) plus VCC(DIGC) and supply
[5]
10 Ω ± 2 %
non-electrolytic; connect between pins VCC(MOD) plus
VCC(DIGC) and GND
[5]
100 nF ± 5 %
[6]
20 Ω (max)
Optional charge pump filtering
Rflt(CP)
charge pump filter resistor connect between pin VBAT and
battery supply
Cflt(CP)
charge pump filter capacitors connect between pin VBAT and
GND and between Rflt(CP) and GND
100 nF (max)
Optional gate Ciss compensation
Cgate(comp)
1 nF ± 5 %
for FETs with low Ciss
Application circuit decoupling
Crf
value to be determined in the application circuit
-
value to be determined in the application circuit
-
Load resistor
RL
Direct input pin resistors (not shown in Figure 8)
RINP
connect between pins VCC(LOG)EXT, VCC(MOD) and pins IN0 to
IN3 as required.
50 kΩ ± 2 %
[1]
Sets IF to nominal 250 µA.
[2]
Sets IIREFCURR to nominal 50 µA.
[3]
Selection of RIMEAS for sufficient dynamic range is also dependent on voltage of VCC(MEASC). Values quoted assume VCC(MEASC) = 5 V.
[4]
Rsense is the drain-source resistance of the sense cells of the TrenchPLUS FET at the nominal drain current. It can be estimated from
the product of the current-sense ratio and the drain-source resistance of the main FET.
[5]
Pins VCC(MOD) and VCC(DIGC) can each have separate filtering for good decoupling.
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Controller for TrenchPLUS FETs
[6]
If Rflt(CP) is not connected, then connect VBAT directly with a short. If required, the charge pump can also be supplied directly from VBAT.
Table 23.
TrenchPLUS FET connections per channel
Connection
Description
Gate
gate of the output power MOSFET switch
Drain
drain of the output power MOSFET switch
Source
source of the output power MOSFET switch
Kelvin
kelvin source connection for current measurement
Sense
analog current measurement cell of the MOSFET switch (provides input for digital and analog current
measurement)
Anode
temperature sense diode (electrically isolated from other connections)
Cathode
temperature sense diode (electrically isolated from other connections); connect to GND
13. Limiting values
Table 24. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
Ptot
total power dissipation
Tamb ≤ 85 °C
Tj
junction temperature
Tstg
storage temperature
[1]
Min
Max
Unit
-
1
W
−40
+150
°C
−40
+150
°C
−32
+60
V
Power supplies
[2]
VBAT
battery supply voltage
VCC(MOD)
module supply voltage
−0.5
+60
V
VBAT(CP)
charge pump battery supply voltage
−32
+60
V
VCC(DIGC)
digital core supply voltage
−0.5
+60
V
−0.5
+5.5
V
−0.5
+7
V
−0.5
+0.5
V
VCC(LOG)EXT
external logic supply voltage
VCC(MEASC)
measure circuit supply voltage
[3]
∆VVBAT-VBAT(CP) voltage difference between pin VBAT
and pin VBAT(CP)
[4]
Ground levels[5]
∆VGND(bat-cp)
ground voltage difference from battery
to charge pump
GND to GND(CP)
−0.5
+0.5
V
∆VGND(bat-log)
ground voltage difference from battery
to logic
GND to GND(DIGC)
−0.5
+0.5
V
∆VGND(cp-log)
ground voltage difference from charge
pump to logic
GND(CP) to GND(DIGC)
−0.5
+0.5
V
pins GATE, KELVIN, SENSE
−32
+60
V
pin ANODE
−0.5
+7
V
between pins KELVIN and VBAT
−60
+2
V
between KELVIN pins of 2
channels and between SENSE
pins of 2 channels
−60
+60
V
FET connection pins
Vx
∆V
voltage on pin x
voltage difference
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Table 24. Limiting values …continued
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
Min
Max
Unit
pins EN, IN0, IN1, IN2, IN3, INP,
SCLK, SCSN, SDI, WDEN
−1.5
-
V
-
1
mA
corner pins
-
750
V
other pins
-
500
V
-
2
kV
Digital input pins
VI(dig)
digital input voltage
II(dig)
digital input current
Electrostatic discharge voltages
electrostatic discharge voltage
VESD
[6]
CDM
[7]
HBM
[1]
When Tj > 125 °C, the device will function, but electrical parameters may deviate from the specified values.
[2]
Circuits will survive higher transient voltages, provided the clamp rating is not exceeded.
[3]
This limiting value also applies to the open-drain output pins INTN and WDTON.
[4]
Pin VBAT can be connected from battery supply through pin VBAT(CP) and internal resistor.
[5]
All 4 GND pins must be connected together to ground.
[6]
CDM: C = 200 pF according to AEC-Q100-002 and 011.
[7]
HBM: C = 100 pF; R = 1.5 kΩ according to AEC-Q100-002 and 011.
14. Recommended operating conditions
Table 25.
Recommended operating conditions
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VBAT
battery supply voltage
operating
5.5
13
52
V
VBAT(CP)
charge pump battery supply voltage
9
13
52
V
VCC(MOD)
module supply voltage
4.6
13
52
V
VCC(DIGC)
digital core supply voltage
4.6
13
52
V
3.3
5
5.5
V
3.3
5
5.5
V
-
-
100
V/µs
−40
+25
+125
°C
pins KELVIN and SENSE (for
sense current measurement)
VBAT −
2.5
-
VBAT +
0.4
V
Supplies
[1]
VCC(LOG)EXT external logic supply voltage
VCC(MEASC)
SRbat
measure circuit supply voltage
[2]
battery slew rate
General
Tamb
ambient temperature
FET connection pins
VI(cm)
common-mode input voltage
Direct input pins
fPWM(ext)
external PWM frequency
on pin INP
-
-
512
Hz
fsw
switching frequency
on pins IN0, IN1, IN2 and IN3
-
-
512
Hz
SPI timing; see Figure 9
[3]
fSPI
SPI frequency
0
-
3
MHz
tsu(SCSN)
SCSN set-up time
10
-
-
ns
td(SCSN)
SCSN delay time
10
-
-
ns
BUK3F00-50WDXX_4
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 04 — 4 September 2008
34 of 52
BUK3F00-50WDxx
NXP Semiconductors
Controller for TrenchPLUS FETs
Table 25.
Recommended operating conditions …continued
Symbol
Parameter
Min
Typ
Max
Unit
tw(SCSN)
SCSN pulse width
Conditions
2
-
-
µs
tsu(SDI)
SDI set-up time
10
-
-
ns
th(SDI)
SDI hold time
10
-
-
ns
tSCLKH
SCLK HIGH time
50
-
-
ns
tSCLKL
SCLK LOW time
50
-
-
ns
[1]
When VBAT < 9 V, the charge pump cannot be guaranteed to drive the external MOSFETs to achieve their specified RDSon.
[2]
Higher slew rates can give uncontrolled device turn-on, device turn-off or channel switching.
[3]
For SDO output characteristics; see Table 30 “SPI and watchdog characteristics”.
tw(SCSN)
SCSN
tsu(SCSN)
tdis(SDO)
tSCLKH
tsu(SDI)
SCLK
th(SDI)
tSCLKL
td(SCSN)
SDI
tv(SDO)
th(SDO)
SDO
001aaf463
The shaded areas indicate the time that output data is not valid.
Fig 9.
SPI timing definitions
15. Thermal characteristics
Table 26.
Thermal characteristics
Symbol
Parameter
Conditions
Rth(j-a)
thermal resistance from junction to ambient
mounted on single-layer PCB, size
11.43 cm × 7.62 cm (4.5 inch × 3.0 inch)
Typ
Unit
in free air
66
K/W
at 1 m/s
54
K/W
at 2.5 m/s
50
K/W
Rth(j-pcb)
thermal resistance from junction to
printed-circuit board
board cooled by cold plate
23
K/W
Rth(j-c)
thermal resistance from junction to case
case cooled at constant temperature
35
K/W
BUK3F00-50WDXX_4
Product data sheet
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Rev. 04 — 4 September 2008
35 of 52
BUK3F00-50WDxx
NXP Semiconductors
Controller for TrenchPLUS FETs
16. Characteristics
Table 27. Supplies characteristics
VBAT = VCC(MOD) = 13 V; typical values are given at Tamb = 25 °C; limit values are given at Tcase = −40 °C to +125 °C; unless
otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Supplies: pins VBAT, VBAT(CP), VCC(MOD), VCC(LOG)EXT and VCC(MEASC)
Standby and quiescent currents (pin EN = LOW)
Istb(bat)
Istb(mod)
battery standby current
module standby current
VBAT = VBAT(CP) = 52 V
[1][2]
-
1.25 5
µA
VCC(MOD) = VCC(DIGC) = 52 V
[3][2]
-
6.75 15
µA
[4]
-
-
1
µA
-
-
1
µA
[1][5]
3
-
10
mA
[1][5]
-
-
12.5
mA
[3][5]
5
-
10
mA
Iq(log)ext
external logic quiescent
current
VCC(LOG)EXT = 5 V; pins SCSN and WDEN
not connected
Iq(meas)
measure quiescent
current
VCC(MEASC) = 5 V
Operating currents (pin EN = HIGH)
Ioper(bat)
battery operating current VBAT = VBAT(CP) = 13 V;
ISENSE = 2 mA [Imeas(ADC)(fs)]
Ibat(M)
peak battery current
Ioper(mod)
module operating current VCC(MOD) = VCC(DIGC) = 13 V;
ISENSE = 2 mA [Imeas(ADC)(fs)]
Imod(M)
peak module current
VCC(MOD) = VCC(DIGC) = 40 V; ISENSE = 6 ×
2 mA [Imeas(ADC)(fs)]
[3][5]
-
-
12.5
mA
Ilog(ext)M
peak external logic
current
VCC(LOG)EXT = 5 V; pin WDEN = LOW; pin
SDO at 3 MHz; CL = 20 pF
[4]
-
-
450
µA
Ioper(meas)
measure operating
current
VCC(MEASC) = 5 V;
RIREFCURR = RIREFTEMP = 24.9 kΩ
-
-
1.5 ×
IO(meas) + 30
µA
VBAT = VBAT(CP) = 40 V; ISENSE = 6 × 2 mA
[Imeas(ADC)(fs)]
Transient voltages: pins VBAT, VCC(MOD), VCC(LOG)EXT, VBAT(CP), CPP, CPN, CT, GATE, KELVIN, SENSE
VCL
clamping voltage
ICL = 10 mA; tp = 300 µs
67.5 -
80
V
4.7
-
5.2
V
Battery supply: pin VBAT and VBAT(CP)
Normal battery operation
Vth(uv)bat
battery undervoltage
threshold voltage
Vhys(uv)bat
battery undervoltage
hysteresis voltage
Vth(low)bat
battery low threshold
voltage
Vhys(low)bat
HIGH-to-LOW
[6]
LOW-to-HIGH
4.95 -
5.4
V
[6]
140
250
mV
HIGH-to-LOW
[6]
1.85 -
2.15
V
LOW-to-HIGH
[6]
2.1
-
2.4
V
[6]
150
225
300
mV
-
3.0
-
V
8
-
11
V
-
-
10
mA
HIGH-to-LOW
4.1
-
4.55
V
LOW-to-HIGH
4.2
-
4.6
V
battery low hysteresis
voltage
200
Reverse battery operation
VG-bat
IR(bat)
voltage from gate to
battery
VBAT = −4 V
battery reverse current
VBAT = VBAT(CP) = −30 V
VBAT = −30 V
[1]
Module supply: pin VCC(MOD)
Vth(uv)mod
module undervoltage
threshold voltage
BUK3F00-50WDXX_4
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 04 — 4 September 2008
36 of 52
BUK3F00-50WDxx
NXP Semiconductors
Controller for TrenchPLUS FETs
Table 27. Supplies characteristics …continued
VBAT = VCC(MOD) = 13 V; typical values are given at Tamb = 25 °C; limit values are given at Tcase = −40 °C to +125 °C; unless
otherwise specified.
Symbol
Parameter
Conditions
Vhys(uv)mod module undervoltage
hysteresis voltage
Min
Typ
Max
Unit
25
50
130
mV
Reference outputs: pins IREFTEMP and IREFCURR
VO(ref)
reference output voltage
IO(ref)
reference output current
RIREFCURR = RIREFTEMP = 24.9 kΩ
[1]
Total current = IBAT + IBAT(CP).
[2]
Standby currents valid provided VBAT and VCC(MOD) > 9 V.
[3]
Total current = ICC(MOD) + ICC(DIGC).
[4]
Does not include current through pins INTN or WDTON pull-up resistors.
[5]
All channels ON; with FET Crss = 210 pF; fSPI = 3 MHz.
[6]
Monitored on pin VBAT(CP).
1.20 1.24 1.28
V
-
µA
49.8 -
Table 28. Charge pump characteristics
VBAT = VCC(MOD) = 13 V; typical values are given at Tamb = 25 °C; limit values are given at Tcase = −40 °C to +125 °C; unless
otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fosc(cp)
charge pump oscillator frequency VBAT > 5.5 V
400
500
600
kHz
VO(cp)
charge pump output voltage
VBAT = 5.5 V to 9 V
4.5
-
-
V
VBAT > 9 V
6
6.5
7.5
V
Charge pump: pins VBAT(CP), CPP, CPN and CT
tbst(cp)
charge pump boost time
Cstg = 1 µF; VBAT > 5.5 V
-
500
-
µs
Vth(fault)cp
charge pump fault threshold
voltage
HIGH-to-LOW
-
-
3
V
LOW-to-HIGH
2.6
-
-
V
50
150
250
mV
Vhys(fault)cp
charge pump fault hysteresis
voltage
Table 29. Control circuits characteristics
VBAT = VCC(MOD) = 13 V; typical values are given at Tamb = 25 °C; limit values are given at Tcase = −40 °C to +125 °C; unless
otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Digital control input: pin EN
VIL
LOW-level input voltage
1
-
-
V
VIH
HIGH-level input voltage
-
-
2
V
Vhys(I)
input hysteresis voltage
150
-
550
mV
VCL(i)
input clamping voltage
9.5
10.5
11.5
V
Cin
input capacitance
-
10
-
pF
Rpd
pull-down resistance
50
100
250
kΩ
-
-
100
µs
-
1
1.6
ms
-
-
0.4
V
ten
enable time
tdis
disable time
[1]
Interrupt output: pin INTN
VOL
LOW-level output voltage
II = 1.6 mA
BUK3F00-50WDXX_4
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 04 — 4 September 2008
37 of 52
BUK3F00-50WDxx
NXP Semiconductors
Controller for TrenchPLUS FETs
Table 29. Control circuits characteristics …continued
VBAT = VCC(MOD) = 13 V; typical values are given at Tamb = 25 °C; limit values are given at Tcase = −40 °C to +125 °C; unless
otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Direct channel control inputs: pins IN0, IN1, IN2 and IN3
VIL
LOW-level input voltage
1
-
-
V
VIH
HIGH-level input voltage
-
-
2
V
Vhys(I)
input hysteresis voltage
200
-
700
mV
Cin
input capacitance
-
10
-
pF
Rpd
pull-down resistance
50
100
250
kΩ
[1]
The time when both analog and digital circuits are enabled. High-side channels cannot be switched until the charge pump boost time
has also elapsed.
Table 30. SPI and watchdog characteristics
VBAT = VCC(MOD) = 13 V; typical values are given at Tamb = 25 °C; limit values are given at Tcase = −40 °C to +125 °C; unless
otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
SPI input pins SCSN, SCLK, SDI and output pin SDO
VIL
LOW-level input voltage
1
-
-
V
VIH
HIGH-level input voltage
-
-
2
V
Vhys(I)
input hysteresis voltage
200
-
700
mV
Cin
input capacitance
-
10
-
pF
VOL
LOW-level output voltage
II = 1.6 mA
-
-
0.4
V
VOH(log)(ext)
external logic HIGH-level output
voltage
IO = 1 mA
VCC(LOG)EXT − 0.4 -
-
V
Rpd
pull-down resistance
pins SCLK and SDI
50
100
250
kΩ
Rpu
pull-up resistance
pin SCSN
50
100
250
kΩ
th(SDO)
SDO hold time
CL = 200 pF
-
-
100
ns
tv(SDO)
SDO valid time
-
-
116
ns
tdis(SDO)
SDO disable time
-
-
100
ns
Watchdog input pin WDEN and output pin WDTON
VIL
LOW-level input voltage
1
-
-
V
VIH
HIGH-level input voltage
-
-
2
V
Vhys(I)
input hysteresis voltage
200
-
700
mV
VCL(i)
input clamping voltage
9.5
10.5
11.5
V
Cin
input capacitance
-
10
-
pF
Rpu
pull-up resistance
pin WDEN
50
100
250
kΩ
VOL
LOW-level output voltage
IO = 1.6 mA
-
-
0.4
V
∆tto(wd)/tto(wd)
relative watchdog time-out time
variation
pin WDEN = HIGH
0
-
28
%
[1]
[1]
Relative watchdog time-out time variation does not include clock frequency variation.
BUK3F00-50WDXX_4
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 04 — 4 September 2008
38 of 52
BUK3F00-50WDxx
NXP Semiconductors
Controller for TrenchPLUS FETs
Table 31. Pulse-width modulation characteristics
VBAT = VCC(MOD) = 13 V; typical values are given at Tamb = 25 °C; limit values are given at Tcase = −40 °C to +125 °C; unless
otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
−20
-
+20
%
Pulse-width modulator
∆fPWM/fPWM
[1]
relative PWM frequency variation
PWM input: pin INP
VIL
LOW-level input voltage
1
-
-
V
VIH
HIGH-level input voltage
-
-
2
V
Vhys(I)
input hysteresis voltage
200
-
700
mV
VCL(i)
input clamping voltage
9.5
10.5
11.5
V
Cin
input capacitance
-
10
-
pF
Rpd
pull-down resistance
50
100
250
kΩ
PWM output: pin PWMMON
VOL
LOW-level output voltage
II = 1.6 mA
-
-
0.4
V
VOH(log)(ext)
external logic HIGH-level output
voltage
IO = 1 mA
VCC(LOG)EXT − 0.4
-
-
V
[1]
Relative PWM frequency error includes clock frequency variation.
Table 32. Current measurement characteristics
VBAT = VCC(MOD) = 13 V; typical values are given at Tamb = 25 °C; limit values are given at Tcase = −40 °C to +125 °C; unless
otherwise specified.
Symbol Parameter
Current
EADC(I)
Conditions
Min
Typ
Max
Unit
−2
-
+2
bit
−4
-
+4
bit
type 50WDFE
−11
-
+15
bit
other 50WDxx types
−13
-
+13
bit
0.00 × Imeas(ADC)(fs)
-
0
5
µA
0.20 × Imeas(ADC)(fs)
15
20
25
µA
1.00 × Imeas(ADC)(fs)
92.5
102.5
112.5
µA
8.00 × Imeas(ADC)(fs)
660
820
980
µA
measurement[1]
ADC error (current)
all ranges; RIREFCURR = 24.9 kΩ
0.01 × Imeas(ADC)(fs)
0.20 × Imeas(ADC)(fs)
[2]
[3]
0.80 × Imeas(ADC)(fs)
IO(meas)
measure output current
all ranges; VCC(MEASC) = 5 V; RIMEAS = 4.7 kΩ;
RIREFCURR = 24.9 kΩ
[1]
If measured without a FET, then connect a suitable resistor between pins VBAT and SENSE to ensure stability.
[2]
ADC accuracy ensured when VBAT and VCC(MOD) > 9 V.
[3]
ADC used at this level for on-state open-circuit detection.
BUK3F00-50WDXX_4
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 04 — 4 September 2008
39 of 52
BUK3F00-50WDxx
NXP Semiconductors
Controller for TrenchPLUS FETs
Table 33. Gate drive high-side switches characteristics
VBAT = VCC(MOD) = 13 V; typical values are given at Tamb = 25 °C; limit values are given at Tcase = −40 °C to +125 °C; unless
otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max Unit
VBAT = 5.5 V to 9 V
4.0
-
7.5
V
VBAT > 9 V
5.5
6.5
Gate drive for high-side switches
gate-source voltage
VGS
VCL(G)
gate clamping voltage
SRr
rising slew rate
on-state
7.5
V
−28.5 −22.5 −20
V
type 50WDFY
0.25
0.5
0.6
V/µs
other 50WDxx types
0.5
1
1.2
V/µs
0.125 0.25
0.3
V/µs
0.25
0.5
0.6
V/µs
type 50WDFY
0.25
0.5
0.6
V/µs
other 50WDxx types
0.5
1
1.2
V/µs
0.25
0.5
0.6
V/µs
inductive ring-off
CTRL_SET[3] = 0 OR VKELVIN-GND > 2.5 V
(high region); FET Crss = 210 pF
[1]
CTRL_SET[3] = 1 AND VKELVIN-GND < 2.5 V
(low region); FET Crss = 210 pF
type 50WDFY
other 50WDxx types
falling slew rate
SRf
CTRL_SET[3] = 0 OR VKELVIN-GND > 2.5 V
(high region); FET Crss = 210 pF
[1]
CTRL_SET[3] = 1 AND VKELVIN-GND < 2.5 V
(low region); FET Crss = 210 pF
Ro(GATE-KELVIN) output resistance between
pin GATE and pin KELVIN
IG(sc)
short-circuit gate current
Standby mode; pin EN = LOW
[2]
70
130
230
Ω
gate hold-off
[2]
70
130
230
Ω
loss of ground; pin GND = VBAT
30
80
200
kΩ
channel on; short-circuit to ground
-
-
2.5
mA
[1]
If fixed gate slew rate option is set, then rising and falling slew rates are constant irrespective of VKELVIN-GND. For accurate measurement
of slew rates, VBAT supply must remain constant during test.
[2]
Specification includes pin KELVIN series resistance.
Table 34. Protection circuits characteristics
VBAT = VCC(MOD) = 13 V; typical values are given at Tamb = 25 °C; limit values are given at Tcase = −40 °C to +125 °C; unless
otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
236
248
260
µA
trip level setting = 00b
2.235
2.305
2.355
V
trip level setting = 01b
2.178
2.248
2.298
V
trip level setting = 10b
2.088
2.158
2.208
V
trip level setting = 11b
1.933
2.003
2.053
V
Overtemperature protection
IF
forward current
RIREFTEMP = 24.9 kΩ
Vtrip(otp)
over-temperature
protection trip voltage
RIREFTEMP = 24.9 kΩ
[1]
BUK3F00-50WDXX_4
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 04 — 4 September 2008
40 of 52
BUK3F00-50WDxx
NXP Semiconductors
Controller for TrenchPLUS FETs
Table 34. Protection circuits characteristics …continued
VBAT = VCC(MOD) = 13 V; typical values are given at Tamb = 25 °C; limit values are given at Tcase = −40 °C to +125 °C; unless
otherwise specified.
Symbol
Parameter
Vhys(trip)otp
Conditions
Min
Typ
Max
Unit
over-temperature
protection trip hysteresis
voltage
40
50
60
mV
tfltr(trip)
trip filter time
26
-
57
µs
Vth(det)oc(TSD)
temperature sensor
diode open-circuit
detection threshold
voltage
Tamb = −40 °C
2.5
-
3.9
V
Tamb = +125 °C
2.4
-
3.8
V
Overcurrent protection[2]
Vth(on)(bat-KEL)
on-state threshold
voltage between battery
and pin KELVIN
HIGH-to-LOW
[3]
1.65
1.95
2.25
V
1.50
1.80
2.10
V
-
150
-
mV
−7.5
+3
+15
%
trip ratio ≥ 5
−10
+5
+20
%
trip ratio ≤ 4
−7.5
+7.5
+22.5
%
−10
+5
+20
%
LOW-to-HIGH
Vhys(on)(bat-KEL) on-state hysteresis
voltage from battery to
pin KELVIN
∆Itrip/Itrip
relative trip current
variation
OCH; RIREFCURR = 24.9 kΩ
[3][4]
type 50WDFY; TONOCH;
Vsense = 3.5 V;
RIREFCURR = 24.9 kΩ;
high-side switch in turn-on
state
[4][5]
other 50WDxx types;
TONOCH; Vsense = 2.5 V;
RIREFCURR = 24.9 kΩ;
high-side switch in turn-on
state
[6]
[4][5]
[6]
trip ratio ≥ 5
trip ratio ≤ 4
∆tblank/tblank
relative blanking time
variation
Vth(sense)low
low sense threshold
voltage
−7.5
+7.5
+22.5
%
0
-
28
%
1
1.25
1.5
V
open-circuit detected
-
-
0.5 / 255 ×
Imeas(ADC)(fs)
µA
open-circuit not detected
4.5 / 255 ×
Imeas(ADC)(fs)
-
-
µA
[7]
HIGH-to-LOW; TONOCH
operation
Open-circuit detection
Idet(oc)on
on-state open-circuit
detection current
DIG_OLTH[3:0] = 3;
RIREFCURR = 24.9 kΩ;
all ranges
BUK3F00-50WDXX_4
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 04 — 4 September 2008
41 of 52
BUK3F00-50WDxx
NXP Semiconductors
Controller for TrenchPLUS FETs
Table 34. Protection circuits characteristics …continued
VBAT = VCC(MOD) = 13 V; typical values are given at Tamb = 25 °C; limit values are given at Tcase = −40 °C to +125 °C; unless
otherwise specified.
Symbol
Parameter
Conditions
Idet(oc)off
off-state open-circuit
detection current
VKELVIN = 2.5 V
Vdet(oc)off
Min
Typ
Max
Unit
type 50WDFE
40
-
100
µA
other 50WDxx types
55
-
115
µA
2.4
2.6
2.8
V
off-state open-circuit
detection voltage
[1]
Nominal trip voltages quoted for each level. Refer to data sheet for TrenchPLUS FET devices for equivalent temperature measurement.
[2]
If measured without a FET, then connect a suitable resistor between pins VBAT and SENSE to ensure stability.
[3]
Accuracy ensured when VBAT and VCC(MOD) > 9 V.
[4]
Nominal Itrip = n × Imeas(ADC)(fs), where n is the OCH and TONOCH trip level ratio for the product type; see NXIFSC_CHn in Table 19.
[5]
Until the channel is fully turned on, when voltage from battery to pin KELVIN < Vth(on)(bat-KEL).
[6]
VSENSE = 3.5 V for type 50WDFY, VSENSE = 2.5 V for other 50WDxx types.
[7]
Relative blanking time variation does not include clock frequency variation.
17. Application information
17.1 ElectroMagnetic Compatibility guidelines
In some applications, problems associated with electromagnetic interference can occur,
such as false overcurrent tripping, false overtemperature tripping or unexpected turn-on of
individual channels. Vulnerable points can be where currents are induced from wiring
harness connectors positioned close to sensitive control tracks (such as control lines or
FET gate, sense and kelvin lines). Good PCB and circuit design, following RF design
principles, can ensure such problems are avoided. The following guidelines are provided
to achieve this.
17.1.1 Ground layers
In multilayer PCB design, keep sensitive analog signals on the top PCB layer with a
second ground layer acting as a shield. There should be no slits or breaks in this ground
layer.
17.1.2 Circuit loops and tracks
Keep the area of circuit loops small and the length of sensitive tracks short with
components positioned as closely as possible. This particularly applies to FET gate,
sense and kelvin lines.
17.1.3 Connector decoupling
Decoupling capacitors should be fitted directly on, or as close as possible to, connectors,
preventing currents being induced on FET or control tracks.
17.1.4 Module supply decoupling
This supply can be decoupled for EMC with a small ferrite bead.
Circuit analysis should include assessment of possible paths for EMC-induced currents
from different wiring harnesses connected to the PCB.
BUK3F00-50WDXX_4
Product data sheet
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BUK3F00-50WDxx
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17.2 ADC accuracy
The ADC accuracy can be calculated at different measurement points using the graphs
Figure 10 and Figure 11 or associated equation. The effect of additional errors in the
reference current resistor can be estimated as a proportion of the resistor value.
001aag055
25
absolute
bit error
20
y = 10.4x2 + 7.9x + 2
15
10
5
0
0
20
40
60
80
100
ADC measurement (% full scale)
RIREFCURR = 24.9 kΩ.
Fig 10. Maximum ADC bit errors (type 50WDFE)
001aaf455
20
absolute
bit error
16
y = 5.5x2 + 9.7x + 2
12
8
4
0
0
20
40
60
80
100
ADC measurement (% full scale)
RIREFCURR = 24.9 kΩ.
Fig 11. Maximum ADC bit errors (other 50WDxx types)
BUK3F00-50WDXX_4
Product data sheet
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Controller for TrenchPLUS FETs
17.3 Additional metal mask options
Additional metal mask options can be provided with different default settings. Table 35 can
be used to submit these requirements for assessment.
Table 35.
Registers for mask options
Register Name
Description
02h
IN02_MAP
direct input pins IN0 and IN2 mapping
03h
IN13_MAP
direct input pins IN1 and IN3 mapping
04h
INP_MAP
PWM input pin INP mapping
05h
ANDOR_MAP
direct input pin AND/OR operation
07h
SEL_CURR_TRIP_CHAN
select current tripping channel
08h
CHAN_OT_FAULT_CLR
channel set overtemperature fault clear
0Ch
CHAN_WD_MAP
select channel watchdog behavior
0Dh
WD_TO
watchdog time-out period setting
0Eh
CTRL_SET
controller settings
0Fh
INT_PWM_FREQ
internal PWM frequency setting
10h
PWM_DC_CH0
internal PWM duty cycle setting for channel 0
11h
PWM_DC_CH1
internal PWM duty cycle setting for channel 1
12h
PWM_DC_CH2
internal PWM duty cycle setting for channel 2
13h
PWM_DC_CH3
internal PWM duty cycle setting for channel 3
14h
PWM_DC_CH4
internal PWM duty cycle setting for channel 4
15h
PWM_DC_CH5
internal PWM duty cycle setting for channel 5
16h
PWM_DC_CH6
internal PWM duty cycle setting for channel 6
17h
PWM_DC_CH7
internal PWM duty cycle setting for channel 7
18h
OT_TRIPLEV_CH30
overtemperature trip level channels 3 to 0
19h
OT_TRIPLEV_CH74
overtemperature trip level channels 7 to 4
1Ah
IFSC_CH30
full-scale reference current channels 3 to 0
1Bh
IFSC_CH74
full-scale reference current channels 7 to 4
24h
IRQ_MAP
interrupt request mapping
25h
CURR_TRIP_BLANKTIME
current trip blanking time
-
DIG_OLTH
open-circuit threshold level
-
DIG_FET
channel tripping behavior and filter times
-
CHAN_ALLOW_RETRY
channel allow trip and retry after OCH or TONOCH faults
-
RETRY_SETTINGS
trip retry delay and number of retries
-
WRITE_PROTECT
write protect (registers WD_TO and CHAN_WD_MAP)
-
WDPN_LOW_TIME
watchdog time-out LOW time pulse (pin WDTON)
-
VSBATLOW_DEB_EN
debounce on VBAT LOW signal
-
NXIFSC_CH0
channel 0 ratio OCH and TONOCH trip level to Imeas(ADC)(fs)
-
NXIFSC_CH1
channel 1 ratio OCH and TONOCH trip level to Imeas(ADC)(fs)
-
NXIFSC_CH2
channel 2 ratio OCH and TONOCH trip level to Imeas(ADC)(fs)
-
NXIFSC_CH3
channel 3 ratio OCH and TONOCH trip level to Imeas(ADC)(fs)
-
NXIFSC_CH4
channel 4 ratio OCH and TONOCH trip level to Imeas(ADC)(fs)
-
NXIFSC_CH5
channel 5 ratio OCH and TONOCH trip level to Imeas(ADC)(fs)
BUK3F00-50WDXX_4
Product data sheet
Setting required
© NXP B.V. 2008. All rights reserved.
Rev. 04 — 4 September 2008
44 of 52
BUK3F00-50WDxx
NXP Semiconductors
Controller for TrenchPLUS FETs
Table 35.
Registers for mask options …continued
Register Name
Description
-
NXIFSC_CH6
channel 6 ratio OCH and TONOCH trip level to Imeas(ADC)(fs)
-
NXIFSC_CH7
channel 7 ratio OCH and TONOCH trip level to Imeas(ADC)(fs)
-
HL_CH0
channel 0 FET configuration (high or low side)
-
HL_CH1
channel 1 FET configuration (high or low side)
-
HL_CH2
channel 2 FET configuration (high or low side)
-
HL_CH3
channel 3 FET configuration (high or low side)
-
HL_CH4
channel 4 FET configuration (high or low side)
-
HL_CH5
channel 5 FET configuration (high or low side)
-
HL_CH6
channel 6 FET configuration (high or low side)
-
HL_CH7
channel 7 FET configuration (high or low side)
-
FIXED_GATE_SLEW_RATE rising and falling slew rate to have fixed or variable values
during gate turn-on
BUK3F00-50WDXX_4
Product data sheet
Setting required
only high side
available
© NXP B.V. 2008. All rights reserved.
Rev. 04 — 4 September 2008
45 of 52
BUK3F00-50WDxx
NXP Semiconductors
Controller for TrenchPLUS FETs
18. Package outline
QFP64: plastic quad flat package; 64 leads (lead length 1.6 mm); body 14 x 14 x 2.7 mm
SOT393-1
c
y
X
A
48
33
49
32
ZE
e
E HE
A
A2
(A 3)
A1
θ
wM
pin 1 index
Lp
bp
L
17
64
detail X
16
1
w M
bp
e
v M A
ZD
D
B
HD
v M B
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
mm
3
0.25
0.10
2.75
2.55
0.25
0.45
0.30
0.23
0.13
14.1
13.9
14.1
13.9
0.8
HD
HE
17.45 17.45
16.95 16.95
L
Lp
v
w
y
1.6
1.03
0.73
0.16
0.16
0.1
Z D (1) Z E (1)
1.2
0.8
1.2
0.8
θ
o
7
o
0
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT393-1
134E07
MS-022
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
00-01-19
03-02-20
Fig 12. Package outline SOT393-1 (QFP64)
BUK3F00-50WDXX_4
Product data sheet
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NXP Semiconductors
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19. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
19.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
19.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
•
•
•
•
•
•
Board specifications, including the board finish, solder masks and vias
Package footprints, including solder thieves and orientation
The moisture sensitivity level of the packages
Package placement
Inspection and repair
Lead-free soldering versus SnPb soldering
19.3 Wave soldering
Key characteristics in wave soldering are:
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
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Product data sheet
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Rev. 04 — 4 September 2008
47 of 52
BUK3F00-50WDxx
NXP Semiconductors
Controller for TrenchPLUS FETs
19.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 13) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 36 and 37
Table 36.
SnPb eutectic process (from J-STD-020C)
Package thickness (mm)
Package reflow temperature (°C)
Volume (mm3)
< 350
≥ 350
< 2.5
235
220
≥ 2.5
220
220
Table 37.
Lead-free process (from J-STD-020C)
Package thickness (mm)
Package reflow temperature (°C)
Volume (mm3)
< 350
350 to 2000
> 2000
< 1.6
260
260
260
1.6 to 2.5
260
250
245
> 2.5
250
245
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 13.
BUK3F00-50WDXX_4
Product data sheet
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Rev. 04 — 4 September 2008
48 of 52
BUK3F00-50WDxx
NXP Semiconductors
Controller for TrenchPLUS FETs
maximum peak temperature
= MSL limit, damage level
temperature
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 13. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
20. Abbreviations
Table 38.
Abbreviations
Acronym
Description
ADC
Analog-to-Digital Converter
ASIC
Application-Specific Integrated Circuit
CDM
Charge Device Model
EMC
ElectroMagnetic Compatibility
ESD
ElectroStatic Discharge
FET
Field Effect Transistor
HBM
Human Body Model
LSB
Least Significant Bit
MOSFET
Metal Oxide Semiconductor Field Effect Transistor
MSB
Most Significant Bit
PCB
Printed-Circuit Board
PWM
Pulse-Width Modulation
RF
Radio Frequency
SPI
Serial Peripheral Interface
BUK3F00-50WDXX_4
Product data sheet
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Rev. 04 — 4 September 2008
49 of 52
BUK3F00-50WDxx
NXP Semiconductors
Controller for TrenchPLUS FETs
21. Revision history
Table 39.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
BUK3F00-50WDXX_4
20080904
Product data sheet
-
BUK3F00-50WDXX_3
Modifications:
•
•
•
•
•
•
Table 5: cross-references linking register numbers to descriptive sections added.
Table 15: bit 3 description changed. Table note added.
Table 33: rising slew rate: separate values for BUK3F00-50WDFY added.
Table 33: falling slew rate: separate values for BUK3F00-50WDFY added.
Table 33: output resistance between in GATE and pin KELVIN maximum value changed.
Table 34: over-temperature protection trip voltage values changed.
BUK3F00-50WDXX_3
20080617
Product data sheet
-
BUK3F00-50WDXX_2
BUK3F00-50WDXX_2
20080121
Product data sheet
-
BUK3F00-50WDXX_1
BUK3F00-50WDXX_1
20071128
Product data sheet
-
-
BUK3F00-50WDXX_4
Product data sheet
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22. Legal information
22.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
22.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
22.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
22.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
23. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
BUK3F00-50WDXX_4
Product data sheet
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Rev. 04 — 4 September 2008
51 of 52
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Controller for TrenchPLUS FETs
24. Contents
1
2
3
4
5
6
6.1
7
8
8.1
8.2
9
9.1
9.1.1
9.1.2
9.1.3
9.1.4
9.1.5
9.1.6
9.2
9.2.1
9.2.2
9.3
9.3.1
9.3.2
9.3.3
9.3.4
9.3.5
9.4
9.4.1
9.4.2
9.4.3
9.4.4
9.5
9.5.1
9.5.2
9.5.3
9.5.4
9.5.5
9.5.6
9.5.7
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Quick reference data . . . . . . . . . . . . . . . . . . . . . 2
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pinning information . . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
Functional description . . . . . . . . . . . . . . . . . . . 7
Power and reference supplies. . . . . . . . . . . . . . 7
Battery supply: pins VBAT and GND . . . . . . . . . 7
Module supply: pins VCC(MOD) and GND. . . . . . 8
External logic supply: pins VCC(LOG)EXT
and GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Analog measurement supply: pins VCC(MEASC)
and GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Digital supply: pins VCC(DIGC) and GND(DIGC). 8
Reference supplies: pins IREFCURR and
IREFTEMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Charge pump supply: pins VBAT(CP) and
GND(CP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Charge pump boost mode . . . . . . . . . . . . . . . . 9
Control logic . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Digital control . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Serial Peripheral Interface (SPI) . . . . . . . . . . . 13
SPI watchdog . . . . . . . . . . . . . . . . . . . . . . . . . 15
Pulse-Width Modulation (PWM) . . . . . . . . . . . 16
Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Current measurement. . . . . . . . . . . . . . . . . . . 17
Current measurement circuits. . . . . . . . . . . . . 17
Analog current measurement output . . . . . . . 18
Digital current measurement output . . . . . . . . 18
Low battery supply voltage conditions . . . . . . 18
TrenchPLUS FET interface . . . . . . . . . . . . . . . 19
Overtemperature protection . . . . . . . . . . . . . . 19
Overcurrent protection . . . . . . . . . . . . . . . . . . 20
Gate inductive ring-off clamp . . . . . . . . . . . . . 21
Loss-of-ground protection. . . . . . . . . . . . . . . . 22
Controller settings. . . . . . . . . . . . . . . . . . . . . . 22
Open-circuit detection. . . . . . . . . . . . . . . . . . . 22
Channel selection . . . . . . . . . . . . . . . . . . . . . . 23
9.5.8
9.5.9
9.5.10
9.5.11
9.5.12
10
11
11.1
11.2
12
13
14
15
16
17
17.1
17.1.1
17.1.2
17.1.3
17.1.4
17.2
17.3
18
19
19.1
19.2
19.3
19.4
20
21
22
22.1
22.2
22.3
22.4
23
24
Mapping channels for direct channel control and
PWM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
FET channel on/off control . . . . . . . . . . . . . . . 24
Power dissipation . . . . . . . . . . . . . . . . . . . . . . 24
Trip and retry . . . . . . . . . . . . . . . . . . . . . . . . . 25
Trip-latch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Fixed functional settings . . . . . . . . . . . . . . . . 26
Diagnostic functions . . . . . . . . . . . . . . . . . . . . 28
Reset for interrupt and SPI watchdog . . . . . . 28
Diagnostic data . . . . . . . . . . . . . . . . . . . . . . . 28
Application design-in information . . . . . . . . . 31
Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 33
Recommended operating conditions . . . . . . 34
Thermal characteristics . . . . . . . . . . . . . . . . . 35
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 36
Application information . . . . . . . . . . . . . . . . . 42
ElectroMagnetic Compatibility guidelines. . . . 42
Ground layers. . . . . . . . . . . . . . . . . . . . . . . . . 42
Circuit loops and tracks . . . . . . . . . . . . . . . . . 42
Connector decoupling . . . . . . . . . . . . . . . . . . 42
Module supply decoupling . . . . . . . . . . . . . . . 42
ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . 43
Additional metal mask options . . . . . . . . . . . . 44
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 46
Soldering of SMD packages . . . . . . . . . . . . . . 47
Introduction to soldering. . . . . . . . . . . . . . . . . 47
Wave and reflow soldering . . . . . . . . . . . . . . . 47
Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 47
Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . 48
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 49
Revision history . . . . . . . . . . . . . . . . . . . . . . . 50
Legal information . . . . . . . . . . . . . . . . . . . . . . 51
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 51
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Contact information . . . . . . . . . . . . . . . . . . . . 51
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2008.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 4 September 2008
Document identifier: BUK3F00-50WDXX_4