10BIT 500KSPS / 8BIT 650KSPS ADC BW1227L FEATURES GENERAL DESCRIPTION The BW1227L is a CMOS 8bit/10bit changeable A/D converter which combines an 8-channel analog input MUX, auto offset calibration comparator, high resolution R-string DAC, clock generator, 8bit/10bit changeable successive approximation register (SAR), output register, and AISC which controls analog input selection. BW1227L provides a hardwired MODE8 pin and software-selection power-down mode. At the MODE8 state is "low", the device operates as 10bit ADC, and if "high", operates as 8bit. The device operates with a single +3.3V supply and A/D conversion rate is 500KSPS at 10bit and 650KSPS at 8bit, external clock XP1 is 25MHz. The operating temperature range is 0~70 °C for commercial spec. Even if The BW1227L is fabricated with 48TSSOP package but the USER can select a fit package using the CORE. - - Resolution : 10 bit Differential Linearity Error : ±1.0 LSB Integral Linearity Error : ±2.0 LSB Maximum Conversion Rate : 500KSPS(10bit) 650KSPS(8bit) Low Power Consumption : at operating, 3.3mW(typ) : at standby, 330nW(typ) Power Supply Voltage : 3.3V single(typ) Guaranteed Monotonicity No Missing Code Latched Tri-state Output Operation Temperature Range : 0 ~70 °C FUNCTIONAL BLOCK DIAGRAM VSSA VDDA REFN REFP DAOUT VDDD VSSD VBBA DAC + MODE8 SAR COP ADEN - FLAG 10 XP1 10 CKGEN OUTREG ADO[9:0] STBY DGET AIN AMUX 3 AISC 8 3 AIN[7:0] ASEL[2:0] Ver 1.5 (Apr. 2002) No responsibility is assumed by SEC for its use nor for any infringements of patents or other rights of third parties that may result from its use. The content of this data sheet is subject to change without any notice. SEC ASIC ANALOG BW1227L 10BIT 500KSPS/8BIT 650KSPS mode-changable ADC CORE PIN DESCRIPTION I/O TYPE ABBR. NAME I/O TYPE I/O PAD REFP AI pia_bb Internal Reference Top Bias. 3.3V REFN AI pia_bb Internal Reference Bottom Bias. 0V VDDA AP vdda Analog Power(3.3V) VSSA AG vssa Analog Ground AIN[7:0] AI piar50_bb MODE8 DI picc_bb 10bit/8bit Mode Change Enable Pin XP1 DI picc_bb Main Clock(external) STBY DI picc_bb System Power Down(Active High) ADEN DI picc_bb A/D Conversion Enable ADO[9:0] DO pot2_bb Digital Outputs DGET DI picc_bb DOUTs Read Enable ASEL[2:0] DB poa_bb AIN Selection Pins, Bidirectional. FLAG DO pot2_bb Test pin for checking the ADC state VBBA DG/AG vbba Sub Bias VSSD DG vssd Digital Ground VDDD DP vddd Digital Power PIN DESCRIPTION AI : Analog Input DI : Digital Input AO : Analog Output DO : Digital Output AP : Analog Power AG : Analog Ground DP : Digital Power DG : Digital Ground VSSD VBB ⋅ AB : Analog Bidirection ⋅ DB : Digital Bidirection VDDD REFP REFN VSSA 8 VDDA Analog Inputs. Input Span : REFP ~ REFN CORE CONFIGURATION AIN[7:0] ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ bw1227l 10 ADO[9:0] SEC ASIC 2/13 FLAG ASEL[2:0] DGET ADEN STBY XP1 MODE8 3 MIXED BW1227L 10BIT 500KSPS/8BIT 650KSPS mode-changable ADC ABSOLUTE MAXIMUM RATINGS Characteristic Symbol Value Unit Supply Voltage VDD 4.5 V Analog Input Voltage AIN VSS to VDD V Digital Input Voltage DIN VSS to VDD V VOH, VOL VSS to VDD V REFP / REFN VSS to VDD V Digital Output Voltage Reference Voltage Storage Temperature Range Tstg -45 to 150 °C Operating Temperature Range Topr 0 to 70 °C NOTES 1. ABSOLUTE MAXIMUM RATING specifies the values beyond which the device may be damaged permanently. Exposure to ABSOLUTE MAXIMUM RATING conditions for extended periods may affect reliability. Each condition value is applied with the other values kept within the following operating conditions and function operation under any of these conditions is not implied. 2. All voltages are measured with respect to VSS unless otherwise specified. 3. 100pF capacitor is discharged through a 1.5kΩ resistor (Human body model) RECOMMENDED OPERATING CONDITIONS Symbol Min Typ Max Unit Supply Voltage VDDA,VDDD 3.3-5% 3.3 3.3+5% V Supply Voltage Difference VDDA-VDDD -0.1 0.0 0.1 V REFP REFN - VDDA 0 - V Analog Input Voltage AIN REFN - REFP V Clock High Time Clock Low Time Tpwh Tpwl - 19 19 - ns VIL VIH 0 0.9*VDDD - 0.1*VDDD VDDD V Topr 0 - 70 °C Characteristics Reference Input Voltage Digital Input 'L' Voltage Digital Input 'H' Voltage Operating Temperature NOTES 1. It is strongly recommended that all the supply pins (VDDA, VDDD) be powered from the same source to avoid power latch-up. SEC ASIC 3/13 MIXED BW1227L 10BIT 500KSPS/8BIT 650KSPS mode-changable ADC DC ELECTRICAL CHARACTERISTICS (10bit) Characteristics Symbol Min Typ Max Unit - - 10 - Bits Differential Linearity Error DLE - ±0.5 ±1.0 LSB Integral Linearity Error ILE - ±1.0 ±2.0 LSB Offset Voltage Error(top) EOT - ±2.0 ±4.0 LSB EOT=REFP-AIN(1023,1024) Offset Voltage Error(bottom) EOB - ±2.0 ±4.0 LSB EOB=AIN(0,1)-REFN - - - ±1/4 LSB 8-channel Resolution Conditions MODE8='0' XP1 : 25MHz Channel to Channel Mismatch NOTES 1. Converter Specifications (unless otherwise specified) VDDA=3.3V VDDD=3.3V VSSA=GND VSSD=GND VBB=GND REFP=3.3V REFN=0.0V Ta=25 °C 2. TBD : To Be Determined AC ELECTRICAL CHARACTERISTICS (10bit) Symbol Min Typ Max Unit Clock High Time Tpwh - 19 - ns Clock Low Time Tpwl - 19 - ns Conversion Rate fAD - 500 550 KSPS Conversion Time tAD 1.8 2 - us Characteristics Conditions XP1 : 25MHz Is - 1 1.5 mA Is=I(VDDA)+I(VDDD)+ I(REFP) Power Load Cap:10uF//0.1uF Output load cap.=1pF Isd - 0.1 0.5 uA at Power Down. Pd - 3.3 5.4 mW during A/D operation Pdd - 0.33 1.8 uW at Power Down. tD - 20 25 ns Output load cap.=1pF Dynamic Supply Current Power Dissipation Digital Output Data Delay SEC ASIC 4/13 MIXED BW1227L 10BIT 500KSPS/8BIT 650KSPS mode-changable ADC DC ELECTRICAL CHARACTERISTICS (8bit) Characteristics Symbol Min Typ Max Unit - - 8 - Bits Differential Linearity Error DLE - ±0.5 ±1.0 LSB Integral Linearity Error ILE - ±0.5 ±1.0 LSB Offset Voltage Error(top) EOT - ±0.5 ±1.0 LSB EOT=REFP-AIN(254,255) Offset Voltage Error(bottom) EOB - ±0.5 ±1.0 LSB EOB=AIN(0,1)-REFN - - - ±1/4 LSB 8-channel Resolution Conditions MODE8='1' XP1 : 25MHz Channel to Channel Mismatch NOTES 1. Converter Specifications (unless otherwise specified) VDDA=3.3V VDDD=3.3V VSSA=GND VSSD=GND VBB=GND REFP=3.3V REFN=0.0V Ta=25 °C 2. TBD : To Be Determined AC ELECTRICAL CHARACTERISTICS (8bit) Symbol Min Typ Max Unit Clock High Time Tpwh - 19 - ns Clock Low Time Tpwl - 19 - ns Conversion Rate fAD - 650 675 KSPS Conversion Time tAD 1.482 1.5 - us Characteristics Conditions XP1 : 25MHz Is - 1 1.5 mA Is=I(VDDA)+I(VDDD)+ I(REFP) Power Load Cap:10uF//0.1uF Output load cap.=1pF Isd - 0.1 0.5 uA at Power Down. Pd - 3.3 5.4 mW during A/D operation Pdd - 0.33 1.8 uW at Power Down. tD - 20 25 ns Output load cap.=1pF Dynamic Supply Current Power Dissipation Digital Output Data Delay SEC ASIC 5/13 MIXED BW1227L 10BIT 500KSPS/8BIT 650KSPS mode-changable ADC TIMING DIAGRAM(the case of 10bit) fig1. XP1 minimum 1-XP1 time STBY MODE8 ADEN ASEL[2:0] AIN[7:0] selected 1-channel FLAG DGET ADO[9:0] fig2. XP1 STBY MODE8 ADEN ASEL[2:0] input mode AIN[7:0] FLAG A/D conversion finished minimum 4-XP1 time DGET ADO[9:0] A/D conversion data out. fig3. at STANDBY XP1 STBY MODE8 ADEN ASEL[2:0] AIN[7:0] last AIN channel is maintained FLAG FLAG state goes to '1' DGET ADO[9:0] previous A/D conversion data out. SEC ASIC 6/13 MIXED 10BIT 500KSPS/8BIT 650KSPS mode-changable ADC BW1227L DATA OUTPUT DELAY TIMING Internal DOUTs are latched at OUTREG by EOC(End Of Conversion, internal). Note that before DGET is forced, this latched DOUTs(ADO[9:0]) don't go out. XP1 EOC FLAG ADO[9:0] tD FUNCTIONAL DESCRIPTION 1. XP1 The XP1 is the system main clock. If 25MHz clock is applied, 10bit 500KSPS or 8bit 650KSPS outputs are produced. In case of 10MHz clock, 10bit 200KSPS or 8bit 250KSPS outputs are made. 2. STBY This pin is used for keeping standby without A/D conversion operation. For A/D operation, its state must be changed from '1' to '0' after at least one XP1 period. In the timing chart, 3.5-XP1 period is drawn and this state transition can occur even at rising or falling edges. If not needed, it can be tied to GND. 3. ADEN This is a A/D conversion enable signal. It is for one XP1 period at falling edge. In a 10bit, at least 45-XP1 periods are required until the next ADEN, and 37-XP1 periods are delayed until the next ADEN for an 8bit. 4. ADO[9:0] Digital output pins. 5. DGET Data read signal. If DGET is applied during A/D conversion, selected AIN pin information is produced(refer to TIMING CHART). It is to check if the right analog input is selected. After A/D operation, the state of the test pin, FLAG, changes to '1', and A/D converted data are produced by applying DGET signal. 6. ASEL[2:0] These bidirectional pins are analog input selection pins. ASEL[2:0] are applied at XP1 rising edge after ADEN is applied, and one of eight analog input channels is selected. 7. AIN[7:0] 8 analog input channels are produced. The channel numbers are programmable. 8. FLAG Test pin. Its state goes LOW during A/D conversion, and goes HIGH after the A/D conversion. If STBY signal is applied even at A/D conversion mode, its state goes HIGH immediately. 9. MODE8 It switches the ADC function between 8bit and 10bit. The LOW state is maintained in 10bit operation, and HIGH state in 8bit operation. The 8bit resolution is kept the same as 10bit. If your application is fixed as 8bit or 10bit, it can be tied to GND at 10bit or VDD at 8bit. SEC ASIC 7/13 MIXED BW1227L 10BIT 500KSPS/8BIT 650KSPS mode-changable ADC CORE EVALUATION GUIDE 1. You can test ADC function by the DGET. If you don't use the DGET pin, this ADC function is evaluated by external check on the bi-directional pads connected to input nodes of HOST DSP back-end circuit. 2. The reference voltages may be biased externally through REFP and REFN pins AIN[7:0] 8 STBY DGET 3 ASEL[2:0] FLAG REFN REFP VDDD VSSD VBB VBBA 10 ADO[9:0] 10 HOST DSP CORE 8/13 NOTES : 10uF ELECTROLYTIC CAPACITOR UNLESS OTHERWISE SPECIFIED : 0.1uF CERAMIC CAPACITOR UNLESS OTHERWISE SPECIFIED ANALOG MUX 10 BIDIRECTIONAL PAD ADC Function Measuring & Digital Input Forcing SEC ASIC VDDA ref. TOP ADEN VSSA ref. BOTTOM XP1 bw1227l MODE8 MIXED BW1227L 10BIT 500KSPS/8BIT 650KSPS mode-changable ADC PACKAGE CONFIGURATION Digital Power 48 VDDD NC 1 Ref. Top 10u Ref. Bottom 0.1u 10u 0.1u 0.1u VBBA 44 VBB NC 5 43 NC VSSA 8 41 ASEL[2] NC 9 40 ASEL[1] AIN[2] 12 10u AIN[3] 13 8 AIN[4] 14 bw1227l AIN[1] 11 Analog Inputs 42 FLAG NC 7 AIN[0] 10 0.1u 45 NC VDDA 6 10u 10u 46 VSSD NC 3 REFN 4 Analog Power Pad Cell Power 47 NC REFP 2 3 39 ASEL[0] 38 DGET 37 NC 36 ADO[9] 35 ADO[8] AIN[5] 15 34 ADO[7] AIN[6] 16 33 ADO[6] AIN[7] 17 32 ADO[5] VDD_IO 18 31 ADO[4] VSS_IO 19 30 ADO[3] MODE8 20 29 ADO[2] XP1 21 28 ADO[1] STBY 22 27 ADO[0] ADEN 23 26 NC NC 24 25 NC Digital Outputs 10 0.1u NOTES : 10uF ELECTROLYTIC CAPACITOR UNLESS OTHERWISE SPECIFIED : 0.1uF CERAMIC CAPACITOR UNLESS OTHERWISE SPECIFIED NOTES 1. ESD (Electro Static Discharge) sensitive device. Although the digital control inputs are diode protected, permanent damage may occur on devices subjected to high electrostatic discharges. It is recommended that unused devices be stored in conductive foam or shunts to avoid performance degradation or loss of functionality. The protective foam should be discharged to the destination socket before devices are inserted. 2. NC denotes "No Connection". SEC ASIC 9/13 MIXED 10BIT 500KSPS/8BIT 650KSPS mode-changable ADC BW1227L PACKAGE PIN DESCRIPTION NAME I/O TYPE REFP AI Internal Reference Top Bias. 3.3V REFN AI Internal Reference Bottom Bias. 0V VDDA AP Analog Power(3.3V) VSSA AG Analog Ground AIN[7:0] AI Analog Inputs. Input Span : REFP ~ REFN VDD_IO DP I/O PAD Power(3.3V) VSS_IO DG I/O PAD Ground MODE8 DI 10bit/8bit Mode Change Enable Pin XP1 DI Main Clock(external) STBY DI System Power Down(Active High) ADEN DI A/D Conversion Enable ADO[9:0] DO Digital Outputs DGET DI ADO/ASEL Read Enable ASEL[2:0] DB Analog Input Selection Pins, Bidirectional. FLAG DO Test pin. ADC Operation Checking. Digital State FLAG VBBA AG Sub Bias VSSD DG Digital Ground VDDD DP Digital Power NC - No Connection SEC ASIC PIN DESCRIPTION 10/13 MIXED BW1227L 10BIT 500KSPS/8BIT 650KSPS mode-changable ADC USER GUIDE 1. Speed Up -The initial target speed(Conversion Rate) of BW1227L was 10bit 500KSPS and 8bit 650KSPS, but it proved to operate well even at 10bit 600KSPS and 8bit 800KSPS because of a lot of design margin. It would be realized by speed-up of XP1. 2. Input Range Variation. - The analog input of this ADC is single input and the range is from REFN to REFP. This AIN voltage follows reference voltage range fundamentally. Therefore, in order to alter into another input voltage range, change the voltage value of REFP. - You can use the AIN voltage whose minimum range is 2.7V. In this case, the REFP is 2.7V and REFN is 0.0V. If the range is 3.0V, the REFP is 3.0V and REFN is 0.0V. It is an user selection item. In case of maximum voltage range, the REFP is the power level(3.3V) and the REFN is the ground level. 3. You can choose ADC for 8bit mode or 10bit mode by controlling the MODE8 pin. At 8bit mode, the MODE8 state is "high" and at 10bit mode, "low". 4. You can select the analog input numbers from one to eight. The relation of ASEL[2:0] is as follows AIN[7] AIN[6] AIN[5] AIN[4] AIN[3] AIN[2] AIN[1] AIN[0] ASEL[2] 1 1 1 1 0 0 0 0 ASEL[1] 1 1 0 0 1 1 0 0 ASEL[0] 1 0 1 0 1 0 1 0 5. Note that this ADC has not the sample and hold circuit, therefore during the A/D conversion the analog input voltage variation should not deviate more than 1 LSB voltage range. 6. If you want to use this ADC as 2-channel 8bit 650KSPS ADC, the ASEL[2:1] and AIN[7:2] pins should be connected "low", and the MODE8 pin should be connected "high". The 2-input channel selection table is as follows ASEL[0] AIN[1] AIN[0] 1 0 The 8bit digital output pins of ADC are ADO[9:2]. The ADO[1:0] pins which are LSB pins of 10bit mode can be ignored. TYPICAL APPLICATIONS ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ MICOM Battery Charger Game Pack Digital Still Camera Hand Held Computer & Organizer. Other Low power equipments. SEC ASIC 11/13 MIXED BW1227L 10BIT 500KSPS/8BIT 650KSPS mode-changable ADC PHANTOM CELL INFORMATION - Pins of the core can be assigned externally (Package pins) or internally (internal ports) depending on design methods. The term "External" implies that the pins should be assigned externally like power pins. The term "External/internal" implies that the applications of these pins depend on the user. VDDA REFP REFN Pin Name Pin Usage VDDA External VSSA External VBBA External VDDD External VSSD External AIN[7:0] External/Internal Pin Layout Guide - Do not merge the analog powers with another power from other blocks. - Use good power and ground source on board. - Do not overlap with digital lines. - Maintain the shortest path to pads. REFP External REFN External ADEL[2:0] External/Internal XP1 External/Internal - Maintain the larger width and the shorter length as far as the pads. VDDD - Separate from all other digital lines. VSSD VBBA VSSA ADEN BW1227L AIN[0] AIN[1] External/Internal ASEL[2] DGET External/Internal ASEL[1] STBY External/Internal ASEL[0] FLAG External/Internal ADO[9] External/Internal ADO[8] External/Internal ADO[7] External/Internal ADO[6] External/Internal ADO[5] External/Internal - Separated from the analog clean ADO[4] External/Internal ADO[3] External/Internal ADO[2] External/Internal ADO[1] External/Internal ADO[0] External/Internal AIN[4] AIN[5] DGET AIN[6] AIN[7] ADO[9] ADO[8] ADO[7] ADO[6] ADO[5] ADO[4] ADO[3] ADO[2] ADO[1] ADO[0] ADEN XP1 STBY MODE8 SEC ASIC signals MODE8 AIN[2] AIN[3] External/Internal - Separate from all other analog FLAG signals if possible. MIXED BW1227L 10BIT 500KSPS/8BIT 650KSPS mode-changable ADC FEEDBACK REQUEST-1 It should be quite helpful to our ADC core development if you specify your system requirements on ADC in the following characteristic checking table and fill out the additional questions. We appreciate your interest in our products. Thank you very much. Characteristic Min Typ Max Unit Analog Power Supply Voltage V Digital Power Supply Voltage V Bit Resolution Bit Reference Input Voltage V Analog Input Voltage Remarks Vpp Number of Analog Input Channel °C Operating Temperature Integral Non-linearity Error LSB Differential Non-linearity Error LSB Bottom Offset Voltage Error mV Top Offset Voltage Error mV Conversion Rate KSPS Conversion Time(ADEN~ADEN) us Dynamic Supply Current mA Power Dissipation mW Power Dissipation at Power Down uW Digital Output Format (Provide detailed description & timing diagram) SEC ASIC 12/13 MIXED 10BIT 500KSPS/8BIT 650KSPS mode-changable ADC BW1227L FEEDBACK REQUEST-2 1. I want to know the detail of the analog input waveform. Which one is adequate for your analog input waveform among the a, b, and c below. If none of the three is adequate, please describe the analog input waveform to be used. If your analog input signal is sine-wave as c, please let me know what is your analog input signal's frequency and how many number of sampling points are required for 1-period? AIN[n] AIN[0] a. (fixed DC input) n-channel Analog MUX b. (ramp DC input) c. (sine-wave input) 2. Between single input-output and differential input-output configurations, which one is suitable for your system and why? 3. Please comment on the internal/external pin configurations and draw the timing diagram you want our ADC to have, if you have any reason to prefer some type of configuration. 4. Freely list those functions you want to be implemented in our ADC, if you have any. SEC ASIC 13/13 MIXED 10BIT 500KSPS/8BIT 650KSPS mode-changable ADC BW1227L HISTORY CARD Version Modified Items Date ver 1.0 Comments Original version published (preliminary) ver 1.1 ver 1.2 ver 1.3 ver 1.4 1200.03 Release the formal datasheet ver 1.5 02.04.27 Add the pin information to the phantom cell information SEC ASIC MIXED