February 1999 CMOS Single-Chip, Full-Feature PCM CODEC Features Description • Meets or Exceeds All AT&T D3/D4 Specifications and CCITT Recommendations The CD22354A and CD22357A are monolithic silicongate, double-poly CMOS integrated circuits containing the band-limiting filters and the companding A/D and D/A conversion circuits that conform to the AT&T D3/D4 specifications and CCITT recommendations. The CD22354A provides the AT&T µ-law and the CD22357A provides the CCITT A-law companding characteristic. • Complete CODEC and Filtering Systems: No External Components for Sample-and-Hold and Auto-Zero Functions. Receive Output Filter with (SIN X)/X Correction and Additional 8kHz Suppression • Variable Data Clocks - From 64kHz . . . . . . . . . . . . . . . . . . . . . 2.1MHz • Receiver Includes Power-Up Click Filter The primary applications for the CD22354A and CD22357A are in telephone systems. These circuits perform the analog and digital conversions between the subscriber loop and the PCM highway in a digital switching system. The functional block diagram is shown below. • TTL or CMOS-Compatible Logic • ESD Protection on All Inputs and Outputs Applications • PABX With flexible features, including synchronous and asynchronous operations and variable data rates, the CD22354A and CD22357A are ideally suited for PABX, central office switching system, digital telephones as well as other applications that require accurate A/D and D/A conversions and minimal conversion time. • Central Office Switching Systems • Accurate A/D and D/A Conversions • Digital Telephones • Cellular Telephone Switching Systems • Voice Scramblers - Descramblers Ordering Information • T1 Conference Bridges • Voice Storage and Retrieval Systems PART NUMBER • Sound Based Security Systems TEMP. RANGE (oC) PACKAGE PKG. NO. • Computerized Voice Analysis CD22354AE -40 to 80 16 Ld PDIP E16.3 • Mobile Radio Telephone Systems CD22357AE -40 to 80 16 Ld PDIP E16.3 • Microwave Telephone Networks • Fiber-Optic Telephone Networks Functional Block Diagram 16 VFX1+ GND 2 15 VFX1- VFRO 3 14 GSX V+ 4 13 TSX FSR 5 12 FSX DR 6 11 DX BCLKR/ 7 CLKSEL MCLKR/ 8 PDN GSX VFX1VFX1+ 14 15 16 + ANTI-ALLAS FILTER XMIT LOW PASS FILTER XMIT HIGH PASS FILTER TRANSMIT COMPARATOR D/A LADDER SIGN BIT INT. XMIT VREF BAND GAP REFERENCE 10 BCLKX 9 MCLKX XMIT CLOCK CIRCUIT XMIT DIGITAL VFRO 2 RCV VREF 3 SMOOTHING FILTER RECEIVE LOW PASS FILTER 8 5 4-165 SERIAL TO PARALLEL D/A REGISTER 7 6 DX BCLKX FSX TSX MCLKX MCLKR/ PDN FSR BCLKR/ CLKSEL DR RCV DIGITAL RECEIVE D/A LADDER CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. © Harris Corporation 1999 11 10 12 13 9 RCV CLOCK CIRCUIT GND Copyright PARALLEL TO SERIAL S.A.R. DDIGITAL OUT V- 1 FULL-FEATURE PCM CODEC DDIGITAL IN CD22354A, CD22357A (PDIP) TOP VIEW FROM SLIC Pinout TO SLIC [ /Title (CD22 354A, CD223 57A) /Subject (CMO S SingleChip, FullFeature PCM CODE C) / Author () /Keywords (Harris Semiconductor, RSLIC 18, Telecom, SLICs, SLACs , Telephone, Telephony, WLL, Wireless Local Loop, CD22354A, CD22357A T UCT ROD ACEMEN 47 P E 7 T L 7 E P 42 OL RE 00-4 m OBS ENDED 8 1 s.co MM ions ECO pplicat p@harri R O A N ral ntap Cent : ce Call or email Semiconductor +5V -5V 4 1 File Number V+ V- 1682.4 CD22354A, CD22357A Absolute Maximum Ratings Thermal Information DC Supply-Voltage, (V+) . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5 to 7V DC Supply-Voltage, (V-) . . . . . . . . . . . . . . . . . . . . . . . . . . .0.5 to -7V DC Input Diode Current, IIK (VI < V- -0.5V or VI > V+ 0.5V) . . . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK (VI < V- -0.5V or VO > V+ 0.5V). . . . . . . . . . . . . . . . . . . . . . .±20mA DC Drain Current, Per Output IO (V- -0.5V < VO < V+ 0.5V) . . . . . . . . . . . . . . . . . . . . . . . . . . . .±25mA DC Supply/Ground Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±50mA Power Dissipation Per Package (PD): For TA = -40oC to 60oC . . . . . . . . . . . . . . . . . . . . . . . . . . . 500mW For TA = 60oC to 85oC . . . . . . . . . . . . Derate Linearly at 8mW/oC to 300mW Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 175oC Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC Maximum Storage Temperature Range (TSTG) . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC Operating Conditions Operating-Temperature Range (TA) . . . . . . . . . . . . . . -40oC to 80oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Electrical Specifications PARAMETER At TA = 25oC SYMBOL TEST CONDITIONS MIN TYP MAX UNITS STATIC SPECIFICATIONS Positive Power Supply V+ 4.75 5 5.25 V Negative Power Supply V- -4.75 -5 -5.25 V Power Dissipation (Operating) POPR V+ = 5V - 75 90 mW Power Dissipation (Standby) PSTBY V- = -5V - 9 15 mW Electrical Specifications PARAMETER At TA = 0oC to 70oC; V+ = 5V ±5%, V- = -5V ±5% SYMBOL TEST CONDITIONS MIN TYP MAX UNITS 10 - - MΩ - 5 - pF -10 - 10 µA STATIC SPECIFICATIONS Analog Input Resistance RINA Input Capacitance CIN Input Leakage Current, Digital II All Logic and Analog Inputs VI = 0V or V+ Low Level Input Voltage VIL IIL = ±10µA (Max) - - 0.8 V High Level Input Voltage VIH IIH = ±10µA (Max) 2 - - V Low Level Output Voltage VOL IOL = 3.2mA - - 0.4 V High Level Output Voltage VOH IOH = 1.0mA 2.4 - - V Open State Output Current IOZ GND < DX < V+ -10 - 10 µA -2.5V ≤ VFX < 2.5V -200 - 200 nA Input Leakage Current, Analog II 4-166 CD22354A, CD22357A V+ = 5V ±5%, V- = -5V ± 5%, BCLKR = BCLKX = MCLKX = 1.544MHz, VIN = 0dBm0, TA = 0oC to 70oC Electrical Specifications PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS f = 16Hz - - -40 dB f = 50Hz - - -30 dB f = 60Hz - - -26 dB f = 200Hz -1.8 - -0.1 dB f = 300Hz to 3000Hz -0.15 - 0.15 dB f = 3300Hz -0.35 - 0.05 dB f = 3400Hz -0.7 - 0 dB f = 4000Hz - - -14 dB f ≥ 4600Hz, Measure 0 - 4kHz Response - - -32 dB f = 0Hz to 3000Hz -0.15 - 0.15 dB f = 3300Hz -0.35 - 0.05 dB f = 3400Hz -0.9 - 0 dB f = 4000Hz - - -14 dB TRANSMIT AND RECEIVE FILTER TRANSFER CHARACTERISTICS Transmit Gain (Relative to Gain at 1020Hz) Input Amplifier Set to Unity Gain GRX Receive Gain (Relative to Gain at 1020Hz) (Includes (SIN X)/X Compensation) GRR AC Specifications Definition Unless otherwise specified, the following conditions apply: AMPLITUDE RESPONSE Absolute Levels Definition: VREF = -2.5V Nominal 0dBm0 level. . . . . . . . . . . . . . . . . . . . . . 4dBm into 600Ω 1.2276VRMS Maximum Overload Level: Voltage reference (VREF) of -2.5V . . . . . . . . . . . . . . . . 2.5V µ-Law 2.49V A-Law V+ = 5V ±5%, V- = -5V ±5% GNDA, GNDD = 0V, FFX = 1020Hz at 0dBm0 Transmit input amplifier operating in a unity gain configuration Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC Receive output is measured single-ended. All output levels are (SIN X)/X corrected. AC Specifications Encoding Format at DX Output CD22357A A-LAW (INCLUDES EVEN BIT INVERSION) CD22354A µ-LAW VIN (at GSX) = +Full-Scale 1 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 VIN (at GSX) = 0V 1 1 1 1 1 1 1 1 1 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 VIN (at GSX) = -Full-Scale 4-167 CD22354A, CD22357A Electrical Specifications PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Level = +3dBm0 33 - - dBc Level = 0 to -30dBm0 36 - - dBc Level = -40dBm0 30 - - dBc Level = -55dBm0, XMT 14 - - dBc Level = -55dBm0, RCV 15 - - dBc - - -46 dBc AC DISTORTION Signal to Total Distortion Xmit or RCV STDX, STDR Single Frequency Distortion Xmit or RCV SFDX, SFDR Intermodulation (End-to-End Measurement) 2-Tone IMD VFX = -4dBm0 to -21dBm0 f1, f2 from 300 to 3400Hz - - -41 dB Transmit Delay, Absolute tDAX f = 1600Hz - 280 315 µs Transmit Envelope Delay Relative to tDAX tDEX f = 500-600Hz - 170 220 µs f = 600-1000Hz - 70 145 µs f = 1000-2600Hz - 40 75 µs f = 2600-2800Hz - 90 105 µs - 180 200 µs Receive Delay, Absolute tDAR f = 1600Hz Receive Envelope Delay Relative to tDAR tDER f = 500-600Hz -40 -25 - µs f = 600-1000Hz -40 -25 - µs f = 1000-2600Hz - 60 90 µs f = 2600-2800Hz - 110 125 µs MIN TYP MAX UNITS +3 to -40dBm0 - - ±0.2 dB -40 to -50dBm0 - - ±0.4 dB -50 to -55dBm0 - - ±1.2 dB +3 to -40dBm0 - - ±0.2 dB -40 to -50dBm0 - - ±0.4 dB -50 to -55dBm0 - - ±1.2 dB 68 - - dB Electrical Specifications PARAMETER SYMBOL TEST CONDITIONS AC GAIN TRACKING Transmit Gain Tracking Error Receive Gain Tracking Error Transmit Input Amplifier Gain, Open Loop GTX GTR AOL RL ≥ 1MΩ at GSX 4-168 CD22354A, CD22357A Electrical Specifications PARAMETER (Continued) SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Transmit Input Amplifier Gain, Unity ACL Unity Gain Configuration Inverting or Non-Inverting RL ≥ 10K, CL ≤ 50pF -0.01 - 0.01 dB Transmit Gain, Absolute GXA RL ≥ 10K, CL ≤ 50pF -0.15 - 0.15 dB Receive Gain, Absolute GRA RL ≥ 600Ω, CL ≤ 500pF -0.15 - 0.15 dB MIN TYP MAX UNITS VFXI- = GND - 12 15 dBrnc0 VFXI+ = GND - -74 -67 dBrn0p PCM Code Equivalent to 0V - 7 11 dBrnc0 - -83 -79 dBrn0p Electrical Specifications PARAMETER SYMBOL TEST CONDITIONS AC NOISE Transmit Noise Receive Noise NX NR V+ Power Supply Rejection Transmit PSRR VFXI+ = 0V V+ = 5V + (100mVRMS) f = 0kHz to 50kHz 40 - - dBc V- Power Supply Rejection Transmit PSRR VFXI- = 0V V- = -5V + (100mVRMS) f = 0kHz to 50kHz 40 - - dBc V+ Power Supply Rejection Receive PSRR PCM Code = All 1 Code V+ = 5V + (100mVRMS) f = 0kHz to 4kHz 40 - - dBc f = 4kHz to 25kHz 37 - - dB f = 25kHz to 50kHz 36 - - dB PCM Code = All 1 Code V- = -5V + (100mVRMS) f = 0kHz to 4kHz 40 - - dBc f = 4kHz to 25kHz 40 - - dB f = 25kHz to 50kHz 36 - - dB V- Power Supply Rejection Receive PSRR Cross Talk Transmit to Receive CTXR VFXI- = 0dBm0 at 1020Hz - -80 -70 dB Cross Talk Receive to Transmit CTRX DR = 0dBm0 at 1020Hz, VFXI- = 0V - -76 -70 dB 4-169 CD22354A, CD22357A Electrical Specifications PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Depends on the Device Used and the BCLKR/CLKSEL Pin - 1.536 - MHz - 1.544 - MHz MCLKX and MCLKR - 2.048 - MHz AC TIMING Frequency of Master Clocks 1/tPM Width of Master Clock High tWMH MCLKX and MCLKR 160 - - ns Width of Master Clock Low tWML MCLKX and MCLKR 160 - - ns Rise Time of Master Clock tRM MCLKX and MCLKR - - 50 ns Fall Time of Master Clock tFM MCLKX and MCLKR - - 50 ns 100 - - ns 485 488 15,725 ns Set-up Time from BCLKX High (and FSX in Long Frame Sync Mode) to MCLKX Falling Edge Period of Bit Clock tSBFM First Bit Clock after the Leading Edge of FSX tPB Width of Bit Clock High tWBH VIH = 2.2V 160 - - ns Width of Bit Clock Low tWBL VIL = 0.6V 160 - - ns Rise Time of Bit Clock tRB tPB = 488ns - - 50 ns Fall Time of Bit Clock tFB tPB = 488ns - - 50 ns Hold Time from Bit Clock Low to Frame Sync tHBF Long Frame Only 0 - - ns Hold Time from Bit Clock High to Frame Sync tHOLD Short Frame Only 0 - - ns Set-up Time from Frame Sync to Bit Clock Low tSFB Long Frame Only 80 - - ns Delay Time from BCLKX High to Data Valid tDBD Load = 150pF plus 2 LSTTL Loads 0 - 180 ns Delay Time to TSX Low tXDP Load = 150pF plus 2 LSTTL Loads - - 140 ns Delay Time from BCLKX Low or FSX Low to Data Output Disabled tDZC 50 - 165 ns Delay Time to Valid Data from FSX or BCLKX, Whichever Comes Later tDZF 20 - 165 ns Set-up Time from DR Valid to BCLKR/X Low tSDB 50 - - ns Hold Time from BCLKR/X Low to DR Invalid tHBD 50 - - ns CL = 0pF to 150pF Set-up Time from FSX/R to BCLKX/R Low tSF Short Frame Sync Pulse (1 or 2 Bit Clock Periods Long) (Note 1) 50 - - ns Hold Time from BCLKX/R Low to FSX/R Low tHF Short Frame Sync Pulse (1 or 2 Bit Clock Periods Long) (Note 1) 100 - - ns 4-170 CD22354A, CD22357A Electrical Specifications (Continued) PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Hold Time from 3rd Period of Bit Clock Low to Frame Sync (FSX or FSR) tHBFI Long Frame Sync Pulse (from 3 to 8-Bit Clock Periods Long) 100 - - ns Minimum Width of the Frame Sync Pulse (Low Level) tWFL 64K Bit/s Operating Mode 160 - - ns NOTE: 1. For short frame sync timing, FSX and FSR must go high while their respective bit clocks are high. Pin Descriptions PIN NO. SYMBOL DESCRIPTION 1 V- 2 GND Analog and digital ground. All signals referenced to this pin. 3 VFRO Analog output of RECEIVE FILTER. 4 V+ Positive power supply, V+ = 5V ±5%. 5 FSR Receive Frame Sync Pulse which enables BCLKR to shift PCM data into DR. FSR is an 8kHz PULSE TRAIN. 6 DR Receive Data Input. PCM data is shifted into DR following the FSR leading edge. 7 BCLKR/CLKSEL The Receive Bit Clock, which shifts data into DR after the frame sync leading edge, may vary from 64kHz to 2.048MHz. Alternatively, the leading edge may be a logic input which selects either 1.536MHz/ 1.544MHz or 2.048MHz for Master Clock in synchronous mode and BCLKX is used for both transmit and receive directions. 8 MCLKR/PDN Receive Master Clock. Must be 1.536MHz, 1.544MHz or 2.048MHz. May be asynchronous with MCLKX, but best performance is realized from synchronous operation. When this pin is continuously connected low, MCLKX is selected for all internal timing. When this pin is continuously connected high, the device is powered down. 9 MCLKX Transmit Master Clock. Must be 1.536MHz, 1.544MHz or 2.048MHz. May be asynchronous with MCLKR, but best performance is realized from synchronous operation. 10 BCLKX The Bit Clock which shifts out the PCM Data on DX. May vary from 64kHz to 2.048MHz, but must be synchronous with MCLKX. 11 DX The THREE-STATE PCM Data Output which is enabled by FSX. 12 FSX Transmit Frame Sync Pulse input which enables BCLKX to shift out the data on DX. FSX is an 8kHz PULSE TRAIN. 13 TSX Open drain output which pulses low during the encoder time slot. 14 GSX Transmit gain adjust. 15 VFXI- Inverting input of the transmit input amplifier. 16 VFXI+ Non-inverting input of the transmit input amplifier. Negative power supply, V- = -5V ±5%. 4-171 CD22354A, CD22357A Functional Description CLOCKING OPTIONS Power Supply Sequencing MASTER CLOCK FREQUENCY SELECTED Do not apply input signal or load on output before powering up VCC supply. Care must be taken to ensure that DX pin goes on common back plane (with other DX pins from other chips). DX pin cannot drive >50mA before Power-Up. This will cause the part to latch up. Asynchronous or Synchronous Clocked 1.536MHz or 1.544MHz 2.048MHz Power-Up Synchronous 0 2.048MHz 1.536MHz or 1.544MHz 1.536MHz or 1.544MHz 2.048MHz When power is first applied, the Power-On reset circuitry initializes the CODEC and places it in a Power-Down mode. When the CODEC returns to an active state from the PowerDown mode, the receive output is muted briefly to minimize turn-on “click”. To power up the device, there are two methods available. 1. A logical zero at MCLK R /PDN will power up the device, provided FSX or FSR pulses are present. 2. Alternatively, a clock (MCLKR) must be applied to MCLKR/ PDN and FSX or FSR pulses must be present. Power-Down Two power-down modes are available. 1. A logical 1 at MCLKR/PDN, after approximately 0.5ms, will power down the device. 2. Alternatively, hold both FSX and FSR continuously low, the device will power down approximately 0.5ms after the last FSX or FSR pulse. Synchronous Operation (Transmit and Receive Sections use the Same Master Clock) The same master clock and bit-clock should be used for the receive and transmit sections. MCLKX (pin 9) is used to provide the master clock for the transmit section; the receive section will use the same master clock if the MCLKR /PDN (pin 8) is grounded (synchronous operation), or at V+ (power-down mode). MCLKR /PDN may be clocked only if a clock is provided at BCLKR /CLKSEL (pin 7) as in asynchronous operation. The BCLKX (pin 10) is used to provide the bit clock to the transmit section. In synchronous operation, this bit clock is also used for the receive section if MCLKR /PDN (pin 8) is grounded. BCLKR /CLKSEL (pin 7) is then used to select the proper internal frequency division for 1.544MHz, 1.536MHz or 2.048MHz operation (see Table below). For 1.544MHz operation, the device automatically compensates for the 193rd clock pulse each frame. Each FSX pulse begins the encoding cycle and the PCM data from the previous encode cycle is shifted out of the enabled DX output on the leading edge of BCLKX. After 8 bitclock periods, the tristate DX output is returned to a high impedance state. With an FSR pulse, PCM data is latched via the DR input on the negative edge of the BCLKX. FSX and FSR must be synchronous with MCLKX. MODE BCLKR /CLKSEL (PIN 7) CD22354A (µ) CD22357A (A) Synchronous 1(or open circuit) Asynchronous Operation (Transmit and Receive Sections use Separate Master Clocks) For the CD22357A, the MCLKX and MCLKR must be 2.048MHz and for the CD22354A must be 1.536MHz or 1.544MHz. These clocks need not be synchronous. However, for best transmission performance, it is recommended that MCLKX and MCLKR be synchronous. For 1.544MHz operation the device automatically compensates for the 193rd clock pulse each frame. FSX starts the encoding operation and must be synchronous with MCLKX and BCLKX. FSR starts the decoding operation and must be synchronous with BCLKR. BCLKR must be clocked in asynchronous operation. BCLKX and BCLKR may be between 64kHz - 2.04MHz. Short-Frame Sync Mode When the power is first applied, the power initialization circuitry places the CODEC in a short-frame sync mode. In this mode both frame sync pulses must be 1 bit-clock period long, with the timing relationship shown in Figure 1. With FSX high during the falling edge of the BCLKX, the next rising edge of BCLKX enables the DX tristate output buffer, which will output the sign bit. The following rising seven edges clock out the remaining seven bits upon which the next falling edge will disable the DX output. With FSR high during the falling edge of the BCLKR (BCLKX in synchronous mode), the next falling edge of BCLKR latches in the sign bit. The following seven edges latch in the seven remaining bits. Long-Frame Sync Mode In this mode of operation, both of the frame sync pulses must be three or more bit-clock periods long with the timing relationship shown in Figure 2. Based on the transmit frame sync FSX, the CODEC will sense whether short or long-frame sync pulses are being used. For 64kHz operation the frame sync pulse must be kept low for a minimum of 160ns. The DX tristate output buffer is enabled with the rising edge of FSX or the rising edge of the BCLKX, whichever comes later and the first bit clocked out is the sign bit. The following seven rising edges of the BCLKX clock out the remaining seven bits. The DX output is disabled by the next falling edge of the BCLKX following the 8th rising edge or by FSX going low whichever comes later. 4-172 CD22354A, CD22357A A rising edge on the receive frame sync, FSR, will cause the PCM data at DR to be latched in on the next falling edge of the BCLKR. The remaining seven bits are latched on the successive seven falling edges of the bit-clock (BCLKX in synchronous mode). Transmit Section The transmit section consists of a gain-adjustable input opamp, an anti-aliasing filter, a low-pass filter, a high-pass filter and a compressing A/D converter. The input op-amp drives a RC active anti-aliasing filter. This filter eliminates the need for any off-chip filtering as it provides 30dB attenuation (Min) at the sampling frequency. From this filter the signal enters a 5th order low-pass filter clocked at 128kHz, followed by a 3rd order highpass filter clock at 32kHz. The output of the high-pass filter directly drives the encoder capacitor ladder at an 8kHz sampling rate. A precision voltage reference is trimmed in manufacturing to provide an input overload of nominally 2.5VPEAK. Transmit frame sync pulse FSX controls the process. The 8-bit PCM data is clocked out at DX by the BCLKX. BCLKX can be varied from 64kHz to 2.048MHz. Receive Section The receive section consists of an expanding D/A converter and a low-pass filter which fulfills both the AT&T D3/D4 specifications and CCITT recommendations. PCM data enters the receive section at DR upon the occurrence of FSR, Receive Frame sync pulse. BCLKR, Receive Data Clock, which can range from 64kHz to 2.048MHz, clocks the 8-bit PCM data into the receive data register. A D/A conversion is performed on the 8-bit PCM data and the corresponding analog signal is held on the D/A capacitor ladder. This signal is transferred to a switched capacitor low-pass filter clocked at 128kHz to smooth the sample-and-hold signal as well as to compensate for the (SIN X)/X distortion. The filter is then followed by a second order Sallen and Key active filter capable of driving a 600Ω load to a level of 7.2dBm. t XDB t DZC t WWL TS X t RM t FM t PM MCLK R MCLK X t WWH BCLKX t SBFM 1 2 3 4 5 6 7 8 t HF t HOLD FSX t SF t DBD DX 1 t HOLD 2 3 4 5 6 2 3 4 5 6 7 t SF 8 8 t HDB t HBD t SDB FSR DR 7 t HF 1 BCLKR t DZC 1 2 3 4 5 FIGURE 1. SHORT FRAME-SYNC TIMING 4-173 6 7 8 CD22354A, CD22357A tWWL t RM tWWH t PM t FM MCLKR MCLKX tWBH tSBFM tSBFM BCLKX 1 tWBL 2 3 4 5 6 7 8 t PB tSFB t FB FSX t RB t HBF t HBFI t DZF t DBD t DZC t DZF DX 1 2 3 4 5 6 7 8 t DZC t HBF BCLKR 1 2 3 4 5 6 7 8 t HBFI FSR t SFB DR 1 t HBD t SDB 2 3 4 5 FIGURE 2. LONG FRAME-SYNC TIMING 4-174 t HBD 6 7 8