SONY CXA1784AS

CXA1784AS
US Audio Multiplexing Decoder
For the availability of this product, please contact the sales office.
Description
The CXA1784AS is an IC designed as a decoder
for the Zenith TV Multi-channel System and also
corresponds with I2C BUS. Functions include stereo
demodulation, SAP (Separate Audio Program)
demodulation, dbx noise reduction and sound
processor. Various kinds of filters are built in while
adjustment, mode control and sound processor
control are all executed through I2C BUS.
42 pin SDIP (Plastic)
Absolute Maximum Ratings (Ta=25°C)
11
• Supply voltage
VCC
• Operating temperature Topr –20 to +75
• Storage temperature
Tstg –65 to +150
• Allowable power dissipation
PD
2.2
Features
• Audio multiplexing decoder, dbx noise reduction
decoder and sound processor are all included in a
single chip. Almost any sort of signal processing is
possible through this IC.
• All adjustments are possible through I2C BUS to
allow for automatic adjustment.
• Various built-in filter circuits greatly reduce external
parts.
• There are two systems for both inputs and outputs,
and each mode control is possible.
Standard I/O Level
• Input level
COMPIN (Pin 17)
AUXIN-L/R (Pins 38 and 37)
• Output level
TVOUT-L/R (Pins 35 and 34)
LSOUT-L/R (Pins 6 and 5)
V
°C
°C
W
Range of Operating Supply Voltage
9±0.5
V
Applications
TV, VCR and other decoding systems for US audio
multiplexing TV broadcasting
Structure
Bipolar silicon monolithic IC
245 mVrms
490 mVrms
490 mVrms
490 mVrms
BASSL1
BASSR2
BASSR1
SURRTC
AUXIN-L
AUXIN-R
NC
TVOUT-L
TVOUT-R
ITIME
VCATC
VCAWGT
VCAIN
VEOUT
VETC
VEWGT
VE
SAPIN
SAPOUT
GND
NOISETC
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
BASSL2
TRER
TREL
SURROUT
LSOUT-R
LSOUT-L
SDA
SCL
DGND
SAD
VGR
IREF
MAININ
MAINOUT
PLINT
STFIL
COMPIN
SAPTC
SUBOUT
STIN
VCC
Pin Configuration (Top View)
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E95430A5Z-PK
22
GND
NOISETC
–2–
ITIME 33
INSW1 &
INSW2
BPF
SAPVCO
STIND
(+6dB)
LPF
SAPVDET
DeEm
AMP
(+4dB)
DeEm
WIDEBAND
"SAPVCO"
LPF
VCA
HPF
LOGIC
VE
NRSW/FOMO/
SAPC
EXT1/EXT2/M1/M2
VCA
MATRIX
PREVOL SURR
SAPTC 18
23
VCC 21
"STEREO"
LPF
1/2
SUBOUT 19
LPF
PLINT 15
FLT
1/4
MAININ 13
VCA
VCO
SURROUND
PREVOL
SW2
SW1
AUXIN-L 38
17
STFIL 16
LFLT
AUXIN-R 37
COMPIN
"STLPF"
STLPF
MAINOUT 14
VOL-L
6
LSOUT-L
BASS
TREBLE
32
VCATC
31
VCAWGT
30
VCAIN
29
VEOUT
28
VETC
27
VEWGT
26
VE
20
STIN
25
SAPIN
24
SAPOUT
7
SDA
8
SCL
9
DGND
10
SAD
12
IREF
11
VGR
IREF
I2 C BUS I/F
SAPFDET
SAPIND
"PONRES"
"SAPLPF"
"SAP"
SW
TREB
SPECTRAL
RMSDET
BASS
LPF
LSOUT-R
LPF
5
STLPF
STVCO
SAPLPF
SAPVCO
VOL-R
RMSDET
TREB
"NOISE"
BASS
NOISE
DET
(L-R)
MATRIX
BASSL2
TREL
TRER
3
2
41 BASSR2
40 BASSR1
1
42 BASSL1
39 SURRTC
34 TVOUT-R
35 TVOUT-L
CXA1784AS
Block Diagram
SURR-VOL
VOL-S
4
SURROUT
VOL-R
VOL-L
CXA1784AS
Pin Description
Pin
No.
Symbol
(Ta = 25 °C, VCC = 9 V)
Pin
voltage
Equivalent circuit
Description
VCC
3k
1
BASSL2
4.0
1
500
41
42
BASSL1
13.2k
4.0
500
10.7k
8.57k
6.89k
41
BASSR2
5.66k
4.0
VCC
4.44k
40
BASSR1
4.0
3.67k
40
15.3k
42
4V
BASS filter pin. (Left channel)
(Connect a 15 nF capacitor
between Pins 1 and 42.)
The cutoff frequency is
determined by the built-in
resistor and the external
capacitance.
BASS filter pin. (Right
channel) (Connect a 15 nF
capacitor between Pins 41
and 40.)
The cutoff frequency is
determined by the built-in
resistor and the external
capacitance.
VCC
3k
2
TRER
4.0
500
4.2k
500
TREBLE filter pin. (Right
channel)
(Connect a 6.8 nF capacitor
between this pin and GND.)
3.42k
2.73k
2.2k
1.8k
TREBLE filter pin. (Left
channel)
(Connect a 6.8 nF capacitor
between this pin and GND.)
1.42k
3
TREL
4.0
VCC
1.17k
4.88k
2
3
VCC
4
SURROUT
4.0
(L - R) signal output pin.
VCC
500
5
LSOUT-R
4.0
LSOUT right channel output
pin.
4
5
500
6
6
LSOUT-L
LSOUT left channel output
pin.
4.0
–3–
CXA1784AS
Pin
No.
Symbol
Pin
voltage
Equivalent circuit
Description
VCC
7.5k
↓ 35µ
2.1V
4k
7
SDA
Serial data I/O pin.
VIH > 3.0 V
VIL < 1.5 V
×2
—
7.5k
×5
4.5k
3k
7
VCC
7.5k
↓ 35µ
2.1V
Serial clock input pin.
VIH > 3.0 V
4k
8
SCL
—
×4
19.5k
3k
VIL < 1.5 V
8
9
DGND
9
—
Digital block GND.
VCC
2V
10
SAD
Slave address control switch.
The slave address is selected
by changing the voltage
applied to this pin.
40k
10
—
80k
10k
3k
11
VGR
1.3V
11k
9.7k
19.4k
147
VCC
11k
×4
11
2.06k
–4–
11k
Band gap reference output
pin. (Connect a 10 µF
capacitor between this pin
and GND.)
CXA1784AS
Pin
No.
Symbol
Pin
voltage
Equivalent circuit
Description
VCC
40k
40k
30k
30k
15k
×2
VCC
12
IREF
1.3V
30p 1.8k
12
147
6.3k
30k
Set the filter and VCO
reference current. The
reference current is adjusted
with the BUS DATA based on
the current which flows to this
pin. (Connect a 62 kΩ (±1%)
resistor between this pin and
GND.)
16k
VCC
23k
23k
↓ 10µ
VCC
13
MAININ
Input the (L + R) signal from
MAINOUT (Pin 14).
4.0V
147
13
47k
4V
VCC
15k
×4
VCC
14
MAINOUT
4.0V
147
(L + R) signal output pin.
14
↓
200µ
1k
VCC
15k
15k
147
15
PLINT
15
6.3V
20k
↓
26µ
20k
20k
↓
50µ
10k
–5–
Pilot cancel circuit loop filter
integrating pin.
(Connect a 1 µF capacitor
between this pin and GND.)
CXA1784AS
Pin
No.
Symbol
Pin
voltage
Equivalent circuit
Description
VCC
3k
3k
150k
16
STFIL
5.3V
4k
75k
4k
16
Stereo block PLL loop filter
integrating pin.
VCC
Audio multiplexing signal
input pin.
147
75k
12k
1k
1k
VCC
11k
11k
11k
27.66k
17
COMPIN
4.0V
500
27.66k
27.66k
500
34.86k
34.86k
24.06k
4V
17
147
VCC
8k
10k
1k
3k
18
SAPTC
4.5V
VCC
4k
↓ 50µ
Set the time constant for the
SAP carrier detection circuit.
(Connect a 4.7 µF capacitor
between this pin and GND.)
18
Vcc
2k
2k
10P
4k
19
SUBOUT
500
4.0V
19
14.4k
2k
2k
2k
4k
500
147
1k
–6–
(L - R) signal output pin.
CXA1784AS
Pin
No.
Symbol
Pin
voltage
Equivalent circuit
Description
VCC
23k
20
STIN
23k
Input the (L - R) signal from
SUBOUT (Pin 19).
4.0V
11.7k
147
147
25
20
25
SAPIN
4.0V
47k
4V
21
VCC
Input the (SAP) signal from
SAPOUT (Pin 24).
47k
4V
20k
—
Supply voltage pin.
21
Vcc
8k
3.3k
10k
1k
22
NOISETC
2k
4k
3.0V
×2
4V
3k
3k
Vcc
Set the time constant for the
noise detection circuit.
(Connect a 4.7 µF capacitor
and a 200 kΩ resistor
between this pin and GND.)
22
23
23
GND
—
Analog block GND.
Vcc
5P
500
24
SAPOUT
4.0V
SAP FM detector output pin.
7.4k
500
24
147
17k
24k
↓ 10µ
4k
↓ 50µ
4V
VCC
7.5k
26
VE
4.0V
Variable de-emphasis
integrating pin.
(Connect a 2700 pF
capacitor and a 3.3 kΩ
resistor in series between
this pin and GND.)
147
26
–7–
CXA1784AS
Pin
No.
Symbol
Pin
voltage
Equivalent circuit
Description
Vcc
2.9V
500
27
VEWGT
4.0V
4V
27
147
500
36k
8k
30k
↓ 8µ
Weight the variable deemphasis control effective
value detection circuit.
(Connect a 0.047 µF
capacitor and a 3 kΩ resistor
in series between this pin and
GND.)
4k
↓ 50µ
Vcc
28
VETC
1.7V
×4
28
×4
20k
↓ 7.5µ
4k
↓ 50µ
Determine the restoration
time constant of the variable
de-emphasis control effective
value detection circuit. (The
specified restoration time
constant can be obtained by
connecting a 3.3 µF capacitor
between this pin and GND.)
Vcc
5P
500
29
VEOUT
4.0V
29
10k
500
Variable de-emphasis output
pin.
(Connect a 4.7 µF non-polar
capacitor between Pins 29
and 30.)
VCC
47k
30
VCAIN
4.0V
20k
VCC
30
–8–
47k
VCA input pin.
Input the variable deemphasis output signal from
Pin 29 via a coupling
capacitor.
CXA1784AS
Pin
No.
Symbol
Pin
voltage
Equivalent circuit
Description
VCC
40k
40k 3p
Weight the VCA control
effective value detection
circuit.
(Connect a 1 µF capacitor
and a 3.9 kΩ resistor in series
between this pin and GND.)
500
31
31
VCAWGT
4.0V
500 147
2.9V
36k
↓
50µ
4k ↓
8µ
30k
8k
VCC
Determine the restoration
time constant of the VCA
control effective value
detection circuit.
(The specified restoration
time constant can be
obtained by connecting a 10
µF capacitor between this pin
and GND.)
32
×4
×4
32
VCATC
1.7V
4k
↓
50µ
20k
↓
7.5µ
VCC
40k
40k 30k
20k
40k 10k
2.6V
33
ITIME
1.3V
30p 1.8k
33
47k
147
25k
×4
Set the reference current for
the effective value detection
timing current. The reference
current is adjusted with the
BUS DATA “SPECTRAL”
based on the current which
flows to this pin.
The timing current determines
the restoration time constant
of the detection circuit and
the variable de-emphasis
characteristics.
(Connect a 43 kΩ (±1%)
resistor between this pin and
GND.)
VCC
3k
34
TVOUT-R
4.0V
500
34
35
35
TVOUT right channel output
pin.
500
TVOUT left channel output
pin.
TVOUT-L
–9–
CXA1784AS
Pin
No.
Symbol
Pin
voltage
36
NC
—
Equivalent circuit
Description
36
36
—
VCC
37
AUXIN-R
Right channel external input
pin.
23k
4.0V
147
37
27.6k
38
47k
38
AUXIN-L
Left channel external input
pin.
4V
4.0V
19.6k
20k
VCC
23k
20k
39
SURRTC
4.0V
20k
40k
500
24k
VCC
500
39
– 10 –
Set the central frequency of
the SURROUND circuit phase
shifter.
The frequency is determined
by the built-in resistor and the
external capacitance.
(Connect a 0.022 µF capacitor
between this pin and GND.)
Vsub
FCsub
THDsub
THDsmax
SNsub
PCsub
THst
HYst
Main overload distortion
Main S/N
Sub output level
Sub LPF frequency
characteristic
Sub distortion
Sub overload distortion
Sub S/N
Sub pilot leak
Stereo ON level
Stereo ON/OFF hysteresis
6
7
– 11 –
8
9
10
11
12
13
14
15
SNmain
THDmmax
Main distortion
17
17
ST
ST
17
17
ST
ST
17
17
ST
ST
17
MONO
17
17
MONO
ST
17
MONO
17
MONO
FCmain
THDm
17
17
Input pin
MONO
MONO
Mode
FCdeem
Vmain
Icc
Symbol
H
Change
PILOT (f ) Level
H
PILOT (f ) 0dB
Mono 1kHz 100% mod.
Pre-em. on
Mono 5kHz 30% mod.
Pre-em. on
Mono 12kHz 30% mod.
Pre-em.on
Mono 1kHz 100% mod.
Pre-em. on
Mono 1kHz 200% mod.
Pre-em off
Mono 1kHz,
Pre-em on
SUB (L-R), 1kHz,
100% mod., NR OFF
SUB (L-R) 12kHz,
30% mod., NR OFF
SUB (L-R) 1kHz,
100% mod., NR OFF
SUB (L-R), 1kHz,
200% mod., NR OFF
SUB (L-R) 1kHz,
NR OFF
No signal
20 log (‘on
level’/’off level’)
0dB=49mVrms
20 log
('100%'/'0%')
20 log
('out'/'in')
20 log
('12k'/'1k')
20 log
('100%'/'0%')
fH BPF
15kLPF
15kLPF
15kLPF
15kLPF
15kLPF
34/35
20 log
('12k'/'1k')
BUS
RETURN
19
19
19
19
19
19
34/35
34/35
34/35
34/35
34/35
Output pin
2.0
-9.0
—
56
—
—
-3.0
150
61
—
—
-3.0
-1.2
440
35
Min.
INSW1 = 0
INSW2 = 1
= 100mVrms
= 200mVrms
= 20mVrms
= 60mVrms
20 log ('5k'/'1k')
15kLPF
Filter
INSW1 = 1
INSW2 = 0
= 490mVrms
= 980mVrms
= 98mVrms
= 294mVrms
Measurement
conditions
INSW1 = 0, = 1
INSW2 = 0, = 1
= 245mVrms
= 490mVrms
= 49mVrms
= 147mVrms
Input signal
Main (L + R) (Pre-Emphasis : OFF)
SUB (L – R) (dbx-TV :OFF)
Pilot
SAP Carrier
fH = 15.734kHz
5
4
Main de-emphasis frequency
characteristic
Main LPF frequency
characteristic
Main output level
2
3
Current consumption
Item
1
No.
COMPIN input level
(100% modulation level)
Electrical Characteristics
8.0
-3.0
-6.0
4.0
-22
—
2.0
1.0
1.0
230
—
0.5
0.5
1.0
1.0
540
53
Max.
-30
64
0.2
0.1
-0.5
190
69
0.15
0.1
-1.0
0
490
44
Typ.
dB
dB
dB
%
dB
mVrms
dB
%
dB
mVrms
mA
Unit
(Ta = 25°C, Vcc = 9V)
CXA1784AS
SAP distortion
19
– 12 –
STRsep1
STLsep2
STRsep2
ST separation 1 R → L
ST separation 2 L → R
ST separation 2 R → L
TVOUT output level
TVOUT
cross talk
27
28
29
30
31
33
TVOUT
muted amount
STLsep1
ST separation 1 L → R
26
32
HYsap
SAP ON/OFF hysteresis
25
ST
ST
ST
ST
SAP
EXT
INT
EXT
CTtv2
MUtv1
MUtv2
INT
THsap
SAP ON level
24
SAP
CTtv1
Ndbx
dbx out noise level
23
SAP
EXT
Smute
SAP soft mute
22
SAP
SAP
SAP
SAP
Mode
Vtv
SNsap
SAP S/N
THDsap2
THDsap1
FCsap
Vsap2
Vsap1
Symbol
21
20
SAP LPF frequency
characteristic
SAP output level
Item
18
17
16
No.
37/38
17
17
37/38
37/38
17
17
17
17
17
17
17
17
17
17
Input pin
Measurement
conditions
0dB=147mVrms
ST-L 300Hz 30% mod.
NR ON
ST-R 300Hz 30% mod.
NR ON
ST-L 3kHz 30% mod.
NR ON
ST-R 3kHz 30% mod.
NR ON
Sine wave 1kHz,
490mVrms
Sine wave 1kHz,
490mVrms
MONO 1kHz, 100%,
Pre-em. on
MONO 1kHz, 100%,
Pre-em. on
Sine wave 1kHz,
490mVrms
20 log (M1="0"/M1="1")
20 log (M1="0"/M1="1")
1kBPF
34/35
34/35
1kBPF
0dB=490mVrms
EXT → INT
0dB=490mVrms
INT → EXT
34/35
34/35
34/35
34/35
BUS
RETURN
34/35
24
24
34/35
24
24
34/35
24
Output pin
34/35
15kLPF
15kLPF
15kLPF
15kLPF
15kLPF
15kLPF
15kLPF
15kLPF
Filter
0dB=490mVrms
SAP Carrier (5fH) Level 20 log(‘on
level’/’off level’)
Change
No signal
SAP 1kHz, 100% mod.
NR OFF
SAP 1kHz 100% mod.
NR OFF
SAP 1kHz 100% mod.
NR ON
SAP 10kHz, 30% mod. 20 log
('10k'/'1k')
NR OFF
SAP 1kHz 100% mod.
NR OFF
SAP 1kHz 100% mod.
NR ON
20 log
SAP 1kHz, NR OFF
('100%'/'0%')
Input signal
—
—
—
-0.5
23
23
23
23
2.0
-12.0
—
-8.5
46
—
—
-3.0
370
150
Min.
-80
-75
-75
0
35
35
35
35
4.0
-9.0
-75
-7.0
55
0.6
2.5
0
490
190
Typ.
-70
-70
-59
0.5
—
—
—
—
6.0
-6.0
-54
-5.5
—
1.5
6.0
2.5
610
230
Max.
dB
dBm
dB
%
dB
mVrms
Unit
CXA1784AS
MUls
OSls
THDls
SNls
TBmax
TBmin
TTmax
TTmin
VOLmin
SVOLmin
LSOUT output level
LSOUT cross talk
LSOUT muted amount
LSOUT DC offset
LSOUT distortion
LSOUT S/N
LSOUT overload distortion
BASS maximum value
BASS minimum value
TREBLE maximum value
TREBLE minimum value
Volume minimum value
SURROUT volume minimum
value
38
39
40
41
42
– 13 –
43
44
45
46
47
48
49
50
THDlsmax
EXT
EXT
EXT
EXT
EXT
EXT
EXT
EXT
37/38
37/38
37/38
37/38
37/38
37/38
37/38
37/38
37/38
—
INT
EXT
EXT
37/38
17
37/38
37/38
17
37/38
37/38
37/38
EXT
EXT
INT
CTls1
CTls2
EXT
Vls2
INT
TVOUT overload distortion
37
EXT
Vls1
SNtv
TVOUT S/N
36
EXT
—
INT
EXT
EXT
THDtv
TVOUT distortion
35
Input pin
Mode
THDtvmax
OStv
TVOUT DC offset
34
Symbol
Item
No.
Sine wave 1kHz,
490mVrms
Sine wave 1kHz,
490mVrms
Sine wave 1kHz,
2Vrms
Sine wave 100Hz,
245mVrms
Sine wave 100Hz,
245mVrms
Sine wave 10kHz,
245mVrms
Sine wave 10kHz,
245mVrms
Sine wave 1kHz,
490mVrms
Sine wave 1kHz,
490mVrms
No signal
Sine wave 1kHz,
490mVrms
Sine wave 1kHz,
490mVrms/No signal
Sine wave 1kHz,
2Vrms
MONO 1kHz
100%, Pre-em. on
Sine wave 1kHz,
490mVrms
Sine wave 1kHz,
490mVrms
MONO 1kHz
100%, Pre-em. on
Sine wave 1kHz,
490mVrms
No signal
Input signal
VOL-SURR="0"
0dB=490mVrms
0dB=490mVrms
VOL-L="0", VOL-R="0"
BASS="F"
0dB=245mVrms
BASS="0"
0dB=245mVrms
TREBLE="F"
0dB=245mVrms
TREBLE="0"
0dB=245mVrms
signal')
20 lgo ('490mVrms'/'No
when there is no signal
Mute (M2=0)/DC difference
20 log (M2="0"/M2="1")
0dB=490mVrms
EXT → INT
0dB=490mVrms
INT → EXT
0dB=490mVrms
0dB=490mVrms
signal')
20 log ('490mVrms'/'No
when there is no signal
Mute (M1=0)/DC difference
Measurement
conditions
1kBPF
1kBPF
15kLPF
15kLPF
15kLPF
1kBPF
1kBPF
15kLPF
15kLPF
15kLPF
Filter
4
5/6
5/6
5/6
5/6
5/6
5/6
5/6
5/6
5/6
5/6
5/6
5/6
34/35
34/35
34/35
34/35
Output pin
—
—
-13
11
-13
11
—
74
—
-25
—
—
-0.9
—
74
—
-25
Min.
13
-11
12
-12
-80
-70
-70
-11
-12
-80
13
1.0
—
0.5
25
-70
-59
0.9
1.0
—
0.5
25
Max.
12
0.1
77
0.01
0
-80
-75
0
0.1
77
0.01
0
Typ.
dB
%
dB
%
mV
dB
%
dB
%
mV
Unit
CXA1784AS
52
51
No.
SURROUND frequency
characteristic 1
SURROUND frequency
characteristic 2
Item
EXT
EXT
Sr2
Mode
Sr1
Symbol
38
38
Input pin
Sine wave 330Hz,
490mVrms
Sine wave 10kHz,
490mVrms
Input signal
Measurement
conditions
SURR="1"
0dB=490mVrms
SURR="1"
0dB=490mVrms
Filter
6
6
Output pin
4.5
1.5
Min.
6.0
3.0
Typ.
7.5
4.6
Max.
dB
Unit
CXA1784AS
– 14 –
CXA1784AS
I2C BUS block items (SDA, SCL)
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
Item
High level input voltage
Low level input voltage
High level input current
Low level input current
Low level output voltage SDA (Pin 7) during 3 mA inflow
Maximum inflow current
Input capacitance
Maximum clock frequency
Minimum waiting time for data change
Minimum waiting time for start of data transfer
Low level clock pulse width
High level clock pulse width
Minimum waiting time for start preparation
Minimum data hold time
Minimum data preparation time
Rise time
Fall time
Minimum waiting time for stop preparation
I2C BUS load conditions:
Symbol
Min.
Typ.
Max.
VIH
VIL
IIH
IIL
VOL
IOL
CI
fSCL
t
3.0
0
—
—
0
3
—
0
4.7
4.0
4.7
4.0
4.7
0
250
—
—
4.7
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
5.0
1.5
10
10
0.4
—
10
100
—
—
—
—
—
—
—
1
300
—
BUF
t
:STA
HD
t
t
LOW
HIGH
t
t
t
:STA
SU
:DAT
HD
:DAT
SU
t
t
R
t
F
:STO
SU
Unit
V
µA
V
mA
pF
kHz
µs
ns
µs
ns
µs
Pull-up resistor 4 kΩ (Connect to +5 V)
Load capacity 200 pF (Connect to GND)
I2C BUS Control Signal
SDA
tBUF
tHD;STA
tF
tR
SCL
P
S
tHD;STA
tLOW
tHD;DAT
tHIGH
tSU;STA
tSU;DAT
– 15 –
Sr
tSU;STO
P
– 16 –
C1
35
TVOUT-L
36
NC
37
AUXIN-R
38
AUXIN-L
39
SURROUT SURRTC
40
BASSR1
41
BASSR2
BASSL1
BASSL2
15n
C2
2
TRER
15n
6.8n
C4
3
TREL
6.8n
C6
C5
4
4.7µ
0.022µ
AC
4.7µ
C7
5
LSOUT-R
4.7µ
C8
C9
4.7µ
6
2
34
TVOUT-R
LSOUT-L
C10
4.7µ
R1
7
AC
V4
SDA
SIGNAL
GENERATOR
220
4.7µ
R2
8
I C BUS DATA
33
ITIME
42
1
22
23
24
25
26
27
28
29
30
31
32
VCATC
C3
VCAWGT
V3
VCAIN
SCL
220
C11
4.7µ
SAD
10
DGND
9
C12
11
VGR
R4
S1
DGND
R3
43k
METAL ±1%
10µ
C13
10µ
C14
TANTALUM
12
1µ
R5
C15
BUFF
IREF
62k
METAL ±1%
3.9k
C16
4.7µ
14
13
4.7µ
C17
15kHz LPF
fHBPF
1kHz BPF
MAININ
FILTERS
VEOUT
MAINOUT
C18
3.3µ
15
1µ
C20
S2
VETC
SIGNAL
GENERATOR
VEWGT
S3
VE
S4
SAPIN
S5
SAPOUT
S6
GND
S7
NOISETC
PLINT
R6
16
STFIL
C22
GND
AC
V2
SIGNAL
GENERATOR
17
COMPIN
MEASURES
C19
TANTALUM
0.047µ R7
0.47µ C21 2.2k
0.22µ
3k
2700p
C23
4.7µ
C24
R8
3.3k
C25
18
4.7µ
SAPTC
4.7µ
19
C27
20
SUBOUT
C26
4.7µ
STIN
GND
4.7µ
C29
21
VCC
C28
R9
100µ
200k
VCC
A
GND
9V
V1
Electrical Characteristics Measurement Circuit
CXA1784AS
CXA1784AS
I2C BUS Register Data Standard Setting Values
Register
ATT
STVCO
SAPVCO
SAPLPF
STLPF
SPECTRAL
WIDEBAND
TEST-DA
TEST1
PRE-VOL
VOL-L
VOL-R
VOL-SURR
TREBLE
BASS
SURR
NRSW
FOMO
EXT1
EXT2
EXTFOMO
M1
M2
INSW1
INSW2
SAPC
Number Classifi- Standard
of bits cation
setting
4
6
4
4
6
6
6
1
1
4
6
6
6
4
4
1
1
1
1
1
1
1
1
1
1
1
Classification A:
U:
S:
T:
A
A
A
A
A
A
A
T
T
U
U
U
U
U
U
U
U
U
U
U
U
U
U
S
S
S
9
1F
8
8
1F
1F
1F
0
0
F
3F
3F
3F
8
8
0
—
—
0
0
0
1
1
—
—
—
Contents
Setting value when electrical
characteristics are measured
Center point
Adjustment point
Normal mode
Standard setting value
F=0dB
3F=0dB
3F=0dB
3F=0dB
7 or 8=0dB
7 or 8=0dB
Surround OFF
According to the modecontrol table
TV decoder output selection
Standard setting value
External forced MONO OFF
Standard setting value
Mute OFF
Fixed by the set specifications
Adjustment
User control
Proper to set
Test
– 17 –
Standard setting value
CXA1784AS
List of Adjustment Contents
Adjustment
Adjustment
item
data
1 MAIN VCA
ATT
2 ST VCO
STVCO
3 SAP VCO
4
5
ST & dbx
FILTER
SAP
FILTER
Low frequency
6
ST separation
High frequency
ST separation
SAPVCO
STLPF
SAPLPF
WIDEBAND
SPECTRAL
Input pin
∗Input
signal data
COMPIN 100Hz
Measurement
245mVrms level
None
None
COMPIN
(Pin 17)
(78.67k)
147mVrms
COMPIN 9.4kHz
(Pin 17)
(Pin 17)
(Pin 17)
300Hz
COMPIN ST-L 30%
(Pin 17)
frequency
STA7
(SAPVCO1)
STA8
(SAPVCO2)
STA3
STA4
110mVrms (SAPLPF)
COMPIN ST-L 30%
3kHz
setting
as possible
TVOUT-R output Adjust as close to 62.936 kHz as
600mVrms (STLPF)
COMPIN 88kHz
Test mode
TVOUT-L output Adjust as close to 490 mVrms
(Pin 17)
5fH
Adjustment contents
TVOUT-R output
level
TVOUT-R output
level
possible
TEST-DA=1
Adjust to the center of the
SAPVCO1 = 0, SAPVCO2 = 1
condition
Adjust to the center of the
STLPF = 1 condition
Adjust to the center of the
SAPLPF = 1 condition
TEST1=1
TEST1=1
Minimize the output level
Minimize the output level
∗ This is the case when standard input level is 245mVrms. When this level is 100mVrms or
490mVrms, input signal during adjustment is varied according to the ratio of these level.
– 18 –
CXA1784AS
Adjustment Method (Input signal level is the case when standard input signal level is 245mVrms)
1 ATT adjustment
1. TEST BIT is set to “TEST1 = 0” and “TEST-DA = 0”.
2. Input a 100 Hz, 245 mVrms sine wave signal to COMPIN and monitor the TVOUT-L output level.
Then, adjust the “ATT” data for ATT adjustment so that the TVOUT-L output goes to the standard
value.
3. Adjustment range: ±30%
Adjustment bits:
4 bits
2
Stereo VCO adjustment
1. TEST BIT is set to “TEST1 = 0” and “TEST-DA = 1”.
2. Monitor the TVOUT-R output (4fH free running) frequency in a no input state, and adjust “STVCO”
adjustment data so that this frequency is as close to 4fH (62.936 kHz) as possible.
3. Adjustment range: ±20%
Adjustment bits:
6 bits
3
SAPVCO adjustment
1. TEST BIT is set to “TEST1 = 0” and “TEST-DA = 0”.
2. Input a 5fH (SAP carrier , 78.67 kHz) , 147 mVrms sine wave signal to COMPIN. While monitoring the
STATUS FLAG (STA7, STA8) condition, adjust “SAPVCO” adjustment data.
3. Adjustment range: ±20%
Adjustment bits:
4 bits
Align SAPVCO with the center of the STA7 = 0 and STA8 = 1 (adjustment OK) condition range.
Adjustment point
0
F
1
0
Measurement data
STA7 "SAPVCO1"
1
0
4
Control data
"SAPVCO"
STA8 "SAPVCO2"
Stereo block dbx filter adjustment
1. TEST BIT is set to “TEST1 = 1” and “TEST-DA = 0”.
2. Input a 9.4 kHz, 600 mVrms sine wave signal to COMPIN. While monitoring the STATUS FLAG
(STA3) condition, adjust the “STLPF” adjustment data.
3. Adjustment range: ±20%
Adjustment bits:
6 bits
Align STLPF with the center of the STA3 = 1 (adjustment OK) condition range.
Adjustment point
3F
0
1
0
Control data
"STLPF"
Measurement data
STA3 "STLPF"
– 19 –
CXA1784AS
5
SAP block filter adjustment
1. TEST BIT is set to “TEST1 = 1” and “TEST-DA = 0”.
2. Input a 88 kHz, 110 mVrms sine wave signal to COMPIN. While monitoring the STATUS FLAG (STA4)
condition, vary and adjust the “SAPLPF” adjustment data.
3. Adjustment range: ±20%
Adjustment bits:
4 bits
Align SAPLPF with the center of the STA4 = 1 (adjustment OK) condition range.
Adjustment point
0
F
1
0
6
Control data
"SAPLPF"
Measurement data
STA4 "SAPLPF"
Separation adjustment
1. TEST BIT is set to “TEST1 = 0” and “TEST-DA = 0”.
2. Set the unit to stereo mode and input the left channel only signal (modulation factor 30%, frequency
300 Hz NR-ON) to COMPIN. At this time, adjust the “WIDEBAND” adjustment data to reduce TVOUTR output to the minimum.
3. Next, set the frequency only of the input signal to 3 kHz and adjust the “SPECTRAL” adjustment data
to reduce TVOUT-R output to the minimum.
4. Then, the adjustments in 2 and 3 above are performed to optimize the separation.
5. “WIDEBAND”
“SPECTRAL”
Adjustment range: ±30%
Adjustment range: ±15%
Adjustment bits:
6 bits
Adjustment bits: 6 bits
– 20 –
CXA1784AS
Description of Operation
The US audio multiplexing system possesses the base band spectrum shown in Fig. 1.
PEAK DEV
kHz
50
AM-DSB-SC
50
L-R
dbx-TV
NR
L+R
50-15kHz
PILOT
25
25
15
SAP
dbx-TV NR
FM 10kHz
50-10kHz
5
2fH
fH
3fH
4fH
TELEMETRY
FM 3kHz
3
5fH
6fH
f
6.5fH
fH=15.734kHz
Fig. 1. Base band spectrum
2fHL0°
PLL
fHL90°
(VCO 8fH)
DET
fHL0°
STEREO LPF
(COMPIN)
17
I 2C BUS
DECODER
MODE
CONTROL
PILOT
MAIN LPF DE.EM
MVCA
(MAIN IN)
(MAIN OUT)
PILOT
14
CANCEL
13
4.7µ
L+R
SUB LPF
L-R (DSB)
WIDEBAND (SUBOUT) (ST IN)
SUBVCA
DET
19
MATRIX
20
4.7µ
L-R
NR SW
SAP(FM)
SAP BPF
DET
INJ.
SAP LPF
A
dbx-TV
TO
B
(Rch)
BLOCK
(SAP OUT)
24
LOCK
(SAP IN)
NOISE
DET
I 2C BUS
DECODER 4.7µ
25
MODE
CONTROL
I 2C BUS
DECODER
MODE
CONTROL
SAP
DET
Fig. 2. Overall block diagram (See Fig. 3 for the dbx-TV block)
20
NR SW
A
(Lch)
VARIABLE
FIXED
DEEMPHASIS DEEMPHASIS (VE OUT)
IN)
30
29
4.7µ
25
HPF
RMS
LPF
DET
LPF
RMS
DET
Fig 3. dbx-TV block
– 21 –
(VCA
B
VCA
TO
MATRIX
SW
CXA1784AS
(TVOUT-L)(TVOUT-R)
35 34
(LSOUT-L)
VOL-L
SW1
6
(AUXIN-L)
BASS
TREBLE
(LSOUT-R)
38
SW2
PREVOL
SURROUND
VOL-R
37
5
(AUXIN-R)
+
(Lch) (Rch)
(SURROUT)
VOL-S
4
from MATRIX
Fig. 4. Sound processor block
(1) L + R (MAIN)
After the audio multiplexing signal input from COMPIN (Pin 17) passes through MVCA, the SAP signal
and telemetry signal are suppressed by STEREO LPF. Next, the pilot signals are canceled. Finally, the
L - R signal and SAP signal are removed by MAIN LPF, and frequency characteristics are flattened
(de-emphasized) and input to the matrix.
(2) L - R (SUB)
The L - R signal follows the same course as L + R before the pilot signal is canceled. L - R has no
carrier signal, as it is a suppressed-carrier double-sideband amplitude modulated signal (DSB-AM
modulated). For this reason, the pilot signal is used to regenerate the carrier signal (quasi-sine wave)
to be used for the demodulation of the L - R signal. In the last stage, the residual high frequency
components are removed by SUB LPF and the L - R signal is input to the dbx-TV block via the NRSW
circuit after passing through SUBVCA.
(3) SAP
SAP is an FM signal using 5fH as a carrier as shown in the Fig. 1. First, the SAP signal only is
extracted using SAP BPF. Then, this is subjected to FM detection. Finally, residual high frequency
components are removed and frequency characteristics flattened using SAP LPF, and the SAP signal
is input to the dbx-TV block via the NRSW circuit. When there is no SAP signal, the Pin 24 output is
soft muted.
(4) Mode discrimination
Stereo discrimination is performed by detecting the pilot signal amplitude. SAP discrimination is
performed by detecting the 5fH carrier amplitude. NOISE discrimination is performed by detecting the
noise near 25 kHz after FM detection of SAP signal.
(5) dbx-TV block
Either the SAP signal or L - R signal input respectively from ST IN (Pin 20) or SAP IN (Pin 25) is
selected by the mode control and input to the dbx-TV block.
The input signal then passes through the fixed de-emphasis circuit and is applied to the variable deemphasis circuit. The signal output from the variable de-emphasis circuit passes through an external
capacitor and is applied to VCA (voltage control amplifier). Finally, the VCA output is converted from a
current to a voltage using an operational amplifier and then input to the matrix.
– 22 –
CXA1784AS
The variable de-emphasis circuit transmittance and VCA gain are respectively controlled by Each of
effective value detection circuits. Each of the effective value detection circuits passes the input signal
through a predetermined filter for weighting before the effective value of the weighted signal is
detected to provide the control signal.
(6) Matrix, SW1, SW2
The signals (L + R, L - R, SAP) input to “MATRIX” become the outputs for the ST-L, ST-R, MONO and
SAP signals according to the BUS data and whether there is ST/SAP discrimination.
“SW1” and “SW2” switch the “MATRIX” output signal, external input signal (input to AUXIN-L, R (Pins
38 and 37)) and external forced MONO.
Signals selected by “SW1” are output to TVOUT.
Signals selected by “SW2” pass through the sound processor and are output to LSOUT.
(7) Sound processor block
The sound processor block contains “PREVOL”, “BASS/TREBLE” tone control functions,
“SURROUND” (quasi-surround function) and “VOLUME”.
BASS:
±12 dB (±1.7 dB/STEP at 100 Hz)
TREBLE: ±12 dB (±1.7 dB/STEP at 10 kHz)
VOLUME: 0 to -80 dB (-1.25 dB/STEP)
“PREVOL” controls the input signal level of the sound processor block. When turning on the bass
boost, treble boost or surround, attenuate the input signal to the sound processor block using
“PREVOL” so that the signal is not dissipated inside the processor.
PREVOL: 0 to -13.75 dB (-1.25 dB/STEP)
(8) Surround
At “SURROUND”, the L and R differential components are phase-shifted and these components are
added to the left and right channels.
When surround is OFF (SURR = 0)
Inputs are output as is.
Lout = Lin
Rout = Rin
{
When surround is ON (SURR = 1)
1-jωRC
Lout = Lin(Lin-Rin)
1+jωRC
1-jωRC
Rout = Rin+
(Lin-Rin)
1+jωRC
R = 24 kΩ (IC on-chip)
C = 0.022 µF (Externally attached to Pin 39)
{
{
(Lin, Lout) and (Rin, Rout) indicate the left- and right- channel I/O of the surround circuit.
– 23 –
CXA1784AS
(9) Others
“MVCA” is a VCA which adjusts the input signal level to the standard level of this IC.
Standard input level can be selected by INSW1 or INSW2.
“Bias” supplies the reference voltage and reference current to the other blocks. The current flowing to
the resistor connecting IREF (Pin 12) and ITIME (Pin 33) with GND become the reference current.
Standard input and output levels
Input pin
COMPIN
AUXIN
INSW1
0
1
1
0
—
INSW2
0
1
0
1
—
Input level
TVOUT output level
LSOUT output level∗3
490mVrms∗2
490mVrms∗2
490mVrms
490mVrms
245mVrms∗1
490mVrms∗1
100mVrms∗1
490mVrms
∗1 MONO, 25kHz Deviation, Pre-Em. off
∗2 MONO, 25kHz Deviation, Pre-Em. on
∗3 VOLUME MAX, PREVOL MAX
– 24 –
CXA1784AS
Register Specifications
Slave address
SAD pin
GND
VCC
SLAVE RECEIVER
80H
8AH
SLAVE TRANSMITTER
81H
8BH
Register table
SUB ADDRESS
MSB
LSB
BIT7
BIT6
BIT5
∗∗∗∗0000
INSW2
INSW1 TEST-DA
∗∗∗∗0001
∗
∗∗∗∗0010
(SAPVCO (4) SAP VCO adj)
∗∗∗∗0011
∗
∗∗∗∗0100
∗
∗∗∗∗0101
∗
∗∗∗∗0110
EXTFOMO EXT1
EXT2
∗∗∗∗0111
∗
∗∗∗∗1000
∗
∗∗∗∗1001
∗
∗∗∗∗1010
∗
∗∗∗∗1011
∗
∗∗∗∗1100
∗
DATA
BIT4
BIT3
BIT2
BIT1
BIT0
TEST1
ATT (4) INPUT LEVEL adj
STVCO (6) STEREO VCO adj
(SAPLPF (4) SAP FILTER adj)
STLPF (6) ST FILTER adj
SPECTRAL (6)
WIDEBAND (6)
M2
NRSW
FOMO
SAPC
M1
SURR
PR-VOL (4) Pre vol cont.
VOL-L (6) Lch vol cont.
VOL-R (6) Rch vol cont.
VOL-SURR (6) Surr vol cont.
TREBLE (4)
BASS (4)
∗: Don't Care
Status Registers
When TEST1 = 0
STA1
STA2
STA3
STA4
STA5
STA6
STA7
STA8
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
POWER
ON RESET
STEREO
SAP
NOISE
—
—
SAP VCO1
SAP VCO2
When TEST1 = 1
STA1
STA2
STA3
STA4
STA5
STA6
STA7
STA8
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
POWER
ON RESET
STEREO
STLPF
SAPLPF
—
—
—
—
– 25 –
CXA1784AS
Description of Registers
Control registers
Register
Number of bits
ATT
4
STVCO
6
SAPVCO
4
SAPLPF
4
STLPF
6
SPECTRAL
6
WIDEBAND
6
Classification∗
A
A
A
A
A
A
A
TEST-DA
1
T
TEST1
1
T
PRE-VOL
VOL-L
VOL-R
VOL-SURR
TREBLE
BASS
4
6
6
6
4
4
U
U
U
U
U
U
SURR
1
U
NRSW
1
U
FOMO
1
U
EXT1
1
U
EXT2
1
U
EXTFOMO
1
U
M1
1
U
M2
1
U
INSW1
INSW2
1
1
S
S
SAPC
1
S
Contents
Input level adjustment
STEREO VCO free running frequency adjustment
SAP VCO free running frequency adjustment
SAP filter adjustment
STEREO and dbx filter adjustment
Adjustment of stereo separation (3 kHz)
Adjustment of stereo separation (300 Hz)
Turn to DAC test mode and STVCO adjustment mode by
means of TEST-DA = 1.
Turn to test mode by means of TEST = 1. (Adjustment of
STLPF and SAPLPF)
Input signal level control of sound processor block
LSOUT-L output signal level control
LSOUT-R output signal level control
SURROUT output signal level control
LSOUT output treble control
LSOUT output bass control
Selection of quasi-surround function ON/OFF (0: OFF, 1:
ON)
Selection of the output signal (Stereo mode, SAP mode)
Turn to forced MONO by means of FOMO = 1. (Left channel
only is MONO during SAP output.)
Selection of TV mode or external input mode for TVOUT
output
Selection of TV mode or external input mode for LSOUT
output
Forced MONO for external input (1: forced MONO ON)
Selection of TVOUT mute ON/OFF
(0: mute ON, 1: mute OFF)
Selection of LSOUT mute ON/OFF
(0: mute ON, 1: mute OFF)
Select of standard input level.
Select of standard input level.
Selection of SAP mode or L + R mode according to the
presence of SAP broadcasting
∗ Classification U: User control
A: Adjustment
S: Proper to set
T: Test
– 26 –
CXA1784AS
Status registers
Register
PONRES
STEREO
SAP
NOISE
STLPF
SAPLPF
SAPVCO1
SAPVCO2
Number of bits
1
1
1
1
1
1
1
1
Contents
POWER ON RESET detection;
1: RESET
Stereo discrimination of the COMPIN input signal;
1: Stereo
SAP discrimination of the COMPIN input signal;
1: SAP
Noise level discrimination of the SAP signal;
1: Noise
Status of STEREO filter adjustment;
1: OK range
Status of SAP filter adjustment;
1: OK range
Status 1 of SAP VCO free running frequency adjustment;0: OK range
Status 2 of SAP VCO free running frequency adjustment;1: OK range
Description of Control Registers
ATT (4):
Adjust the signal level input to COMPIN (Pin 17) to the standard input level.
Variable range of the input signal:
standard input level -5.0 dB to +3.0 dB
0 = Level min.
F = Level max.
STVCO (6):
Adjust STEREO VCO free running frequency (fo).
Variable range:
fo ±20%
0 = Free running frequency min.
3F= Free running frequency max.
SAPVCO (4):
Adjust SAPVCO free running frequency (fo).
Variable range:
fo ±20%
0 = Free running frequency min.
F = Free running frequency max.
SAPLPF (4):
Adjust the filter fo of the SAP block.
Variable range:
fo ±20%
0 = Frequency min.
F = Frequency max.
STLPF (6):
Adjust the filter fo of the ST and dbx blocks.
Variable range:
fo ±20%
0 = Frequency min.
3F= Frequency max.
SPECTRAL (6): Perform high frequency (fs = 3 kHz) separation adjustment.
0 = Level max.
3F= Level min.
WIDEBAND (6): Perform low frequency (fs = 300 Hz) separation adjustment.
0 = Level min.
3F= Level max.
– 27 –
CXA1784AS
TEST1 (1):
Set filter adjustment mode.
0 = Normal mode
1 = STLPF (STA3) and SAPLPF (STA4) adjustment mode
In addition, the following outputs are present at Pins 35 and 34.
TVOUT-L (Pin 35):
SAP BPF OUT
TVOUT-R (Pin 34):
NR BPF OUT
TEST-DA (1):
Set DAC output test mode and STVCO adjustment mode.
0 = Normal mode
1 = DAC output test mode and STVCO adjustment mode
In addition, the following outputs are present at Pins 35 and 34.
TVOUT-L (Pin 35):
DA control DC level
TVOUT-R (Pin 34):
STEREO VCO oscillation frequency (4fH)
PRE-VOL (4):
Input signal level control of sound processor block
When turning on the bass boost, treble boost or surround, attenuate the input signal to the
sound processor block using “PREVOL” so that the signal is not dissipated inside the
processor.
4 = Volume Min. (-13.75 dB)
F = Volume Max. (0 dB)
-1.25 dB/STEP
VOL-L (6):
LSOUT-L output signal level control
0 = Volume Min. (-80 dB)
3F= Volume Max. (0 dB)
-1.25 dB/STEP
VOL-R (6):
LSOUT-R output signal level control
0 = Volume Min. (-80 dB)
3F= Volume Max. (0 dB)
-1.25 dB/STEP
VOL-SURR (6): SURROUT output signal level control
0 = Volume Min. (-80 dB)
3F= Volume Max. (0 dB)
-1.25 dB/STEP
TREBLE (4):
LSOUT output treble control
0 = Treble Min.
7 & 8 = Treble Center (0 dB)
F = Treble Max.
BASS (4):
LSOUT output bass control
0 = Bass Min.
7 & 8 = Bass Center (0 dB)
F = Bass Max.
– 28 –
CXA1784AS
SURR (1):
Surround function selection
0 = Surround OFF
1 = Surround ON
NRSW (1):
Select stereo mode or SAP mode
0 = Stereo mode
1 = SAP mode
FOMO (1):
Select forced MONO mode
0 = Normal mode
1 = Forced MONO mode
SAPC (1):
Select the SAP signal output mode
When there is no SAP signal, the conditions for selecting SAP output are selected by
SAPC.
0 = L + R output is selected
1 = SAP output is selected
INSW1 (1) &
INSW2 (1):
Select standard input level of COMPIN(Pin 17)
Standard input level
INSW1 = 0 , INSW2 = 0
245mVrms
=1,
=1
}
INSW1 = 1 , INSW2 = 0
INSW1 = 0 , INSW2 = 1
490mVrms
100mVrms
EXT1 (1):
Select TV mode or external input mode for TVOUT output.
0 = TV mode
1 = External input mode
EXT2 (1):
Select TV mode or external input mode for LSOUT output.
0 = TV mode
1 = External input mode
EXT-FOMO (1): Turn external input to forced MONO.
0 = Normal mode
1 = External input is forced MONO.
Input the same signal to both AUXIN-L and AUXIN-R.
M1 (1):
Mute the TVOUT-L and TVOUT-R output.
0 = Mute ON
1 = Mute OFF
M2 (1):
Mute the LSOUT-L and LSOUT-R output.
0 = Mute ON
1 = Mute OFF
– 29 –
CXA1784AS
Description of Mode Control
Priority ranking: M1/M2 > EXT1/EXT2 > TEST-DA > TEST1 > (NRSW & FOMO & SAPC)
Mode control
SAPC=0
“Select dbx input and TV decoder output”
Conditions: FOMO = 0
NRSW = 0 (MONO or ST output)
SAPC=1
“Select dbx input and TV decoder output”
Conditions: FOMO = 0
NRSW = 0 (MONO or ST output)
• During ST input:
As on the left
• During other input:
NRSW
left channel:L,
right channel: R
left channel:L + R,
right channel: L + R
NRSW = 1 (SAP output)
• When there is “SAP” during SAP
discrimination
- left channel: SAP, right channel: SAP
• When there is “No SAP”, output is the
same as when NRSW = 0.
NRSW = 1 (SAP output)
• Regardless of the presence of SAP
discrimination,
dbx input: “SAP”
left channel: SAP, right channel: SAP
However, when there is no SAP, SAPOUT
output is soft muted (-7 dB)
“Forced MONO”
FOMO
SAPC
M1/M2
EXT1/EXT2
TEST1
TEST-DA
FOMO = 1
• During SAP output: left channel: L + R, right channel: SAP
• During ST or MONO output: left channel: L + R, right channel: L + R
Change the selection conditions for “MONO or ST output” and “SAP output”.
SAPC = 0:
Switch to SAP output when there is SAP discrimination.
Do not switch to SAP output when there is no SAP discrimination.
SAPC = 1:
Switch to SAP output regardless of whether there is SAP discrimination.
“MUTE”
M1 = 0: TVOUT output is muted.
M2 = 0: LSOUT output is muted.
“TV mode/external input mode selection”
EXT1 = 0:
Set TVOUT output to TV mode.
EXT1 = 1:
Set TVOUT output to external input mode.
EXT2 = 0:
Set LSOUT output to TV mode.
EXT2 = 1:
Set LSOUT output to external input mode.
“TEST1”
TEST1 = 1
Return adjustment data with STATUS REGISTER as an adjustment mode.
In addition, outputs are as follows.
left channel: SAP BPF OUT
right channel: NR BPF OUT
“TEST-DA”
TEST-DA = 1
Used to adjust the D/A TEST and STVCO.
left channel: D/A output
right channel: STVCO oscillation frequency (4fH)
– 30 –
CXA1784AS
Decoder Output and Mode Control Table 1 (SAPC = 1)
Input signal mode
1)
MONO
1)
STEREO
MONO & SAP
STEREO & SAP
Mode detection
ST
SAP
NOISE
0
0
0
0
0
0
0
0
0
∗
0
1
∗
0
1
∗
0
1
∗
1
0
∗
1
0
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
∗
∗
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
∗
∗
0
0
1
1
∗
∗
0
0
1
1
Mode control
NRSW FOMO SAPC
∗
0
1
1
0
1
1
1
1
∗
0
1
1
0
1
1
1
1
0
0
1
0
1
1
0
0
1
0
1
1
1
0
1
1
1
1
1
0
1
1
1
1
0
0
1
0
1
1
1
0
1
1
1
1
1
0
1
1
1
1
0
0
1
0
1
1
1
0
1
1
1
1
1
0
1
1
1
1
dbx
input
MUTE
SAP
SAP
MUTE
(SAP)
(SAP)
L-R
MUTE
L-R
MUTE
SAP
SAP
(SAP)
(SAP)
MUTE
MUTE
SAP
SAP
(SAP)
(SAP)
L-R
MUTE
SAP
SAP
(SAP)
(SAP)
Output
Lch
Rch
L+R
L+R
SAP
SAP
L+R
SAP
L+R
L+R
(SAP)
(SAP)
L+R
(SAP)
L
R
L+R
L+R
L
R
L+R
L+R
SAP
SAP
L+R
SAP
(SAP)
(SAP)
L+R
(SAP)
L+R
L+R
L+R
L+R
SAP
SAP
L+R
SAP
(SAP)
(SAP)
L+R
(SAP)
L
R
L+R
L+R
SAP
SAP
L+R
SAP
(SAP)
(SAP)
L+R
(SAP)
Note
(SAP) : The SAPOUT output signal is soft muted (approximately -7 dB).
The signal is soft muted when NOISE = 1.
∗ : Don’t care.
1): SAP or NOISE discrimination may be made during MONO or STEREO input when the noise
is inputted in the weak electric field.
"NOISE" status rises earlier than "SAP" status when the amount of noise is increased to COMPIN.
– 31 –
CXA1784AS
Decoder Output and Mode Control Table 2 (SAPC = 0)
Input signal mode
1)
MONO
1)
STEREO
MONO & SAP
STEREO & SAP
Mode detection
ST
SAP
NOISE
∗
0
0
0
1
1
0
1
1
0
1
1
0
1
1
∗
1
0
∗
1
0
∗
1
0
∗
1
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Mode control
NRSW FOMO SAPC
∗
∗
0
0
0
0
0
1
0
1
0
0
1
1
0
0
0
0
0
1
0
1
0
0
1
1
0
0
0
0
0
1
0
1
0
0
1
1
0
0
0
0
0
1
0
1
0
0
1
1
0
0
0
0
0
1
0
1
0
0
1
1
0
0
0
0
0
1
0
1
0
0
1
1
0
0
0
0
0
1
0
1
0
0
1
1
0
dbx
input
MUTE
MUTE
MUTE
(SAP)
(SAP)
L-R
MUTE
L-R
MUTE
L-R
MUTE
(SAP)
(SAP)
MUTE
MUTE
SAP
SAP
MUTE
MUTE
(SAP)
(SAP)
L-R
MUTE
SAP
SAP
L-R
MUTE
(SAP)
(SAP)
Output
Lch
Rch
L+R
L+R
L+R
L+R
L+R
L+R
(SAP)
(SAP)
L+R
(SAP)
L
R
L+R
L+R
L
R
L+R
L+R
L
R
L+R
L+R
(SAP)
(SAP)
L+R
(SAP)
L+R
L+R
L+R
L+R
SAP
SAP
L+R
SAP
L+R
L+R
L+R
L+R
(SAP)
(SAP)
L+R
(SAP)
L
R
L+R
L+R
SAP
SAP
L+R
SAP
L
R
L+R
L+R
(SAP)
(SAP)
L+R
(SAP)
Note
(SAP) : The SAPOUT output signal is soft muted (approximately -7 dB).
The signal is soft muted when NOISE = 1.
∗ : Don’t care.
1): SAP or NOISE discrimination may be made during MONO or STEREO input when the noise
is inputted in the weak electric field.
"NOISE" status rises earlier than "SAP" status when the amount of noise is increased to COMPIN.
– 32 –
CXA1784AS
Mode Control Table 3
EXT1 EXT2
0
0
EXTFOMO
∗
1
0
0
1
1
EXT mode L channel
EXT mode R channel
TV mode L channel
TV mode R channel
1
0
1
1
1
EXT mode L channel
EXT mode L channel
TV mode L channel
TV mode R channel
0
1
0
1
1
TV mode L channel
TV mode R channel
EXT mode L channel
EXT mode R channel
0
1
1
1
1
TV mode L channel
TV mode R channel
EXT mode L channel
EXT mode L channel
1
1
0
1
1
EXT mode L channel
EXT mode R channel
EXT mode L channel
EXT mode R channel
1
1
1
1
1
EXT mode L channel
EXT mode L channel
EXT mode L channel
EXT mode L channel
Selected according to
Selected according to
the EXT1, EXT2,
the EXT1, EXT2,
∗
∗
M1
M2
1
1
TV mode L channel
TV mode R channel
TV mode L channel
TV mode R channel
∗
0
1
TV OUT-L
MUTE
TV OUT-R
MUTE
LS OUT-L
LS OUT-R
EXTFOMO conditions EXTFOMO conditions
Selected according to Selected according to
∗
∗
∗
1
0
the EXT1, EXT2,
the EXT1, EXT2,
MUTE
MUTE
EXTFOMO conditions EXTFOMO conditions
I2C BUS Signal
There are two I2C signals, SDA (Serial DATA) and SCL (Serial CLOCK) signals. SDA is a bidirectional
signal.
• Accordingly there are 3 values outputs, H, L and HIZ.
H
L
HIZ
L
• I2C transfer begins with Start Condition and ends with Stop Condition.
Start Condition S
Stop Condition P
SDA
SCL
– 33 –
CXA1784AS
• I2C data Write (Write from I2C controller to the IC)
L during Write
MSB
SDA
MSB
LSB
HIZ
SCL
1
2
3
4
5
6
7
8
HIZ
9
1
8
9
S
Address
MSB
ACK
Sub Address
ACK
LSB
HIZ
1
8
HIZ
9
DATA(n)
1
ACK
8
DATA(n+1)
ACK
HIZ
8
9
DATA(n+2)
HIZ
9
1
8
9
∗ Data can be transferred in 8-bit units to be
P
DATA
ACK
DATA
set as required.
ACK
Sub address is incremented automatically.
• I2C data Read (Read from the IC to I2C controller)
H during Read
HIZ
SDA
SCL
1
6
7
8
9
7
1
8
9
P
S
Address
ACK
DATA
ACK
• Read timing
MSB
IC output SDA
SCL
9
1
LSB
2
3
4
5
6
7
8
9
Read timing
ACK
DATA
∗ Data Read is performed during SCL rise.
– 34 –
ACK
CXA1784AS
Input level vs. Distortion characteristics 2 (Stereo)
Input level vs. Distortion characteristics 1 (MONO)
10
Input signal: Stereo L = -R
(dbx-TVNR ON), 1 kHz
0 dB = 100% modulation level
VCC = 9 V, 30 kHz using LPF, ST mode
Measurement point: TVOUT-L/R
Distortion (%)
Distortion (%)
1.0
Input signal: MONO (Pre-emphasis on), 1 kHz
0 dB = 100% modulation level
VCC = 9 V, 30 kHz using LPF
Measurement point: TVOUT-L/R
1.0
0.1
Standard level (100%)
–10
0
Input level (dB)
10
Standard level (100%)
–10
Input level vs. Distortion characteristics 3 (SAP)
Distortion (%)
10
Input signal: SAP (dbx-TVNR ON)
1 kHz, 0 dB = 100% modulation
level
VCC = 9 V, 30 kHz using LPF, SAP mode
Measurement point: TVOUT-L/R
1.0
Standard level (100%)
–10
0
Input level (dB)
10
– 35 –
0
Input level (dB)
10
CXA1784AS
Stereo LPF frequency characteristics
10
Gain (dB)
5
0
–5
–10
0
20
40
60
80
100
Frequency (kHz)
Main LPF and Sub LPF frequency characteristics
Gain (FC main and FC sub) (dB)
30
20
10
0
–10
–20
–30
–40
–50
1
2
5
7
10
20
50 70 100
Frequency (kHz)
SAP frequency characteristics and group delay
100
20
90
5fH
70
60
50
0
40
30
–10
20
Group delay
3.8fH
–20
20
40
60
80
Frequency (kHz)
– 36 –
6.2fH
100
10
0
120
Group delay (µs)
10
Gain (dB)
80
Gain
CXA1784AS
BASS - TREBLE
characteristics
BASS. MAX
TREBLE. MAX
BASS. MIN
TREBLE. MIN
+12
+4
0
-4
-8
-12
2
0
100
1k
Frequency (Hz)
10
k
Input:
AUXIN (Pins 37 and 38) 245 mVrms
Output: LSOUT (Pins 4, 5 and 6)
Volume
characteristics
0
-20
LSOUT output level (dB)
Boost amount (dB)
+8
-40
-60
Input:
AUXIN (Pins 37 and 38)
1 kHz,490mVrms
Output: LSOUT (Pins 4, 5 and 6)
-80
-100
0
F
1F
2
F
Control data VOL-L, VOL-R, VOL-SURR
– 37 –
3
F
20
k
CXA1784AS
Package Outline
Unit: mm
+ 0.1
– 0.05
42PIN SDIP (PLASTIC) 600mil
0.25
+ 0.4
37.8 – 0.1
42
+ 0.3
13.0 – 0.1
15.24 ± 0.25
22
0° to 15°
21
1
+ 0.4
4.6 – 0.1
3.0 MIN
0.5 MIN
1.778 ± 0.25
0.5 ± 0.1
0.9 ± 0.15
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
SONY CODE
SDIP-42P-02
LEAD TREATMENT
SOLDER PLATING
EIAJ CODE
SDIP042-P-0600-A
LEAD MATERIAL
COPPER / 42 ALLOY
PACKAGE WEIGHT
4.4g
JEDEC CODE
– 38 –