SONY CXD2510Q

CXD2510Q
CD Digital Signal Processor
Description
The CXD2510Q is a digital signal processor LSI for
CD players and is equipped with the following functions.
• Wide frame jitter margin (±28 frames) due to a builtin 32K RAM
• Bit clock, which strobes the EFM signal, is
generated by the digital PLL
• EFM data demodulation
• Enhanced EFM frame sync signal protection
• Refined super strategy-based powerful error correction
C1: double correction, C2: quadruple correction
• Quadruple-speed, double-speed and variable pitch
playback
• Noise reduction during track jumps
• Auto zero-cross mute
• Subcode demodulation and Sub Q data error
correction
• Digital spindle servo (built-in oversampling filter)
• 16-bit traverse counter
• Asymmetry compensation circuit
• Serial bus-based CPU interface
• Error correction monitor signals are output from a
new CPU interface.
• Servo auto sequencer
• Fine search which performs high-precision track
jumps
• Digital audio interface output
• Digital level meter, peak meter
• Bilingual compatible
Features
• All digital signals processed with a single chip
during playback
• High-integrated mounting possible due to a built-in
RAM
Structure
Silicon gate CMOS IC
Absolute Maximum Ratings
VDD
• Supply voltage
–0.3 to +7.0 V
• Input voltage
VI
–0.3 to +7.0 V
(VSS – 0.3V to VDD + 0.3V)
• Output voltage
VO
–0.3 to +7.0 V
• Storage temperature Tstg
–40 to +125 °C
• Supply voltage difference
Vss – AVss –0.3 to +0.3 V
VDD – AVDD –0.3 to +0.3 V
-L01
80 pin QFP (Plastic)
-L051
Recommended Operating Conditions
4.50 to 5.50
V
• Supply voltage
VDD∗
• Operating temperature Topr
–20 to +75
°C
∗ The VDD (min.) for the CXD2510Q varies according
to the playback speed and built-in VCO selection.
The VDD (min.) is 4.50 V when high speed VCO
and quadruple-speed playback are selected
(variable pitch off). The VDD (min.) for the
CXD2510Q under various conditions are as shown
in the following table.
VDD (min.) [V]
Playback
speed
VCO high-speed VCO normal-speed
×4
4.50
—
× 2∗1
4.00
—
×2
3.40
4.00
×1
3.40
3.40
× 1∗2
3.40
3.40
Dashes indicate that there is no assurance of the
processor operating. All values are for variable pitch off.
∗1 When the internal operation of the LSI is set to
normal-speed playback and the operating clock
of the signal processor is doubled, double-speed
playback results.
∗2 When the internal operation of the LSI is set to
double-speed mode and the crystal oscillating
frequency is halved in low power consumption
mode, normal-speed playback results.
Input/output Capacitances
• Input capacitance
CI
• Output capacitance CO
Note) Measurement conditions
12 (max.)
pF
12 (max.)
pF
for high impedance
VDD = VI = 0V
fM = 1MHz
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E94412A11
CXD2510Q
17 16
54 55
56 53
VPCO
VCKI
XTSL
XTAO
XTAI
FSTT
Block Diagram
23 AVDD
FSOF 57
21 AVSS
Clock
generator
C16M 58
33 VDD
32K RAM
PDO 11
VCOO
8
73 VDD
Digital PLL
vari-pitch
double speed
PCO 20
EFM
demodulator
Address
generator
Priority
encoder
Serial/parallel
processor
9
Register
VCOI
FILI 19
8
FILO 18
Sync
protector
CLTV 22
D/A
data processor
RF 24
ASYI 26
∗
12
VSS
52
VSS
30
PSSL
DA01 to 16
16
68 MUTE
MIX
ASYO 27
ASYE 28
Peak detector
Timing
generator 1
WFCK 62
SCOR 63
Digital out
Subcode
P-W
processor
EXCK 65
SBSO 64
EMPH 61
SQSO 66
Noise
shaper
TEST 10
DATO
79 CLKO
78 XLTO
4
∗ Asymmetry
FOK
CNIN
MIRR
SEIN
1
correction.
DA09
DA08
DA07
DA06
DA05
DA04
DA03
SENS
75 69 80 76
WDCK
DA02
DA01
APTL
LRCK
APTR
APTR
VSS
XTAI
XTAO
XTSL
APTL
LOCK
FSTT
C16M
MD2
DOUT
Pin Configuration
50 51 32 31
6
XRST
SBSO
BIAS
TEST0
70
FSOF
13
25
EMPH
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
DA11
SQCK
67
38
DA12
MUTE
68
37
DA13
SENS
69
36
DA14
XRST
70
35
DA15
DATA
71
34
DA16
XLAT
72
33
VDD
VDD
73
32
LRCK
CLOK
74
31
WDCK
SEIN
75
30
PSSL
CNIN
76
29
NC
DATO
77
28
ASYE
XLTO
78
27
ASYO
CLKO
79
26
ASYI
MIRR
80
25
BIAS
–2–
RF
AVDD
CLTV
AVSS
PCO
FILI
FILO
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
VCKI
8
VPCO
7
NC
6
NC
5
VSS
4
TEST0
3
PDO
2
TEST
1
VCOI
39
VCOO
DA10
66
NC
40
SQSO
LOCK
EXCK
65
MDS
NC
77
Servo
auto
sequencer
Timing
generator 2
18-times
ever sampling
filter
WFCK
5
MDP
4
MDS
72 XLAT
MON
MDP
74 CLOK
CLV
processor
SCOR
2
FSW
3
FSW
71 DATA
CPU interface
FOK
MON
Error corrector
Subcode
Q
processor
SQCK 67
60 DOUT
59 MD2
CXD2510Q
Pin Description
Pin
No.
Symbol
I/O
Description
1
FOK
I
2
FSW
O
Z, 0
Spindle motor output filter switching output.
3
MON
O
1, 0
Spindle motor on/off control output.
4
MDP
O
1, Z, 0
Spindle motor servo control.
5
MDS
O
1, Z, 0
Spindle motor servo control.
6
LOCK
O
1, 0
7
NC
8
VCOO
O
9
VCOI
I
Analog EFM PLL oscillation circuit input. fLOCK = 8.6436MHz.
10
TEST
I
TEST pin. Normally GND.
11
PDO
O
12
Vss
13
TEST0
—
14
NC
—
15
NC
—
16
VPCO
O
17
VCKI
I
18
FILO
O
19
FILI
I
20
PCO
O
21
AVss
22
CLTV
23
AVDD
24
RF
I
EFM signal input.
25
BIAS
I
Constant current input of the asymmetry circuit.
26
ASYI
I
Asymmetry comparator voltage input.
27
ASYO
O
28
ASYE
I
29
NC
30
PSSL
I
31
WDCK
O
1, 0
D/A interface for 48-bit slot. Word clock f = 2Fs.
32
LRCK
O
1, 0
D/A interface for 48-bit slot. LR clock f = Fs.
33
VDD
Focus OK input. Used for SENS output and the servo auto sequencer.
GFS is sampled at 460Hz; when GFS is high, this pin outputs a high signal.
If GFS is low eight consecutive samples, this pin outputs low.
—
1, 0
1, Z, 0
Analog EFM PLL oscillation circuit output.
Analog EFM PLL charge pump output.
GND
1, Z, 0
TEST output pin. Normally open.
Variable pitch PLL charge pump output.
Variable pitch clock input from the external VCO. fc center = 16.9344MHz.
Analog
Master PLL filter output.
Master PLL filter input.
1, Z, 0
Master PLL charge pump output.
Analog GND.
I
Master VCO control voltage input.
Analog power supply (5V).
1, 0
EFM full-swing output (low = Vss, high = VDD).
Low: asymmetry circuit off; high: asymmetry circuit on
—
Audio data output mode switching input. Low: serial output; high: parallel output.
Power supply (5V).
–3–
CXD2510Q
Pin
No.
Symbol
34
DA16
O
1, 0
DA16 (MSB) output when PSSL = 1.
48-bit slot serial data (two's complement, MSB first) when PSSL = 0.
35
DA15
O
1, 0
DA15 output when PSSL = 1.
36
DA14
O
1, 0
DA14 output when PSSL = 1.
64-bit slot serial data (two's complement, LSB first) when PSSL = 0.
37
DA13
O
1, 0
DA13 output when PSSL = 1.
64-bit slot bit clock when PSSL = 0.
38
DA12
O
1, 0
DA12 output when PSSL = 1.
64-bit slot LR clock when PSSL = 0.
39
DA11
O
1, 0
DA11 output when PSSL = 1.
GTOP output when PSSL = 0.
40
DA10
O
1, 0
DA10 output when PSSL = 1.
XUGF output when PSSL = 0.
41
DA09
O
1, 0
DA09 output when PSSL = 1.
XPLCK output when PSSL = 0.
42
DA08
O
1, 0
DA08 output when PSSL = 1.
GFS output when PSSL = 0.
43
DA07
O
1, 0
DA07 output when PSSL = 1.
RFCK output when PSSL = 0.
44
DA06
O
1, 0
DA06 output when PSSL = 1.
C2PO output when PSSL = 0.
45
DA05
O
1, 0
DA05 output when PSSL = 1.
XRAOF output when PSSL = 0.
46
DA04
O
1, 0
DA04 output when PSSL = 1.
MNT3 output when PSSL = 0.
47
DA03
O
1, 0
DA03 output when PSSL = 1.
MNT2 output when PSSL = 0.
48
DA02
O
1, 0
DA02 output when PSSL = 1.
MNT1 output when PSSL = 0.
49
DA01
O
1, 0
DA01 output when PSSL = 1.
MNT0 output when PSSL = 0.
50
APTR
O
1, 0
Aperture compensation control output.
This pin outputs a high signal when the right channel is used.
51
APTL
O
1, 0
Aperture compensation control output.
This pin outputs a high signal when the left channel is used.
52
Vss
53
XTAI
I
54
XTAO
O
55
XTSL
I
56
FSTT
O
1, 0
2/3 frequency divider output for Pins 53 and 54.
This pin does not change with the variable pitch.
57
FSOF
O
1, 0
1/4 frequency divider output for Pins 53 and 54.
This pin does not change with the variable pitch.
58
C16M
O
1, 0
16.9344MHz output. This pin changes simultaneously with the variable pitch.
59
MD2
I
60
DOUT
O
1, 0
Digital-out output.
61
EMPH
O
1, 0
Outputs a high signal when the playback disc has emphasis, and a low signal
when there is no emphasis.
62
WFCK
O
1, 0
WFCK (write frame clock) output.
63
SCOR
O
1, 0
Outputs a high signal when either subcode sync S0 or S1 is detected.
64
SBSO
O
1, 0
Sub P to W serial output.
65
EXCK
I
I/O
Description
48-bit slot bit clock when PSSL = 0.
GND
16.9344MHz crystal oscillation circuit input. Also the 33.8688MHz input.
1, 0
16.9344MHz crystal oscillation circuit output.
Crystal selector input. The crystal is low for 16.9344MHz, and high for 33.8688MHz.
Digital-out on/off control. High: on; low: off
SBSO readout clock input.
–4–
CXD2510Q
Pin
No.
Symbol
66
SQSO
O
67
SQCK
I
SQSO readout clock input.
68
MUTE
I
High: mute; low: release
69
SENS
—
70
XRST
I
System reset. Reset when low.
71
DATA
I
Serial data input from CPU.
72
XLAT
I
Latch input from CPU. Serial data is latched at the falling edge.
73
VDD
74
CLOK
I
Serial data transfer clock input from CPU.
75
SEIN
I
SENS input from SSP.
76
CNIN
I
Track jump count signal input.
77
DATO
O
1, 0
Serial data output to SSP.
78
XLTO
O
1, 0
Serial data latch output to SSP. Latched at the falling edge.
79
CLKO
O
1, 0
Serial data transfer clock output to SSP.
80
MIRR
I
I/O
1, 0
1, Z, 0
Description
Sub Q 80-bit and PCM peak and level data 16-bit output.
SENS output to CPU.
Power supply (5V).
Mirror signal input.
Notes)
• The 64-bit slot is an LSB first, two's complement output, and the 48-bit slot is an MSB first, two's complement
output.
• GTOP is used to monitor the frame sync protection status. (High: sync protection window open.)
• XUGF is the negative pulse for the frame sync obtained from the EFM signal. It is the signal before sync
protection.
• XPLCK is the inverse of the EFM PLL clock. The PLL is designed so that the falling edge and the EFM signal
transition point coincide.
• GFS goes high when the frame sync and the insertion protection timing match.
• RFCK is derived from the crystal accuracy, and has a cycle of 136µ.
• C2PO represents the data error status.
• XRAOF is generated when the 32K RAM exceeds the ±28F jitter margin.
–5–
CXD2510Q
Electrical Characteristics
DC Characteristics
(VDD = AVDD = 5.0V ± 10%, Vss = AVss = 0V, Topr = –20 to +75°C)
Item
Conditions
Input
voltage (1)
High level input voltage
VIH (1)
Low level input voltage
VIL (1)
Input
voltage (2)
High level input voltage
VIH (2)
Low level input voltage
VIL (2)
Input voltage
VIN (3)
Output
voltage (1)
High level output voltage
VOH (1) IOH = –1mA
Low level output voltage
VOL (1) IOL = 1mA
Output
voltage (2)
High level output voltage
VOH (2) IOH = –1mA
Low level output voltage
Input
voltage (3)
Output
voltage (3)
Output
voltage (4)
Min.
Typ.
Max.
0.7VDD
V
0.3VDD
Schmitt input
Unit
0.8VDD
Applicable
pins
∗1
V
V
∗2
0.2VDD
V
Vss
VDD
V
∗3
VDD – 0.5
VDD
V
∗4
0
0.4
V
VDD – 0.5
VDD
V
VOL (2) IOL = 2mA
0
0.4
V
Low level output voltage
VOL (3) IOL = 2mA
0
0.4
V
∗6
High level output voltage
VOH (4) IOH = –0.28mA VDD – 0.5
VDD
V
∗7
Low level output voltage
VOL (4) IOL = 0.36mA
0
0.4
V
Analog input
∗5
Input leak current
ILI
VI = 0 to 5.50V
–5
5
µA
∗1, 2, 3
Tri-state pin output
leak current
ILO
VO = 0 to 5.50V
–5
5
µA
∗8
Applicable pins
∗1 XTSL, DATA, XLAT, MD2, PSSL
∗2 CLOK, XRST, EXCK, SQCK, MUTE, FOK, SEIN, CNIN, MIRR, VCKI, ASYE
∗3 CLTV, FILI, RF
∗4 MDP, PDO, PCO, VPCO
∗5 ASYO, DOUT, FSTT, FSOF, C16M, SBSO, SQSO, SCOR, EMPH, MON, LOCK, WDCK, DATO, CLKO,
XLTO, SENS, MDS, DA01 to DA16, APTR, APTL, LRCK, WFCK
∗6 FSW
∗7 FILO
∗8 SENS, MDS, MDP, FSW, PDO, PCO, VPCO
–6–
CXD2510Q
AC Characteristics
1. XTAI pin, VCOI pin
(1) When using self-oscillation
(Topr = –20 to +75°C, VDD = AVDD = 5.0V ± 10%)
Item
Symbol
Oscillation
frequency
Min.
fMAX
Typ.
7
Max.
Unit
34
MHz
(2) When inputting pulses to XTAI and VCOI
(Topr = –20 to +75°C, VDD = AVDD = 5.0V ± 10%)
Item
Symbol
Min.
Typ.
Max.
Unit
High level pulse
width
tWHX
13
500
ns
Low level pulse
width
tWLX
13
500
ns
Pulse cycle
tCX
26
1,000
ns
Input high level
VIHX
VDD – 1.0
Input low level
VILX
0.8
V
Rise time,
fall time
tR, tF
10
ns
V
tCX
tWLX
tWHX
VIHX
VIHX × 0.9
VDD/2
XTAI
VIHX × 0.1
VILX
tR
tF
(3) When inputting sine waves to XTAI and VCOI pins via a capacitor
(Topr = –20 to +75°C, VDD = AVDD = 5.0V ± 10%)
Item
Input amplitude
Symbol
Min.
VI
2.0
Typ.
Max.
Unit
VDD+0.3
Vp-p
–7–
CXD2510Q
2. CLOK, DATA, XLAT, CNIN, SQCK EXCK pins
(VDD = AVDD = 5.0V ± 10%, VSS = AVSS = 0V, Topr = –20 to +75°C)
Item
Symbol
Clock frequency
fCK
Clock pulse width
Latch pulse width
tWCK
tSU
tH
tD
tWL
EXCK SQCK frequency
fT
Setup time
Hold time
Delay time
Min.
Typ.
Max.
Unit
0.65
MHz
750
ns
300
ns
300
ns
300
ns
750
ns
0.65
EXCK SQCK pulse width tWT
CNIN freqency ∗
fT
CNIN pulse width ∗
tWT
750
MHz
ns
65
7.5
kHz
µs
∗ When $44 and $45 are excuted.
1/fCK
tWCK
tWCK
CLOK
DATA
XLAT
tSU
tH
EXCK
CNIN
SQCK
tD
tWT
tWL
tWT
1/fT
SBSO
SQSO
tSU
tH
Description of Functions
§1. CPU Interface and Instructions
• CPU interface
This interface uses DATA, CLOK, and XLAT to set the modes.
The interface timing chart is shown below.
750ns or more
CLOK
DATA
D1
D2
Data
D3
D0
D1
D2
D3
750ns or more
Address
XLAT
Registers 4 to E
Valid
300ns max
• Information on each address and the data is provided in Table 1-1.
• The internal registers are initialized by a reset when XRST = 0; the initialization data is shown in Table 1-2.
–8–
0
Auto sequence (N)
track jump count setting
MODE specification
7
8
–9–
1
1
Audio CTRL
Traverse monitor
counter setting
Spindle servo
coefficient setting
CLV CTRL
CLV mode
A
B
C
D
E
1
1
1
Function specification
9
1
1
0
0
Sled_kick, brake (D)
Kick (F)
Brake (B)
Blind (A, E), Overflow (C, G)
6
5
0
4
Auto sequence
D3
Command
Register
name
Command Table
1
1
1
0
0
0
0
1
1
1
1
D2
1
0
0
1
1
0
0
1
1
0
0
D1
Address
0
1
0
1
0
1
0
1
0
1
0
D0
D2
D1
D0
D3
D2
D1
Data 2
D0
D3
TR2
TR1
TR0
—
KF2
—
DOUT D.out WSEL
Mute Mute-F
0
—
Table 1-1.
CM3 CM2 CM1 CM0
TP
—
TB
Gain
CLVS
DCLV
PWM MD
0
Gain Gain Gain Gain
MDP1 MDP0 MDS1 MDS0
—
—
Gain
DCLV0
—
—
0
32,76816,384 8,192 4,096 2,048 1,024 512
Vari Vari Mute ATT
PCT1 PCT2
Up Down
BiliGL
FLFC
MAIN SUB
VCO
ASHS SOCT
SEL
DCLV DSPB ASEQ DPLL BiliGL
ON-OFF ON-OFF ON-OFF ON-OFF
CDROM
—
—
—
0
256
0
0
0
256
KF1 KF0
—
32,76816,384 8,192 4,096 2,048 1,024 512
SD3 SD2 SD1 SD0 KF3
TR3
—
—
—
128
—
—
—
128
—
—
AS3 AS2 AS1 AS0 MT3 MT2 MT1 MT0 LSSL
D3
Data 1
—
—
—
64
—
—
—
64
—
—
0
D2
—
—
—
32
—
—
—
32
—
—
0
D1
Data 3
—
—
—
16
—
—
—
16
—
—
0
D0
—
—
—
8
—
—
—
8
—
—
—
D3
—
—
—
4
—
—
—
4
—
—
—
D2
—
—
—
2
—
—
—
2
—
—
—
D1
Data 4
—
—
—
1
—
—
—
1
—
—
—
D0
CXD2510Q
1
1
1
1
1
1
Audio CTRL
Traverse monitor
counter setting
Servo
coefficient setting
CLV CTRL
CLV mode
A
B
C
D
E
1
MODE specification
8
Function specification
0
Auto sequence (N)
track jump count setting
7
9
0
0
Sled_kick, brake (D)
Kick (F)
Brake (B)
Blind (A, E), Overflow (C, G)
6
5
0
4
Auto sequence
D3
Command
Register
name
Reset Initialization
– 10 –
1
1
1
0
0
0
0
1
1
1
1
D2
1
0
0
1
1
0
0
1
1
0
0
D1
Address
0
1
0
1
0
1
0
1
0
1
0
D0
0
0
0
0
0
1
0
0
0
0
0
D3
0
0
1
0
0
0
0
0
1
1
0
D2
0
0
1
0
1
0
0
0
1
0
0
0
0
0
0
1
1
0
0
1
1
0
D0
—
—
0
0
0
0
0
0
0
—
0
D3
Table 1-2.
D1
Data 1
—
—
0
0
0
0
0
0
0
—
0
D2
—
—
0
0
0
0
0
0
0
—
0
D1
Data 2
—
—
0
1
0
0
0
1
0
—
0
D0
—
—
—
—
—
—
0
—
—
0
—
—
—
—
0
—
—
—
D2
0
—
—
0
D3
—
—
—
0
—
—
—
0
—
—
—
D1
Data 3
—
—
—
0
—
—
—
0
—
—
—
D0
—
—
—
0
—
—
—
0
—
—
—
D3
—
—
—
0
—
—
—
0
—
—
—
D2
—
—
—
0
—
—
—
0
—
—
—
D1
Data 4
—
—
—
0
—
—
—
0
—
—
—
D0
CXD2510Q
CXD2510Q
The meaning of the data for each address is explained below.
$4X commands
Register name
4
AS3
Data 1
Data 2
Data 3
Command
MAX timer value
Timer range
AS2
AS1
Command
AS0
MT3
MT2
MT1
MT0
LSSL
0
0
AS3
AS2
AS1
AS0
Cancel
0
0
0
0
FineSearch
0
1
0
RXF
Focus-On
0
1
1
1
1 TrackJump
1
0
0
RXF
10 TrackJump
1
0
1
RXF
2N TrackJump
1
1
0
RXF
0
RXF = 0 Forward
RXF = 1 Reverse
• When the FOCUS-ON command ($47) is canceled, $02 is sent and the auto sequence is interrupted.
• When the TRACK JUMP commands ($44 to $45, $48 to $4D) are canceled, $25 is sent and the auto
sequence is interrupted.
Max. timer value
Timer range
MT3
MT2
MT1
MT0
LSSL
0
0
0
23.2ms
11.6ms
5.8ms
2.9ms
0
0
0
0
1.49s
0.74s
0.37s
0.18s
1
0
0
0
• To invalidate the MAX timer, set the MAX timer value to 0.
$5X commands
Timer
TR3
TR2
TR1
TR0
Blind (A, E), Overflow (C, G)
0.18ms
0.09ms
0.045ms
0.022ms
Brake (B)
0.36ms
0.18ms
0.09ms
0.045ms
$6X commands
Register name
6
SD3
Data 1
Data 2
KICK (D)
KICK (F)
SD2
SD1
Timer
SD0
KF3
KF2
KF1
KF0
SD3
SD2
SD1
SD0
When executing KICK (D) $44 or $45
23.2ms
11.6ms
5.8ms
2.9ms
When executing KICK (D) $4C or $4D
11.6ms
5.8ms
2.9ms
1.45ms
Timer
KF3
KF2
KF1
KF0
0.72ms
0.36ms
0.18ms
0.09ms
KICK (F)
– 11 –
CXD2510Q
$7X commands
Auto sequence track jump count setting
Data 1
Command
Data 2
Data 3
Data 4
D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0
Auto sequencer
track jump count setting
215 214 213 212 211 210
29
28
27
26
25
24
23
22
21
20
This command is used to set N when a 2N track jump is executed, and the jump count setting when fine
search is executed for auto sequence.
• The maximum track count is 65,535, but note that with 2N track jumps the maximum track jump count is
determined by the mechanical limitations of the optical system.
• When N is from 0 to 15, the number of 2N track jumps is counted according to the signals input from the
CNIN pin. When N is 16 or over, it is counted according to the signals input from the MIRR pin.
$8X commands
Data 1
Command
MODE
specification
Data 2
D3
D2
D1
CDROM
DOUT
Mute
D.out
Mute-F
D0
D3
WSEL VCO SEL
D2
D1
D0
ASHS
SOCT
0
Command bit
C2PO timing
CDROM = 1
See the Timing
Chart 1-3
CDROM mode; average value interpolation and pre-value
hold are not performed.
CDROM = 0
See the Timing
Chart 1-3
Audio mode; average value interpolation and pre-value
hold are performed.
Command bit
Processing
Processing
DOUT Mute = 1
When Digital out is on (MD2 pin = 1), DOUT output is muted.
DOUT Mute = 0
When Digital out is on, DOUT output is not muted.
Command bit
Processing
D. out Mute F = 1
When Digital out is on (MD2 pin = 1), DA output is muted.
D. out Mute F = 0
DA output mute is not affected when Digital out is either on or off.
– 12 –
CXD2510Q
MD2
Other mute conditions∗
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
DOUT Mute D.out Mute F DOUT output
DA output
0dB
off
–∞dB
0dB
0dB
–∞dB
0dB
–∞dB
–∞dB
∗ See mute conditions (1), (2), and (4) to (6) under $AX commands for other mute conditions.
Command bit
Sync protection window width
Application
WSEL = 1
±26 channel clock∗
Anti-rolling is enhanced.
WSEL = 0
±6 channel clock
Sync window protection is enhanced.
∗ In normal-speed playback, channel clock = 4.3218MHz.
Command bit
Processing
Use
VCOSEL = 0
The built-in VCO is set to
normal-speed.
Used for normal-speed and double-speed
(double correction) playback.
VCOSEL = 1
The built-in VCO is set to
high-speed.
Used for quadruple-speed and double-speed
(quadruple correction) playback.
Command bit
Function
Use
ASHS = 0
The command transfer rate to SSP is set Used for normal-speed and double-speed
to normal-speed.
(double correction) playback.
ASHS = 1
The command transfer rate to SSP is set Used for quadruple-speed and double-speed
to half-speed.
(quadruple correction) playback.
Command bit
Function
SOCT = 0
Sub Q is output from the SQSO pin.
SOCT = 1
Each output signal is output from the SQSO pin. Input the readout clock to SQCK.
(See the Timing Chart 2-4.)
– 13 –
CXD2510Q
$9X commands
Command
Data 1
D3
D2
Data 2
D1
Function
DCLV
DSPB
A.SEQ
D.PLL
specifications ON-OFF ON-OFF ON-OFF ON-OFF
Command bit
DCLV on/off = 0
DCLV on/off = 1
(FSW, MON not
required)
D3
D2
D1
D0
BiliGL
MAIN
BiliGL
SUB
FLFC
0
D0
CLV mode
Contents
During
CLVS mode
FSW = low, MON = high, MDS = Z; MDP = servo control signal,
carrier frequency of 230Hz at TB = 0, and 460Hz at TB = 1.
During
CLVP mode
FSW = Z, MON = high; MDS = speed control signal, carrier frequency of
7.35kHz; MDP = phase control signal, carrier frequency of 1.8kHz.
During CLVS
and CLVP modes
MDS = PWM polarity signal, carrier frequency of
When DCLV
132kHz.
PWM and MD = 1 MDP = PWM absolute value output (binary),
carrier frequency of 132kHz.
MDS = Z
When DCLV
MDP = ternary PWM output, carrier frequency
PWM and MD = 0
of 132kHz.
When DCLV on/off = 1 for the Digital CLV servo, the sampling frequency of the internal digital filter switches
simultaneously with the CLVP/CLVS switching.
Therefore, the cut-off frequency for the CLVS is fc = 70Hz when TB = 0, and fc = 140Hz when TB = 1.
Command bit
Processing
DSPB = 0
Normal-speed playback, C2 error correction quadruple correction, variable pitch possible.
DSPB = 1
Double-speed playback, C2 error correction double correction, variable pitch prohibited.
FLFC is normally 0.
– 14 –
CXD2510Q
SENS output
Microcomputer serial register
value (latching not required)
ASEQ = 0
ASEQ = 1
$0X
Z
SEIN (FZC)
$1X
Z
SEIN (A.S)
$2X
Z
SEIN (T.Z.C)
$3X
Z
SEIN (SSTOP)
$4X
Z
XBUSY
$5X
Z
FOK
$6X
Z
SEIN (Z)
$AX
GFS
GFS
$BX
COMP
COMP
$CX
COUT
COUT
$EX
OV64
OV64
$7X, 8X, 9X, DX, FX
Z
0
Description of SENS signals
SENS output
Meaning
Z
The SENS pin is high impedance.
XBUSY
Low while the auto sequencer is in operation, high when operation terminates.
FOK
Outputs the same signal as the FOK pin.
High for "focus OK".
GFS
High when the played back frame sync is obtained with the correct timing.
COMP
Measures the number of tracks set with Reg B. High when Reg B is latched, low when the
initial Reg B number is input by CNIN.
COUT
Measures the number of tracks set with Reg B. High when Reg B is latched, toggles each time
the Reg B number is input by CNIN. While $44 and $45 are being executed, toggles with each
CNIN 8-count instead of the Reg B number.
OV64
Low when the EFM signal, after passing through the sync detection filter, is lengthened by
64 channel clock pulses or more.
Command bit
Meaning
DPLL = 0∗
RFPLL is analog. PDO, VCOI and VCOO are used.
DPLL = 1
RFPLL is digital. PDO is impedance.
∗ External parts for Pins 18 to 20 are required even when analog PLL is selected.
Command bit
BiliGL MAIN = 0
BiliGL MAIN = 1
BiliGL SUB = 0
STEREO
MAIN
BiliGL SUB = 1
SUB
Mute
Definition of bilingual capable MAIN, SUB and STEREO:
The left channel input is output to the left and right channels for MAIN.
The right channel input is output to the left and right channels for SUB.
The left and right channel inputs are output to the left and right channels for STEREO.
– 15 –
CXD2510Q
$AX commands
Data 1
Command
Audio CTRL
Data 2
D3
D2
D1
D0
D3
D2
D1
D0
Vari
Up
Vari
Down
Mute
ATT
PCT1
PCT2
0
0
XTal 0%
VCO 0% +0.1% +0.2% +0.3% +0.2% +0.1% +0%
Vari Up
Vari Down
Pitch
Command bit
Command bit
Meaning
Mute = 0
Mute off if other mute
conditions are not set.
Mute = 1
Mute on.
Peak register reset.
–0.1% –0.2%
XTal 0%
Meaning
ATT = 0
Attenuation off.
ATT = 1
–12dB
Mute conditions
(1) When register A mute = 1.
(2) When MUTE pin = 1.
(3) When register 8 D.out mute = 1 and the Digital out is on (MD2 pin = 1).
(4) When GFS stays low for over 35ms (at normal speed).
(5) When register 9 BiliGL MAIN = Sub = 1.
(6) When register A PCT1 = 1 and PCT2 = 0.
(1) to (4) perform zero-cross muting with a 1ms time limit.
Command bit
Meaning
PCM Gain
ECC correction ability
Normal mode
× 0dB
C1: double; C2: quadruple
1
Level meter mode
× 0dB
C1: double; C2: quadruple
1
0
Peak meter mode
Mute
C1: double; C2: double
1
1
Normal mode
× 0dB
C1: double; C2: double
PCT1
PCT2
0
0
0
Description of level meter mode (see the Timing Chart 1-4.)
• When this LSI is set to this mode, it can possess digital level meter functions.
• When the 96-bit clock is input to SQCK, 96 bits of data are output to SQSO.
The initial 80 bits of data are Sub Q data (see §2. Subcode Interface). The last 16 bits are LSB first 15-bit
PCM data (absolute values). The final bit is PCM data. However, it is high when generated by the left
channel and low when generated by the right channel.
• PCM data is reset and the L/R flag is reversed after one readout.
The maximum value for this status is then measured until the next readout.
– 16 –
CXD2510Q
Description of peak meter mode (see the Timing Chart 1-5.)
• When the LSI is set to this mode, the maximum PCM data value is detected regardless of if it comes from the
left or right channel.
The 96-bit clock must be input to SQCK to read out this data.
• When the 96-bit clock is input, 96 bits of data are output to SQSO and the LSI internal register is reset.
In other words, the PCM maximum value detection register is not reset by the readout.
• To reset the PCM maximum value register, set PCT1 = PCT2 = 0 or set the $AX mute.
• The Sub Q absolute time is automatically controlled in this mode.
In other words, after the maximum value is generated, the absolute time for CRC to become OK is retained in
the memory. Relative time operates as normal.
• The final bit (L/R flag) of the 96-bit data is normally 0.
• The pre-value hold and average value interpolation data are fixed to level (–∞) for this mode.
$BX commands
This command sets the traverse monitor count.
Data 1
Command
Data 2
Data 3
Data 4
D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0
Traverse monitor count
setting
215 214 213 212 211 210
29
28
27
26
25
24
23
22
21
20
• When the set number of tracks are counted during fine search, the sled control for the traverse cycle control
goes off.
• The traverse monitor count is set when the traverse status is monitored by the SENS output COMP and
COUT.
$CX commands
Data 1
Command
D3
D1
D2
Data 2
D0
Servo coefficient Gain Gain Gain Gain
MDP1 MDP0 MDS1 MDS0
setting
D3
D2
D1
D0
0
Gain
DCLV0
0
0
Gain
CLVS
CLV CTRL ($DX)
Explanation
Valid only when DCLV = 1.
Valid when DCLV = 1 or 0.
The spindle servo gain is externally set when DCLV = 1.
• CLVS mode gain setting: GCLVS
Gain
MDS1
Gain
MDS0
Gain
CLVS
GCLVS
0
0
0
–12dB
0
0
1
–6dB
0
1
0
–6dB
0
1
1
0dB
1
0
0
0dB
1
0
1
+6dB
Note) When DCLV = 0, the CLVS gain is as follows.
When Gain CLVS = 0, GCLVS = –12dB.
When Gain CLVS = 1, GCLVS = 0dB.
– 17 –
CXD2510Q
• CLVP mode gain setting: GMDP: GMDS
Gain
MDP1
Gain
MDP0
GMDP
Gain
MDS1
Gain
MDS0
GMDS
0
0
–6dB
0
0
–6dB
0
1
0dB
0
1
0dB
1
0
+6dB
1
0
+6dB
• DCLV overall gain setting: GDCLV
Gain
DCLV0
GDCLV
0
0dB
1
+6dB
$DX commands
Command
D3
D2
D1
D0
CLV CTRL
DCLV
PWM MD
TB
TP
Gain
CLVS
See the $CX commands
Command bit
Explanation (See the Timing Chart 1-6.)
DCLV PWM MD = 1
Digital CLV PWM mode specified. Both MDS and MDP are used.
DCLV PWM MD = 0
Digital CLV PWM mode specified. Ternary MDP values are output.
Command bit
Explanation
TB = 0
Bottom hold in CLVS and CLVH modes at a cycle of RFCK/32.
TB = 1
Bottom hold in CLVS and CLVH modes at a cycle of RFCK/16.
TP = 0
Peak hold in CLVS mode at a cycle of RFCK/4.
TP = 1
Peak hold in CLVS mode at a cycle of RFCK/2.
Note) Peak hold is performed at 34kHz in CLVH mode.
– 18 –
CXD2510Q
$EX commands
Command
D3
D2
D1
D0
CLV mode
CM3
CM2
CM1
CM0
CM3
CM2
CM1
CM0
Mode
Explanation
0
0
0
0
STOP
See the Timing Chart 1-7.
1
0
0
0
KICK
See the Timing Chart 1-8.
1
0
1
0
BRAKE
See the Timing Chart 1-9.
1
1
1
0
CLVS
1
1
0
0
CLVH
1
1
1
1
CLVP
0
1
1
0
CLVA
STOP
KICK
BRAKE
CLVS
CLVP
CLVA
: Spindle motor stop mode.
: Spindle motor forward rotation mode.
: Spindle motor reverse rotation mode.
: Rough servo mode. When the RF-PLL circuit lock is disengaged, this mode is used to pull the disc
rotations within the RF-PLL capture range.
: PLL servo mode.
: Automatic CLVS/CLVP switching mode. This mode is normally used during playback.
– 19 –
– 20 –
C2PO
CDROM = 1
C2PO
CDROM = 0
WDCK
LRCK
Timing Chart 1-3
C2 Pointer for lower 8bits
Rch C2 Pointer
C2 Pointer for upper 8bits
Rch 16bit C2 Pointer
C2 Pointer for lower 8bits
Lch C2 Pointer
C2 Pointer for upper 8bits
Lch 16bit C2 Pointer
If C2 Pointer = 1,
data is NG
48 bit slot
CXD2510Q
– 21 –
SQSO
SQCK
WFCK
SQSO CRCF
SQCK
Timing Chart 1-4
2
L/R
2
3
Sub Q Data
See "Sub Code Interface"
3
96 bit data
Hold section
1
96 clock pulses
1
D0
CRCF
81
D2
1
Level Meter Timing
16 bit
96 clock pulses
D1
Peak data of this section
80
D4
D5
D6
R/L
2
3
CRCF
15-bit peak-data
Absolute value display, LSB first
D3
750ns to 120µs
D13
D14
L/R
Peak data
L/R flag
96
CXD2510Q
SQCK
WFCK
– 22 –
96 clock pulses
Measurement
CRCF
Timing Chart 1-5
1
2
3
Peak Meter Timing
Measurement
CRCF
96 clock pulses
1
2
3
Measurement
CRCF
CXD2510Q
CXD2510Q
Timing Chart 1-6
DCLV PWM MD = 0
Z
MDS
n · 236 (ns) n = 0 to 31
Acceleration
MDP
Z
132kHz
7.6µs
Deceleration
DCLV PWM MD = 1
MDS
Deceleration
Acceleration
MDP
n · 236 (ns) n=0 to 31
7.6µs
Output Waveforms with DCLV = 1
Timing Chart 1-7
DCLV = 0
STOP
MDS
Z
MDP
L
FSW
L
MON
L
DCLV = 1 DCLV PWM MD = 0
STOP
MDS
Z
MDP
Z
FSW and MON are the same as for DCLV = 0
– 23 –
CXD2510Q
DCLV = 1 DCLV PWM MD = 1
STOP
MDS
L
MDP
FSW and MON are the same as for DCLV = 0
Timing Chart 1-8
DCLV = 0
KICK
MDS
Z
MDP
H
FSW
L
MON
H
DCLV = 1 DCLV PWM MD = 0
KICK
Z
MDS
MDP
H
Z
7.6µs
FSW and MON are the same as for DCLV = 0
DCLV = 1 DCLV PWM MD = 1
KICK
H
MDS
MDP
H
L
FSW and MON are the same as for DCLV = 0
– 24 –
CXD2510Q
Timing Chart 1-9
BRAKE
DCLV = 0
MDS
Z
MDP
L
FSW
L
MON
H
DCLV = 1 DCLV PWM MD = 0
BRAKE
MDS
Z
MDP
Z
L
FSW and MON are the same as for DCLV = 0
DCLV =1 DCLV PWM MD = 1
L
MDS
MDP
H
L
FSW and MON are the same as for DCLV = 0
– 25 –
CXD2510Q
§2. Subcode Interface
This section explains the subcode interface.
There are two methods for reading out a subcode externally. The 8-bit subcodes P to W can be read from
SBSO by inputting EXCK.
Sub Q can be read out after the CRC check of the 80 bits of information in the subcode frame.
This is accomplished, after checking SCOR and CRCF, by inputting 80 clock pulses to SQCK and reading data
from the SQSO pin.
§2-1. P to W Subcode Read
Data can be read out by inputting EXCK immediately after WFCK falls. (See the Timing Chart 2-1.)
§2-2. 80-bit Sub Q read
Fig. 2-2 shows the peripheral block of the 80-bit Sub Q register.
• First, Sub Q, regenerated at one bit per frame, is input to the 80-bit serial/parallel register and the CRC
check circuit.
• 96-bit Sub Q is input, and if the CRC is OK, it is output to SQSO with CRCF = 1. In addition, the 80 bits are
loaded into the parallel/serial register.
When SQSO goes high after SCOR is output, the CPU determines that new data (which passed the CRC
check) has been loaded.
• In the CXD2510Q, when 80-bit data is loaded, the order of the MSB and LSB is inverted for each byte. As a
result, although the sequence of bytes is the same, the bits within the bytes are now ordered LSB first.
• Once the fact that the 80-bit data has been loaded is confirmed, SQCK is input so that the data can be
read. In this LSI, the SQCK input is detected, and the retriggerable monostable multivibrator is reset during
low.
• The retriggerable monostable multivibrator has a time constant from 270 to 400µs. When the duration that
SQCK is high is less than this time constant, the monostable multivibrator is kept reset; during this interval,
the S/P register is not loaded into the P/S register.
• While the monostable multivibrator is being reset, data cannot be loaded in the peak detection
parallel/serial register or the 80-bit parallel/serial register.
In other words, while reading out with a clock cycle shorter than the monostable multivibrator time constant,
the register will not be rewritten by CRCOK and others.
• In this LSI, the previously mentioned peak detection register can be connected to the shift-in of the 80-bit
P/S register.
Input and output for ring control 1 are shorted in peak meter or level meter mode.
Ring control 2 is shorted in peak meter mode.
This is because the register is reset with each readout in level meter mode, and to prevent readout
destruction in peak meter mode.
As a result, the 96-bit clock must be input in peak meter mode.
• In addition, as previously mentioned, the absolute time after peak is generated is stored in the memory in
peak meter mode.
Fig. 2-3 shows the Timing Chart.
• Although a clock is input from the SQCK pin to actually perform these operations, the high and low intervals
for this clock should be between 750ns and 120µs.
– 26 –
CXD2510Q
Timing Chart 2-1
Internal
PLL clock
4.3218 ±DMHz
WFCK
SCOR
EXCK
750ns max
SBSO
S0 · S1
Q
R
WFCK
SCOR
EXCK
SBSO
S0•S1 Q R S T U V W S0•S1
Same
P1
Q R S T
U V W
P1
Same
Subcode P.Q.R.S.T.U.V.W Read Timing
– 27 –
P2
P3
SUBQ
Block Diagram 2-2
SI
8
(ASEC)
LD
Order
Inversion
8
(AMIN)
LD
SUBQ
LD
– 28 –
LD
LD
Peak detection
16
16 bit P/S register
Monostable
multivibrator
8
SI
8
8
Ring control 2
SHIFT
8
LD
SO
LOAD CONTROL
CRCC
80 bit P/S Register
8
80 bit S/P Register
SHIFT
8
CRCF
Mix
8
ADDRS CTRL
LD
Ring control 1
ABS time load control
for peak value
H G F E D C B A
A B C D E F G H
SIN
(AFRAM)
SQCK
SO
SQSO
CXD2510Q
LD
– 29 –
SQSO
SQCK
SQCK
SQSO
SCOR
WFCK
Timing Chart 2-3
CRCF
Monostable
Multivibrator
(Internal)
CRCF1
1
2
3
2
1
ADR1
94
ADR2
ADR3
CTL0
270 to 400µs when SQCK = high.
Register load forbidder
CRCF1
Determined by mode
93
92
91
80 or 96 Clock
750ns to 120µs
300ns max
ADR0
3
95
CTL1
96
CTL2
97
CTL3
CRCF2
98
CXD2510Q
Signal
750ns or more
C1F0
C1F1 C1F2 C2F0 C2F1 C2F2 FOK
GFS LOCK EMPH
– 30 –
High when the frame sync and the insertion protection timing match.
GFS is sampled at 460 Hz; when GFS is high, this pin outputs a high signal.
If GFS is low eight consecutive samples, this pin outputs low.
Outputs a high signal when the playback disc has emphasis.
GFS
LOCK
EMPH
C1F1
0
0
1
1
0
0
1
1
C1F2
0
0
0
0
1
1
1
1
1
0
1
0
1
0
1
0
C1F0
; C1 pointer set
; C1 pointer set
; C1 pointer reset
; C1 pointer reset
C1 correction impossible ; C1 pointer set
Two C1 errors corrected ; C1 pointer set
One C1 error corrected
No C1 errors
—
—
One C1 error corrected
No C1 errors
Description
C2F1
0
0
1
1
0
0
1
1
C2F2
0
0
0
0
1
1
1
1
1
0
1
0
1
0
1
0
C2F0
; C2 pointer reset
C2 correction impossible ; C2 pointer set
C2 correction impossible ; C1 pointer copy
—
Four C2 errors corrected ; C2 pointer reset
Three C2 errors corrected ; C2 pointer reset
Two C2 errors corrected
; C2 pointer reset
; C2 pointer set
Description
One C2 error corrected
No C2 errors
∗ RF jitter amount, PER0 to PER7 is output in binary code.When RF jitter amount is little, value of binary code is small.
Focus OK
FOK
RF jitter amount (used to adjust the focus bias). 8bit binary data in PER0 = LSB, PER7 = MSB.
Explanation
PER1 PER2 PER3 PER4 PER5 PER6 PER7
Internal signal latch
PER0
PER0 to PER7 ∗
SQSO
SQCK
XLAT
Set SQCK and EXCK high during this interval.
Example: $802 latch
Timing Chart 2-4
CXD2510Q
CXD2510Q
§3. Description of Other Functions
§3-1. Channel Clock Regeneration by the Digital PLL Circuit
• The channel clock is necessary for demodulating the EFM signal regenerated by the optical system.
Assuming T as the channel clock cycle, the EFM signal is modulated in an integer multiple of T from 3T to
11T. In order to read the information in the EFM signal, this integer value must be read correctly. As a
result, T, that is the channel clock, is necessary.
In an actual player, PLL is necessary to regenerate the channel clock because the fluctuation in the spindle
rotation alters the width of the EFM signal pulses.
The block diagram of this PLL is shown in Fig. 3-1.
The CXD2510Q has a built-in three-stage PLL.
• The first-stage PLL regenerates the variable pitch.
LPF and VCO are necessary as external parts.
The minimum variable amount of the pitch is 0.1%. The output of this first-stage PLL is used as a reference
for all clocks within the LSI. Input the XTAO output to the VCKI pin when variable pitch is not used.
• The second-stage PLL regenerates a high-frequency clock needed by the third-stage digital PLL.
• The third-stage PLL is a digital PLL that regenerates the actual channel clock, and has a ±150kHz (normal
state) or more capture range.
• The digital PLL has a secondary loop, and is controlled by the primary loop (phase) and the secondary loop
(frequency). When FLFC = 1, the secondary loop can be turned off .
• High-frequency components such as 3T and 4T may contain deviations. In such a case, turning the
secondary loop off yields better playability.
However, in this case the capture range becomes 50kHz.
– 31 –
CXD2510Q
Block Diagram 3-1
16.9344MHz
(384Fs)
1/4
1/1000
Phase comparator
OSC
X'Tal
XTSL
1/4
1/1000 + n
LPF
VPCO
VCO
19.78 to 13.26MHz
VCKI
2/1 MUX
Vari-Pitch
Up down counter
n = –217 to 168
Microcomputer control
Vari-Pitch
Phase comparator
I/M
I/N
PCO
FILI
FILO
VCO
CLTV
Digital PLL
VDD
RFPLL
CXD2510Q
– 32 –
CXD2510Q
§3-2. Frame Sync Protection
• In a CD player operating at normal speed, a frame sync is recorded approximately every 136µs (7.35kHz).
This signal is used as a reference to know which data is the data within a frame. Conversely, if the frame
sync cannot be recognized, the data is processed as error data because the data cannot be recognized.
As a result, recognizing the frame sync properly is extremely important for improving playability.
• In the CXD2510Q, window protection and forward protection/backward protection have been adopted for
frame sync protection. The adoption of these functions achieves very powerful frame sync protection.
There are two window widths: one for cases where a rotational disturbance affects the player and the other
for cases where there is no rotational disturbance (WSEL = 0/1). In addition, the forward protection counter
is fixed to 13, and the backward protection counter to 3. In other words, when the frame sync is being
played back normally and then cannot be detected due to scratches, a maximum of 13 frames are inserted.
If frame sync cannot be detected for 13 frames or more, the window is released and the frame sync is
resynchronized.
In addition, immediately after the window is released and the resynchronization is executed, if a proper
frame sync cannot be detected within 3 frames, the window is released immediately.
§3-3. Error correction
• In the CD format, one 8-bit data contains two error correction codes, C1 and C2. For C1 correction, the
code is created with 28-byte information and 4-byte C1 parity.
For C2 correction, the code is created with 24-byte information and 4-byte parity.
Both C1 and C2 are Reed Solomon codes with a minimum distance of 5.
• The CXD2510Q uses refined super strategy to achieve double correction for C1 and quadruple correction
for C2.
• In addition, to prevent C2 miscorrection, a C1 pointer is attached to data after C1 correction according to
the C1 error status, the playback status of the EFM signal, and the operating status of the player.
• The correction status can be monitored outside the LSI.
See the Table 3-2.
• When the C2 pointer is high, the data in question was uncorrectable. Either the pre-value was held or an
average value interpolation was made for the data.
MNT3
MNT2
MNT1
MNT0
0
0
0
0
No C1 errors
; C1 pointer reset
0
0
0
1
One C1 error corrected
; C1 pointer reset
0
0
1
0
—
0
0
1
1
—
0
1
0
0
No C1 errors
; C1 pointer set
0
1
0
1
One C1 error corrected
; C1 pointer set
0
1
1
0
Two C1 errors corrected
; C1 pointer set
0
1
1
1
C1 correction impossible
; C1 pointer set
1
0
0
0
No C2 errors
; C2 pointer reset
1
0
0
1
One C2 error corrected
; C2 pointer reset
1
0
1
0
Two C2 errors corrected
; C2 pointer reset
1
0
1
1
Three C2 errors corrected
; C2 pointer reset
1
1
0
0
Four C2 errors corrected
; C2 pointer reset
1
1
0
1
1
1
1
0
C2 correction impossible
; C1 pointer copy
1
1
1
1
C2 correction impossible
; C2 pointer set
Description
—
Table 3-2.
– 33 –
CXD2510Q
Timing Chart 3-3
Normal-speed PB
400 to 500ns
RFCK
t = Dependent on error
condition
MNT3
C1 correction
C2 correction
MNT2
MNT1
MNT0
Strobe
Strobe
§3-4. DA Interface
• The CXD2510Q has two modes as DA interfaces.
a) 48-bit slot interface
This interface includes 48 cycles of the bit clock within one LRCK cycle, and is MSB first.
When LRCK is high, the data is for the left channel.
b) 64-bit slot interface
This interface includes 64 cycles of the bit clock within one LRCK cycle, and is LSB first.
When LRCK is low, the data is for the left channel.
– 34 –
R0
1
2
– 35 –
DA16
WDCK
DA15
(4.23M)
LRCK
(88.2K)
R0
1 2
3
4
5
Lch MSB (15)
Lch MSB (15)
48bit slot Double-Speed Playback
DA16
WDCK
DA15
(2.12M)
LRCK
(44.1K)
48bit slot Normal-Speed Playback PSSL = L
Timing Chart 3-4
6
7
8
9
L14
10
L13
11
L12
12
L0
24
L11
L9
Rch MSB
L10
L8
L7
L6
L5
L4
L3
L2
L1
L0
24
RMSB
CXD2510Q
– 36 –
DA14
DA13
(5.64M)
DA12
(88.2K)
DA14
DA13
(2.82M)
DA12
(44.1K)
2
3
4
5
L15
1
2
3
4
5
64 Bit slot Double- Speed PB
1
64 Bit slot Normal Speed PB PSSL = L
Timing Chart 3-5
6
9
10
10
R ch LSB (0)
8
R ch LSB (0)
7
11
12
15
13
14
15
1
2
3
20
4
1
5
2
6
3
20
7
8
25
4
9
5
7
9
10
30 31 32
8
10 11 12 13 14 15
6
11
13
L ch LSB
12
30
32
14 R15
31
L ch LSB (0)
CXD2510Q
CXD2510Q
§3-5. Digital Out
There are three digital out formats: the type 1 format for broadcasting stations, the type 2 form 1 format for
home use, and the type 2 form 2 format for the manufacture of software.
The CXD2510Q supports type 2 form 1.
In addition, regarding the clock accuracy of the channel status, level III is set automatically when the crystal
clock is used and level II is variable pitch. In addition, Sub Q data which are matched twice in succession
after a CRC check are input to the first four bits (bit 0 to 3).
DOUT is output when the crystal is 34MHz, the variable pitch is reset, and DSPB = 1. Therefore, set MD2 to
0 and turn DOUT off.
bit 0 to 3 -Sub Q control bits that matched twice with CRCOK
Digital Out C bit
0
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0/1
0
0
From sub Q
0
ID0
16
1
0
ID1 COPY Emph
0
0
0
32
48
0
176
bit 0 to 3 – Sub Q control bits that matched twice with CRCOK
bit29
– Varipitch: 1
X'Tal: 0
Table 3-6.
§3-6. Servo Auto Sequence
This function performs a series of controls, including auto focus and track jumps. When the auto sequence
command is received from the CPU, auto focus, 1 track jump, 2N track jumps, and fine search are executed
automatically.
SSP (servo signal processor LSI) is used in an exclusive manner during the auto sequence execution (when
XBUSY = low), so that commands from the CPU are not transferred to the SSP, but can be sent to the
CXD2510Q.
In addition, when using the auto sequence, connect the CPU, RF and SSP as shown in Fig. 3-7, and turn the
A.SEQ of register 9 on.
When CLOK goes from low to high while XBUSY is low, XBUSY does not become high for a maximum of
100µs after that point. This is designed to prevent the transfer of erroneous data to the SSP when XBUSY
changes from low to high by the monostable multivibrator, which is reset by CLOK being low (when XBUSY
is low).
– 37 –
CXD2510Q
In addition, a MAX timer is built in as a countermeasure against abnormal operation due to external
disturbances, etc. When the auto sequence command is sent from the CPU, this command assumes a $4XY
format, in which X specifies the command and Y sets the MAX timer value and timer range. If the executed
auto sequence command does not terminate within the set timer value, the auto sequence is interrupted (like
$40). See §1-2, $4X commands concerning the timer value and range. Also, the MAX timer is invalidated by
inputting $4X0.
Although this command is explained in the format of $4X in the following command descriptions, the timer
value and timer range are actually sent together from the CPU.
(a) Auto focus ($47)
Focus search up is performed, FOK and FZC are checked, and the focus servo is turned on.
If $47 is received from the CPU, the focus servo is turned on according to Fig. 3-8. The auto focus is
executed after focus search up, and the pickup should be lowered beforehand (focus search down). In
addition, blind E of register 5 is used to eliminate FZC chattering. In other words, the focus servo is turned
on at the falling edge of FZC after FZC has been continuously high for a longer time than E.
Connection diagram for using the auto sequencer (example)
RF
MIRR
FOK
MIRR
FOK
DATA
CXD2510Q
CLOK
Micro-computer
XLAT
SSP
C. out
CNIN
SENS
SEIN
DATA
DATO
CLK
CLKO
XLT
XLTO
Fig. 3-7.
– 38 –
SENS
CXD2510Q
Auto focus
Focus search up
FOK = H
NO
YES
FZC = H
NO
YES
FZC = L
Check whether FZC is
continuously high for the period
of time E set with register 5.
NO
YES
Focus servo ON
END
Fig. 3-8. (a) Auto Focus Flow Chart
$47latch
XLAT
FOK
SEIN (FZC)
BUSY
Command
for SSP
Blind E
$08
$03
Fig. 3-8. (b) Auto Focus Timing Chart
– 39 –
CXD2510Q
(b) Track jump
1, 10, and 2N-track jumps are performed respectively. Always use this when focus, tracking, and sled servo
are on. Note that tracking gain up and braking on ($17) should be sent beforehand because they are not
performed.
• 1-track jump
When $48 ($49 for REV) is received from the CPU, a FWD (REV) 1-track jump is performed in
accordance with Fig. 3-9. Set blind A and brake B with register 5.
• 10-track jump
When $4A ($4B for REV) is received from the CPU, a FWD (REV) 10-track jump is performed in
accordance with Fig. 3-10. The principal difference between the 10-track jump and the 1-track jump is
whether to kick the sled or not. In addition, after kicking the actuator, when 5 tracks have been counted
through CNIN, the brake is applied to the actuator. Then, when the actuator speed is found to have
slowed up enough (determined by the CNIN cycle becoming longer than the overflow C set in register 5),
the tracking and sled servos are turned on.
• 2N-track jump
When $4C ($4D for REV) is received from the CPU, a FWD (REV) 2N-track jump is performed in
accordance with Fig. 3-11. The track jump count "N" is set in register 7. Although N can be set to 216
tracks, note that the setting is actually limited by the actuator. CNIN is used for counting the number of
jumps when N is less than 16, and MIRR is used when N is 16 or higher.
Although the 2N-track jump basically follows the same sequence as the 10-track jump, the one difference
is that after the tracking servo is turned on, the sled continues to move only for "D", set in register 6.
• Fine search
When $44 ($45 for REV) is received from the CPU, a FWD (REV) fine search (N-track jump) is performed
in accordance with Fig. 3-12. The one difference from a 2N-track jump is that a higher precision is
achieved by controlling the traverse speed. The track jump count is set in register 7. N can be set to 216
tracks. After kicking the actuator and sled, the traverse speed is controlled based on the overflow G. Set
kick D and F in register 6 and overflow G in register 5. After N tracks have been counted through CNIN,
the brake is applied to the actuator and sled. This is performed by turning the tracking servo for the
actuator on, and by kicking the sled in the opposite direction. The cancel command $40 is sent from the
CPU when track jump is terminated.
Set overflow G to the speed required to slow up just before the track jump terminates. The speed should
be such that it will come on-track when the tracking servo turns on at the termination of the track jump.
(Set the target track count N-α for the traverse monitor counter which is set in register B, and COMP will
be monitored. When the falling edge of this COMP is detected, overflow G can be reset.)
– 40 –
CXD2510Q
1 Track
Track kick
sled servo
(REV kick for REV jump)
WAIT
(Blind A)
CNIN =
NO
YES
Track REV
kick
(FWD kick for REV jump)
WAIT
(Brake B)
Track sled
servo ON
END
Fig. 3-9. (a) 1-Track Jump Flow Chart
$48 (REV = $49) latch
XLAT
CNIN
BUSY
Brake B
Blind A
Command
for SSP
$28 ($2C)
$2C ($28)
Fig. 3-9. (b) 1-Track Jump Timing Chart
– 41 –
$25
CXD2510Q
10 Track
Track, sled
FWD kick
WAIT
(Blind A)
CNIN = 5 ?
NO
(Counts CNIN × 5)
NO
Checks whether the CNIN cycle
is longer than overflow C.
YES
Track, REV
kick
C = Overflow ?
YES
Track, sled
servo ON
END
Fig. 3-10. (a) 10-Track Jump Flow Chart
$4A (REV = $4B) latch
XLAT
CNIN
BUSY
Blind A
CNIN 5count
Overflow C
Command
for SSP
$2E ($2B)
$2A ($2F)
Fig. 3-10. (b) 10-Track Jump Timing Chart
– 42 –
$25
CXD2510Q
2N Track
Track, sled
FWD kick
WAIT
(Blind A)
CNIN (MIRR) = N
NO
Counts CINI for the first 16 times
and MIRR for more times.
YES
Track REV
kick
C = Overflow
NO
YES
Track servo
ON
WAIT
(Kick D)
Sled servo
ON
END
Fig. 3-11. (a) 2N-Track Jump Flow Chart
$4C (REV = $4D) latch
XLAT
CNIN
(MIRR)
BUSY
Blind A
Command
$2A ($2F)
for SSP
CNIN (MIRR)
N count
Overflow
$2E ($2B)
$26 ($27)
Fig. 3-11. (b) 2N-Track Jump Timing Chart
– 43 –
Kick D
$25
CXD2510Q
Fine Search
Track Servo ON
Sled FWD Kick
WAIT
(Kick D)
Track Sled
FWD Kick
WAIT
(Kick F)
Traverse
Speed Ctrl
(Overflow G)
CNIN = N ?
NO
YES
Track Servo ON
Sled REV Kick
Track jump is terminated by sending
and latching $40 from the CPU.
END
Fig. 3-12. (a) Fine Search Flow Chart
$44 (REV = $45) latch
$40 (cancel) latch
XLAT
CNIN
Kick D
$26 ($27)
Command
for SSP
Kick F
Traverse Speed Control (Overflow G)
&
CNIN N count
$2A ($2F)
$27 ($26)
$25
Fig. 3-12. (b) Fine Search Timing Chart
– 44 –
CXD2510Q
§3-7. Digital CLV
Fig. 3-13 shows the block diagram. Digital CLV makes PWM output in CLVS, CLVP and other modes with
the MDS error or MDP error signal sampling frequency increased to 130kHz during normal-speed operation.
In addition, the digital spindle servo can set the gain.
Digital CLV
CLVS U/D
Gain
CLVS
CLV P/S
MDS Error
MDP Error
Measure
Measure
Over Sampling
Filter-1
2/1 MUX
Gain
MDS
Gain
MDP
1/2
CLV P
Mux
CLV S
Gain
DCLV
Over Sampling
Filter-2
CLV-P/S
Noise Shape
KICK, BRAKE STOP
Modulation
Mode Select
DCLVMD
CLVS U/D: Up/down signal from the CLV-S servo.
MDS error: Frequency error for CLV-P servo.
MDP error: Phase error for CLV-P servo.
Fig. 3-13. Block Diagram
– 45 –
MDP
MDS
CXD2510Q
§3-8. Asymmetry Compensation
Fig. 3-14 shows the block diagram and circuit example.
D2510
28
ASYE
ASYO
27
R1
RF
24
R1
R2
R1
ASYI
26
R1
25
BIAS
R1
2
=
R2
5
Fig. 3-14. Example of an Asymmetry Compensation Application Circuit
§3-9. Playback Speed
In the CXD2510Q, the following playback modes can be selected through different combinations of the
crystal, XTSL pin, double-speed command (DSPB), VCO selection command (VCOSEL) and command
transfer rate selector (ASHS). Also, the minimum operating voltage changes according to the playback mode.
(See the Recommended Operating Conditions.)
Playback modes
Mode
X'tal
XTSL
DSPB
VCOSEL
ASHS
Playback speed
1
768Fs
1
0
0/1
0
×1
C1: double; C2: quadruple
2
768Fs
1
1
0/1
0
×2
C1: double; C2: double
3
768Fs
0
0
1
1
×2
C1: double; C2: quadruple
4
768Fs
0
1
1
1
×4
C1: double; C2: double
5
384Fs
0
0
0/1
0
×1
C1: double; C2: quadruple
6
384Fs
0
1
0/1
0
×2
C1: double; C2: double
7
384Fs
1
1
0/1
0
×1
C1: double; C2: double
However, Fs = 44.1kHz.
– 46 –
Error correction
GND
SSTOP
GND
SPIND-D
GND
SLED-D
GND
FOCUS-D
GND
TRACK-D
TD
GND
R5
R2
R1
GND
R9
GND
TG2
AVCC
TA0
TA–
10
11
12
R14
R11
C35
GND
GND
R10
GND
R6
C28
TGU
SRCH
8
7
FE–
FLB
4
FEO
FS3
5
FGD
2
3
6
VC
1
9
C27
C23
C26
C10
C9
GND
R7
GND
SLD
SPD
FD
C15
C16
VCC
RF
TE
CXA1372AQ
C13
R13
R12
GND
R4 R3
28
27
26
25
SENS
COUT
XRST
DFCT
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
GND
VCOI
9
CXD2510Q
FSTT
VCOO
8
NC
NC
VPCO
VCKI
FILO
FILI
PCO
14
15
16
17
18
19
20
RF
24
GND
52
VSS
49
48
MNT0
MNT1
43
42
41
RFCK
GFS
XPLCK
GND
45
44
C2PO
46
MNT3
MNT2 47
50
APTR
APTL 51
53
XTAI
54
55
56
57
58
59
XRAOF
25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
200p
1M
AVDD
23
AVDD
CLTV
22
AVSS
TEST0
13
21
VSS
12
XTSL
FSOF
NC
7
XTAO
C16M
LOCK
PDO
MD2
MDS
5
6
TEST
DOUT
MDP
4
11
61
EMPH
MON
3
10
63
WFCK 62
FSW
2
60
SBSO 64
SCOR
FOK
1
DEMP
LRCK
DATA
BCLK
C2PO
DOUT
WFCK
GTOP
XUGF
XPLCK
GFS
RFCK
XRAOF
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
13 14 15 16 17 18 19 20 21 22 23 24
29
MIRR
30
31
32
33
34
35
36
FOK
DGND
DFCT
ASY
EFM
FOK
CC2
CC1
DVCC
C17
MIRR
GND
MIRR
BIAS
GND GND
VDD
CLKO
ASYI
RF
XLTO
ASYO
LDON
C14
48 47 46 45 44 43 42 41 40 39 38 37
C12
FDFCT
SL+
GND
FE
SL0
MUTE
DATO
ASYE
GND
FZC
SL–
SQCK
SEIN
PSSL
FE
C11
ATSC
FSET
SUBQ
CLOK
WDCK(48)
TDFCT
ISET
GFS
VDD
LRCK (48) VDD
TE
SSTOP
CLK
XLAT
DATA (48)
DVCC
DIRC
XLT
DATA
BCLK (48)
TZC
AVCC
DATA
XRST
DATA (64)
VO
RF0
LOCK
XRST
SENS
BCLK (64)
VCC
RF1
CLK
SENS
MUTE
LRCK (64)
TE
CP
XLT
FOK
SQCK
GTOP
GND
CB
DATA
EXCK
FE
GND
SCOR
CNIN
NC
GND
GND
GND GND GND
GND
LDON
SQSO
XUGF
RV2
VSS
GND
GND
MUTE
GND
GND
WDCK
RV1
GND
– 47 –
VCC
GND
Application Circuit
GND
MNT3
MNT2
MNT1
MNT0
GND
CXD2510Q
CXD2510Q
Unit: mm
80PIN QFP (PLASTIC)
23.9 ± 0.4
+ 0.1
0.15 – 0.05
+ 0.4
20.0 – 0.1
64
0.15
41
65
16.3
+ 0.4
14.0 – 0.1
17.9 ± 0.4
40
A
80
+ 0.2
0.1 – 0.05
1
24
0.8
0.12
+ 0.15
0.35 – 0.1
M
0.8 ± 0.2
25
+ 0.35
2.75 – 0.15
0° to 10°
DETAIL A
PACKAGE STRUCTURE
SONY CODE
QFP-80P-L01
EIAJ CODE
∗QFP080-P-1420-A
JEDEC CODE
PACKAGE MATERIAL
EPOXY RESIN
LEAD TREATMENT
SOLDER PLATING
LEAD MATERIAL
COPPER / 42 ALLOY
PACKAGE WEIGHT
1.6g
QFP 80PIN (PLASTIC)
23.9 ± 0.2
∗20.0 ± 0.2
0.15 ± 0.05
15°
24
1
0.35 ± 0.1
.2
15°
25
80
A
4 – 1.0
40
∗14.0 ± 0.2
4 – 0.8
0.15
M
1.45
0.8 ± 0.15
0.15
0° to 10°
DETAIL A
NOTE: Dimension “∗” does not include mold protrusion.
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
SONY CODE
QFP-80P-L051
LEAD TREATMENT
SOLDER PLATING
EIAJ CODE
∗QFP080-P-1420-AH
LEAD MATERIAL
42 ALLOY
PACKAGE WEIGHT
1.6g
JEDEC CODE
– 48 –
1.95 ± 0.15
15°
2.94 ± 0.15
15°
0.24 ± 0.15
+ 0.20
2.7 – 0.16
17.9 ± 0.2
65
0.8
41
64
C1
Package Outline