CXP84540/84548 CMOS 8-bit Single Chip Microcomputer Description The CXP84540/84548 is a CMOS 8-bit microcomputer integrating on a single chip an A/D converter, serial interface, timer/counter, time-base timer, capture timer/counter, PWM output and the like besides the basic configurations of 8-bit CPU, ROM, RAM and I/O port. The CXP84540/84548 also provide a sleep/stop functions that enable to execute the power-on reset function or lower the power consumption. 80 pin QFP (Plastic) 80 pin LQFP (Plastic) Features • Wide range instruction system (213 instructions) which covers various of data — 16-bit arithmetic/multiplication and division/Boolean bit operation instructions • Minimum instruction cycle 143ns at 28MHz operation (4.5 to 5.5V) 200ns at 20kHz operation (3.0 to 5.5V) • Incorporated ROM capacity 40K bytes (CXP84540) 48K bytes (CXP84548) • Incorporated RAM capacity 1472 bytes • Peripheral functions — A/D converter 8 bits, 8 channels, successive approximation method (Conversion time of 1.93µs / at 28MHz, 2.7µs / at 20MHz) — Serial interface Incorporated 8-bit, 8-stage FIFO (Auto transfer for 1 to 8 bytes, latch output function, MSB/LSB first selectable), 1 channel 8-bit clock syncronization, 1 channel — Timer 8-bit timer 8-bit timer/counter 19-bit time-base timer 16-bit capture time/counter — PWM output 8 bits, 2 channels • Interruption 14 factors, 14 vectors, multi-interruption possible • Standby mode Sleep/Stop • Package 80-pin plastic QFP/LQFP • Piggyback/evaluator CXP84500 Structure Silicon gate CMOS IC Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E96528A77-PS –2– TO CINT EC1 16 BIT CAPTURE TIMER/COUNTER 2 8 BIT TIMER 1 8 BIT TIMER/COUNTER 0 FIFO EC0 SERIAL INTERFACE UNIT (CH0) 8 BIT PWM GENERATOR 1 8 BIT PWM GENERATOR 0 A/D CONVERTER AVss SERIAL INTERFACE UNIT (CH1) 8 AVREF SI1 SO1 SCK1 CS0 SI0 SO0 SCK0 LAT0 PWM1 PWM0 AN0 to AN7 2 2 INT0 INT1 INT2 INT3 INTERRUPT CONTROLLER Block Diagram PRESCALER/ TIME BASE TIMER ROM 40K/48K BYTES SPC700 CPU CORE RST VDD Vss EXTAL XTAL RAM 1472 BYTES CLOCK GENERATOR/ SYSTEM CONTROL 8 PI0 to PI7 PH0 to PH7 PG0 to PG7 8 8 PF0 to PF7 PE4 to PE7 4 8 PE0 to PE3 PD0 to PD7 PC0 to PC7 PB0 to PB7 PA0 to PA7 4 8 8 8 8 CXP84540/84548 PORT I PORT H PORT G PORT F PORT E PORT D PORT C PORT B PORT A NMI CXP84540/84548 PI5 PI7 PI6 PG0 PG1 PG3 PG2 VDD NC PG5 PG4 PG6 PG7 PF0 PF1 PF2 Pin Assignment (Top View) 80-pin QFP package 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 PF3 1 64 PI4 PF4 2 63 PI3/INT3 PF5 3 62 PI2/INT2 PF6 4 61 PI1/INT1 PF7 5 60 PI0/INT0 PD0 6 59 PE5/TO/PWM1 PD1 7 58 PE4/PWM0 PD2 8 57 PE3/NMI PD3 9 56 PE2/CINT PD4 10 55 PE1/EC1 PD5 11 54 PE0/EC0 PD6 12 53 PB7/SO1 PD7 13 52 PB6/SI1 PC0 14 51 PB5/SCK1 PC1 15 50 PB4/SO0 PC2 16 49 PB3/SI0 PC3 17 48 PB2/SCK0 PC4 18 47 PB1/CS0 PC5 19 46 PB0/LAT0 PC6 20 45 PA7/AN7 PC7 21 44 PA6/AN6 PH0 22 43 PA5/AN5 PH1 23 42 PA4/AN4 PH2 24 41 PA3/AN3 PA2/AN2 PA1/AN1 AVREF PA0/AN0 AVSS PE7 VSS PE6 XTAL EXTAL PH7 RST PH6 PH5 PH3 PH4 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Note) NC (Pin 73) is left open. However, this pin is used for the Flash EEPROM incorporated version (CXP845F60). –3– CXP84540/84548 PI3/INT3 PI4 PI5 PI6 PI7 PG0 PG1 PG2 PG3 VDD NC PG4 PG5 PG6 PG7 PF0 PF1 PF2 PF3 PF4 Pin Assignment (Top View) 80-pin LQFP package 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 PF5 1 60 PI2/INT2 PF6 2 59 PI1/INT1 PF7 3 58 PI0/INT0 PD0 4 57 PE5/TO/PWM1 PD1 5 56 PE4/PWM0 PD2 6 55 PE3/NMI PD3 7 54 PE2/CINT PD4 8 53 PE1/EC1 PD5 9 52 PE0/EC0 PD6 10 51 PB7/SO1 PD7 11 50 PB6/SI1 PC0 12 49 PB5/SCK1 PC1 13 48 PB4/SO0 PC2 14 47 PB3/SI0 PC3 15 46 PB2/SCK0 PC4 16 45 PB1/CS0 PC5 17 44 PB0/LAT0 PC6 18 43 PA7/AN7 PC7 19 42 PA6/AN6 PH0 20 41 PA5/AN5 Note) NC (Pin 73) is left open. –4– PA4/AN4 PA3/AN3 PA2/AN2 PA1/AN1 PA0/AN0 AVREF PE7 AVSS PE6 VSS XTAL EXTAL RST PH7 PH6 PH5 PH4 PH3 PH2 PH1 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 CXP84540/84548 Pin Description Symbol I/O PA0/AN0 to PA7/AN7 I/O/Analog input PB0/LAT0 I/O/Output PB1/CS0 I/O/Input PB2/SCK0 I/O/I/O PB3/SI0 I/O/Input PB4/SO0 I/O/Output PB5/SCK1 I/O/I/O PB6/SI1 I/O/Input PB7/SO1 I/O/Output Description (Port A) 8-bit I/O port. I/O can be set in a unit of single bits. Incorporation of the Analog inputs to A/D converter. pull-up resistance can be (8 pins) set through the software in a unit of 4 bits. (8 pins) Latch output for serial interface (CH0). (Port B) 8-bit I/O port. I/O can be set in a unit of single bits. Incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (8 pins) Chip select input for serial interface (CH0). Serial clock I/O (CH0). Serial data input (CH0). Serial data output (CH0). Serial clock I/O (CH1). Serial data input (CH1). Serial data output (CH1). I/O (Port C) 8-bit I/O port. I/O can be set in a unit of single bits. Can drive 12mA sync current. Incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (8 pins) PD0 to PD7 I/O (Port D) 8-bit I/O port. I/O can be set in a unit of single bits. Incorporation of pullup resistor can be set through the software in a unit of 4 bits. (8 pins) PE0/EC0 Input/Input PE1/EC1 Input/Input PE2/CINT Input/Input PE3/NMI Input/Input PE4/PWM0 Output/Output PE5/TO/ PWM1 Output/Output/ Output PE6 Output PE7 Output PC0 to PC7 PF0 to PF7 I/O External event inputs for timer/counter. (2 pins) (Port E) 8-bit port. Lower 4 bits are for inputs; upper 4 bits are for outputs. (8 pins) Capture trigger input. Non-maskable interruption request input. 8-bit PWM0 output. Rectangular wave output for 16-bit timer/ counter and 8-bit PWM1 output. (Port F) 8-bit I/O port. I/O can be set in a unit of single bits. Incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (8 pins) –5– CXP84540/84548 Symbol PG0 to PG7 PH0 to PH7 I/O I/O (Port G) 8-bit I/O port. I/O can be set in a unit of single bits. Incorporation of pullup resistor can be set through the software in a unit of 4 bits. (8 pins) I/O (Port H) 8-bit I/O port. I/O and standby release input function can be set in a unit of single bits. Incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (8 pins) PI0/INT0 to PI3/INT3 I/O/Input PI4 to PI7 I/O EXTAL Input XTAL Output RST I/O (Port I) 8-bit I/O port. I/O can be set in a unit of single bits. Incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (8 pins) External interruption request inputs. (4 pins) Crystal connectors for system clock oscillation. When the clock is supplied externally, input it to EXTAL; opposite phase clock should be input to XTAL. System reset for active at Low level. This pin is I/O pin, and outputs Low level at the power on with the power-on reset function executed. (Mask option) No connected. Leave this pin open. However, this is used for the Flash EEPROM incorporated version (CXP845F60). NC AVREF Description Input Reference voltage input for A/D converter. AVss A/D converter GND. VDD Positive power supply. Vss GND –6– CXP84540/84548 Input/Output Circuit Formats for Pins Pin AAAA AAAA AAAA AAAA AAAA When reset Circuit format Port A ∗ Pull-up resistor AA AAAA "0" when reset Port A data PA0/AN0 to PA7/AN7 Port A direction IP "0" when reset Input protection circuit Hi-Z Data bus RD (Port A) Port A function selection Input multiplexer "0" when reset A/D converter 8 pins AAAA AAAA AAAA AAAA AAAA ∗ Pull-up transistor approx. 100kΩ (VDD = 4.5 to 5.5V) approx. 300kΩ (VDD = 3.0 to 3.6V) Port B ∗ Pull-up resistor "0" when reset LAT0 Latch output enable PB0/LAT0 AAA Port B data IP Port B direction "0" when reset Hi-Z Data bus RD (Port B) ∗ Pull-up transistor approx. 100kΩ (VDD = 4.5 to 5.5V) approx. 300kΩ (VDD = 3.0 to 3.6V) 1 pin Port B AAA AAA AAA AAA AAA ∗ Pull-up resistor AA AA AA AA "0" when reset Port B data PB1/CS0 PB3/SI0 PB6/SI1 Port B direction IP "0" when reset Schmitt input Data bus RD (Port B) 3 pins CS0 SI0 SI1 ∗ Pull-up transistor approx. 100kΩ (VDD = 4.5 to 5.5V) approx. 300kΩ (VDD = 3.0 to 3.6V) –7– Hi-Z CXP84540/84548 Pin Port B AAA AAA AAA AAA AAA AAA When reset Circuit format ∗ Pull-up resistor AA AAAA "0" when reset SCK OUT Serial clock output enable Port B function selection "0" when reset PB2/SCK0 PB5/SCK1 IP Port B data Port B direction "0" when reset Data bus Hi-Z Schmitt input RD (Port B) AAA AAA AAA AAA AAA AAA SCK0, SCK1 in 2 pins Port B ∗ Pull-up transistor approx. 100kΩ (VDD = 4.5 to 5.5V) approx. 300kΩ (VDD = 3.0 to 3.6V) ∗ Pull-up resistor SO Serial data output enable AAA Port B function selection "0" when reset PB4/SO0 PB7/SO1 IP Port B data Port B direction "0" when reset Data bus RD (Port B) ∗ Pull-up transistor approx. 100kΩ (VDD = 4.5 to 5.5V) approx. 300kΩ (VDD = 3.0 to 3.6V) 2 pins Port C AAA AAA AAA AAA AAA ∗2 Pull-up resistor AA AA AA AA "0" when reset Port C data PC0 to PC7 Hi-Z ∗1 Port C direction "0" when reset Data bus RD (Port C) IP ∗1 Large current drive (12mA: VDD = 4.5 to 5.5V) ( 5mA: VDD = 3.0 to 3.6V) ∗2 Pull-up transistor approx. 100kΩ (VDD = 4.5 to 5.5V) approx. 300kΩ (VDD = 3.0 to 3.6V) 8 pins –8– Hi-Z CXP84540/84548 Pin When reset Circuit format Port E A A PE0/EC0 PE1/EC1 PE2/CINT PE3/NMI Schmitt input EC0, EC1 CINT, NMI IP Hi-Z Data bus RD (Port E) 4 pins Port E AAAA AAAA AAAA PWM0 Port E function selection "0" when reset PE4/PWM0 Port E data "1" when reset AA AA High level Data bus 1 pin RD (Port E) Port E AAAA AAAA AAAAAAAA AAAA AAAAA AAAAA Internal reset signal PE5/TO/ PWM1 Port E data 00 "1" when reset TO PWM1 01 1x MPX Port E function selection (upper) Port E function selection (lower) "00" when reset TO output enable AA AA( ∗ High level with resistor of pull-up transistor ON for reset ∗ Pull-up transistor approx. 150kΩ (VDD = 4.5 to 5.5V) approx. 400kΩ (VDD = 3.0 to 3.6V) 1 pin Port E AAA AAA AA AA Port E data PE6, PE7 "0" when reset Data bus 2 pins RD (Port E) –9– Low level ) CXP84540/84548 Pin Port D Port F Port G PD0 to PD7 PF0 to PF7 PG0 to PG7 PI4 to PI7 AAAA AAAA AAAAA AAAAA AAAAA When reset Circuit format Port I ∗ Pull-up resistor AA AA AA AA "0" when reset Ports D, F, G, I data Ports D, F, G, I direction IP "0" when reset Data bus RD ∗ Pull-up transistor approx. 100kΩ (VDD = 4.5 to 5.5V) approx. 300kΩ (VDD = 3.0 to 3.6V) 28 pins Port H AAA AAA AAA AAA AAA ∗ Pull-up resistor AA AA AA AA "0" when reset Port H data PH0 to PH7 Port H direction IP "0" when reset Data bus AA AA AAAA AAAA AAAA AAAA AAAA RD (Port H) Edge detection Standby release 8 pins Port I Pull-up resistor "0" when reset Port I data PI0/INT0 to PI3/INT3 Hi-Z Port I direction "0" when reset Data bus ∗ Pull-up transistor approx. 100kΩ (VDD = 4.5 to 5.5V) approx. 300kΩ (VDD = 3.0 to 3.6V) ∗ AA AA AA AA IP Schmitt input RD INT0 INT1 INT2 INT3 ∗ Pull-up transistor approx. 100kΩ (VDD = 4.5 to 5.5V) approx. 300kΩ (VDD = 3.0 to 3.6V) 4 pins – 10 – Hi-Z Hi-Z CXP84540/84548 Pin EXTAL XTAL 2 pins RST 1 pin When reset Circuit format AA AA A AA EXTAL IP • Diagram shows the circuit composition during oscillation. IP • Feedback resistor is removed during stop mode and XTAL becomes High level. Oscillation XTAL AA AA Mask option OP Pull-up resistor AA Schmitt input Low level IP – 11 – From power-on reset circuit (Mask option) CXP84540/84548 Absolute Maximum Ratings (Vss = 0V reference) Item Symbol Supply voltage Ratings Unit VDD –0.3 to +7.0 V AVSS V Remarks Input voltage VIN –0.3 to +0.3 –0.3 to +7.0∗1 Output voltage VOUT –0.3 to +7.0∗1 V High level output current IOH –5 mA Output (value per pin) High level total output current ∑IOH –50 mA Total of all output pins IOL 15 mA IOLC 20 mA Pins excluding large current outputs (value per pin) Large current outputs (value per pin∗2) Low level total output current ∑IOL 100 mA Total of all output pins Operating temperature Topr –20 to +75 °C Storage temperature Tstg –55 to +150 °C Allowable power dissipation PD 600 mW QFP-80P-L01 380 mW LQFP-80P-L01 Low level output current V ∗1 VIN and VOUT must not exceed VDD + 0.3V. ∗2 The large current drive transistor is the N-ch transistor of Port C (PC) Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should be conducted under the recommended operating conditions. Exceeding these conditions may adversely affect the reliability of the LSI. Recommended Operating Conditions Item Supply voltage∗1 High level input voltage Low level input voltage Operating temperature ∗1 ∗2 ∗3 ∗4 Symbol (Vss = 0V reference) Min. Max. 4.5 (3.0) 5.5 3.5 (2.7) 5.5 2.0 5.5 VIH 0.7VDD VDD V VIHS 0.8VDD VDD V VIHEX 0.9VDD VDD + 0.3 V Hysteresis input∗3 EXTAL∗4 VIL 0 0.3VDD V ∗2 VILS 0 0.2VDD V VILEX –0.3 0.1VDD V Topr –20 +75 °C VDD Unit Remarks Guaranteed operation range for 1/2 and 1/4 frequency dividing clocks V Guaranteed operation range for 1/16 frequency dividing clock and sleep mode Guaranteed data hold range during stop mode ∗2 Hysteresis input∗3 EXTAL∗4 Specifies values in parenthesis for 1 to 20MHz system clock operation. Normal input ports (PA, PB0, PB4, PB7, PC, PE0 to PE3, PD, PF to PH, PI4 to PI7) RST, CINT, CS0, SCK0, SCK1, EC0, EC1, SI0, SI1, NMI, INT0, INT1, INT2, INT3 Specifies only during external clock input. – 12 – CXP84540/84548 Electrical Characteristics DC Characteristics (VDD 4.5 to 5.5V) Item High level output voltage Low level output voltage Symbol VOH VOL Pins EXTAL IILE Input current I/O leakage current IILR RST∗2 IIL PA to PD∗3 PF to PI∗3 IIZ PA to PD∗3 PF to PI∗3 PE0 to PE3, RST∗2 IDD1 Typ. Max. Unit 4.0 V 3.5 V VDD = 4.5V, IOL = 12.0mA 0.4 V 0.6 V 1.5 V VDD = 5.5V, VIH = 5.5V 0.1 25 µA VDD = 5.5V, VIL = 0.4V –0.1 –25 µA –1.5 –400 µA –50 µA VDD = 5.5V, VIL = 4.0V VDD = 4.5V, VIL = 4.0V –2.78 µA VDD = 5.5V, VI = 0, 5.5V VDD = 5.5V, 28MHz crystal oscillation (C1 = C2 = 5pF) ±10 µA 28 58 mA 4.0 10 mA 10 µA 20 pF Sleep mode IDDS1 IDDS2 Min. 1/2 frequency dividing clock operation IDD2 Supply current ∗4 Conditions VDD = 4.5V, IOH = –0.5mA PA to PD, VDD = 4.5V, IOH = –1.2mA PE4 to PE7, PF to PI, VDD = 4.5V, IOL = 1.8mA RST (only VOL)∗1 VDD = 4.5V, IOL = 3.6mA PC IIHE (Ta = –20 to +75°C, Vss = 0V reference) VDD VDD = 5.5V, 28MHz crystal oscillation (C1 = C2 = 5pF) Stop mode IDDS3 Input capacity CIN VDD = 5.5V, termination of 28MHz crystal oscillation PA to PD, PE0 to PE3, PF to PI, EXTAL, RST Clock 1MHz 0V for no-measured pins 10 ∗1 Specifies RST pin when the power-on reset circuit is selected with mask option. ∗2 For RST pin, specifies the input current when pull-up resistance is selected; leakage current when no resistance is selected. ∗3 For PA to PD and PF to PI pins, specifies the input current when pull-up resistance is selected; leakage current when no resistance is selected. ∗4 When all pins are open. – 13 – CXP84540/84548 DC Characteristics (VDD = 3.0 to 3.6V) Item High level output voltage Low level output voltage Symbol VOH VOL Pins IIHE Input current I/O leakage current IILR EXTAL RST∗2 IIL PA to PD∗3 PF to PI∗3 IIZ PA to PD∗3 PF to PI∗3 PE0 to PE3, RST∗2 Typ. Max. Unit 2.7 V 2.3 V VDD = 3.0V, IOL = 5mA 0.3 V 0.5 V 1.0 V VDD = 3.6V, VIH = 3.6V 0.05 15 µA VDD = 3.6V, VIL = 0.3V –0.05 –15 µA –0.7 –200 µA –30 µA VDD = 3.6V, VIL = 2.7V VDD = 3.0V, VIL = 2.7V –1.0 µA VDD = 3.6V, VI = 0, 3.6V VDD = 3.6V, 20MHz crystal oscillation (C1 = C2 = 10pF) IDD2 ±5 µA 13.5 30 mA 1.2 4.0 mA 5 µA Sleep mode IDDS1 IDDS2 Min. 1/2 frequency dividing clock operation IDD1 Supply current∗4 Conditions VDD = 3.0V, IOH = –0.15mA PA to PD, VDD = 3.0V, IOH = –0.5mA PE4 to PE7, PF to PI, VDD = 3.0V, IOL = 1.2mA RST (only VOL)∗1 VDD = 3.0V, IOL = 1.6mA PC IILE (Ta = –20 to +75°C, VSS = 0V reference) VDD VDD = 3.6V, 20MHz crystal oscillation (C1 = C2 = 10pF) Stop mode IDDS3 VDD = 3.6V, termination of 20MHz crystal oscillation ∗1 Specifies RST pin when the power-on reset circuit is selected with mask option. ∗2 For RST pin, specifies the input current when pull-up resistance is selected; leakage current when no resistance is selected. ∗3 For PA to PD and PF to PI pins, specifies the input current when pull-up resistance is selected; leakage current when no resistance is selected. ∗4 When all pins are open. – 14 – CXP84540/84548 AC Characteristics (Ta = –20 to +75°C, VDD = 3.0 to 5.5V, Vss = 0V reference) (1) Clock timing Item Symbol Pin Conditions System clock frequency fC VDD = 4.5 to 5.5V XTAL Fig. 1, Fig. 2 EXTAL System clock input pulse width tXL, tXH EXTAL Fig. 1, Fig. 2 VDD = 4.5 to 5.5V External clock drive EXTAL Fig. 1, Fig. 2 External clock drive EC0 EC1 Fig. 3 EC0 EC1 Fig. 3 tCR, tCF tEH, tEL tER, tEF System clock input rise time, fall time Event count input clock pulse width Event count input clock rise time, fall time Min. Typ. Max. Unit 1 28 1 20 MHz 15.6 ns 23 100 tsys + 50∗1 ns ns 20 ns ∗1 tsys indicates three values according to the contents of the clock control register (CLC: 00FEH) upper 2 bits (CPU clock selection). tsys (ns) = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11") Fig. 1. Clock timing 1/fc VDD – 0.4V EXTAL 0.4V tXH tCF tXL tCR Fig. 2. Clock applied conditions AAAA AAAA AAAA AAAA AAAA AAAA Crystal oscillation Ceramic oscillation EXTAL External clock EXTAL XTAL C1 C2 XTAL 74HC04 Fig. 3. Event count clock timing 0.8VDD EC0 EC1 0.2VDD tEH tTH tEF tTF – 15 – tEL tTL tER tTR CXP84540/84548 (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) (2) Serial transfer (CH0) Item Symbol Pin Condition Min. Max. Unit CS0 ↓ → SCK0 delay time tDCSK SCK0 Chip select transfer mode (SCK0 = output mode) 1.5tsys + 100 ns CS0 ↑ → SCK0 float delay time tDCSKF SCK0 Chip select transfer mode (SCK0 = output mode) 1.5tsys + 100 ns CS0 ↓ → SO0 delay time tDCSO SO0 Chip select transfer mode 1.5tsys + 100 ns CS0 ↑ → SO0 float delay time tDCSOF SO0 Chip select transfer mode 1.5tsys + 100 ns CS0 High level width tWHCS CS0 Chip select transfer mode SCK0 cycle time tKCY SCK0 SCK0 High, Low level widths tKH tKL SCK0 SI0 input setup time (for SCK0 ↑) tSIK SI0 SI0 input hold time (for SCK0 ↑) tKSI SI0 SCK0 ↓ → SO0 delay time tKSO SO0 SCK0 ↓ → LAT0 output delay time tLADLY LAT0 Latch output mode (SCK0 = output mode) LAT0 data pulse width tLAPLS LAT0 Latch output mode (SCK0 = output mode) tsys + 150 2tsys + 200 ns 8000/fc ns tsys + 90 ns 4000/fc – 25 ns SCK0 input mode 50 ns SCK0 output mode 100 ns tsys + 100 ns 50 ns Input mode Output mode Input mode Output mode SCK0 input mode SCK0 output mode ns tsys + 100 ns 50 ns tKCY tKCY + 50 ns tKCY – 10 tKCY + 50 ns SCK0 input mode SCK0 output mode Note 1) tsys indicates three values according to the ccontents of the clock control register (CLC: 00FEH) upper 2 bits (CPU clock selection). tsys (ns) = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11") Note 2) The load condition for the SCK0 output mode, SO0 output delay time is 50pF + 1TTL. – 16 – CXP84540/84548 (Ta = –20 to +75°C, VDD = 3.0 to 3.6V, Vss = 0V reference) Serial transfer (CH0) Item Symbol Pin Condition CS0 ↓ → SCK0 delay time tDCSK SCK0 CS0 ↑ → SCK0 float delay time Min. Max. Unit Chip select transfer mode (SCK0 = output mode) 1.5tsys + 200 ns tDCSKF SCK0 Chip select transfer mode (SCK0 = output mode) 1.5tsys + 200 ns CS0 ↓ → SO0 delay time tDCSO SO0 Chip select transfer mode 1.5tsys + 200 ns CS0 ↑ → SO0 float delay time tDCSOF SO0 Chip select transfer mode 1.5tsys + 200 ns CS0 High level width tWHCS CS0 Chip select transfer mode SCK0 cycle time tKCY SCK0 SCK0 High, Low level widths tKH tKL SCK0 SI0 input setup time (for SCK0 ↑) tSIK SI0 SI0 input hold time (for SCK0 ↑) tKSI SI0 SCK0 ↓ → SO0 delay time tKSO SO0 SCK0 ↓ → LAT0 output delay time tLADLY LAT0 Latch output mode (SCK0 = output mode) LAT0 data pulse width tLAPLS LAT0 Latch output mode (SCK0 = output mode) tsys + 200 2tsys + 200 ns 8000/fc ns tsys + 80 ns 4000/fc – 50 ns SCK0 input mode 80 ns SCK0 output mode 150 ns tsys + 120 ns 70 ns Input mode Output mode Input mode Output mode SCK0 input mode SCK0 output mode ns tsys + 200 ns 80 ns tKCY tKCY + 100 ns tKCY – 10 tKCY + 100 ns SCK0 input mode SCK0 output mode Note 1) tsys indicates three values according to the contents of the clock control register (CLC: 00FEH) upper 2 bits (CPU clock selection). tsys (ns) = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11") Note 2) The load condition for the SCK0 output mode, SO0 output delay time is 50pF + 1TTL. – 17 – CXP84540/84548 Fig. 4. Serial transfer CH0 timing tWHCS 0.8VDD CS0 0.2VDD tKCY tDCSK tKL tDCSKF tKH 0.8VDD 0.8VDD 0.8VDD SCK0 0.2VDD tSIK tKSI 0.8VDD Input data SI0 0.2VDD tDCSO tKSO tDCSOF 0.8VDD SO0 Output data 0.2VDD tLADLY 0.8VDD LAT0 – 18 – tLAPLS 0.8VDD CXP84540/84548 (3) Serial transfer (CH1) Item (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, VSS = 0V reference) Symbol Pin tKCY SCK1 SCK1 High, Low level widths tKH tKL SCK1 SI1 input set-up time (for SCK1 ↑) tSIK SI1 SI1 input hold time (for SCK1 ↑) tKSI SI1 SCK1 ↓ → SO1 delay time tKSO SO1 SCK1 cycle time Condition Min. Max. Unit 500 ns 8000/fc ns 200 ns 4000/fc – 25 ns SCK1 input mode 50 ns SCK1 output mode 100 ns SCK1 input mode 100 ns SCK1 output mode 50 ns Input mode Output mode Input mode Output mode SCK1 input mode 100 ns SCK1 output mode 50 ns Note) The load condition for the SCK1 output mode, SO1 output delay time is 50pF + 1TTL. (Ta = –20 to +75°C, VDD = 3.0 to 3.6V, VSS = 0V reference) Item SCK1 cycle time Symbol tKCY Pin SCK1 SCK1 High, Low level widths tKH tKL SCK1 SI1 input set-up time (for SCK1 ↑) tSIK SI1 SI1 input hold time (for SCK1 ↑) tKSI SCK1 ↓ → SO1 delay time tKSO SI1 SO1 Condition Min. Max. Unit 700 ns 8000/fc ns 300 ns 4000/fc – 50 ns SCK1 input mode 70 ns SCK1 output mode 150 ns SCK1 input mode 150 ns SCK1 output mode 70 ns Input mode Output mode Input mode Output mode SCK1 input mode 150 ns SCK1 output mode 80 ns Note) The load condition for the SCK1 output mode, SO1 output delay time is 50pF. – 19 – CXP84540/84548 Fig. 5. Serial transfer CH1 timing tKCY tKL tKH 0.8VDD SCK1 0.2VDD tSIK tKSI 0.8VDD Input data SI1 0.2VDD tKSO 0.8VDD SO1 Output data 0.2VDD – 20 – CXP84540/84548 (4) A/D converter characteristics (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, AVREF = 4.0 to VDD, Vss = AVSS = 0V reference) Item Symbol Pin Condition Min. Typ. Resolution Linearity error Zero transition voltage VZT∗1 Full-scale transition voltage VFT∗2 Conversion time tCONV tSAMP Sampling time Ta = 25°C VDD = AVREF = 5.0V VSS = AVSS = 0V AVREF Analog input voltage AN0 to AN7 IREFS 8 Bits ±4 LSB –10 10 70 mV 4910 4970 5030 mV AVREF µs µs VDD – 0.5 VDD V 0 AVREF V 1.0 mA 10 µA 0.6 Operation mode IREF AVREF current Unit 27/fADC∗3 6/fADC∗3 Reference input voltage VREF VIAN Max. Sleep mode Stop mode (Ta = –20 to +75°C, VDD = 3.0 to 3.6V, AVREF = 2.7 to VDD, Vss = AVSS = 0V reference) Item Symbol Pin Condition Min. Typ. Resolution Linearity error Zero transition voltage VZT∗1 Full-scale transition voltage VFT∗2 Conversion time tCONV tSAMP Sampling time Ta = 25°C VDD = AVREF = 3.3V VSS = AVSS = 0V AVREF Analog input voltage AN0 to AN7 Operation mode IREF AVREF current IREFS Unit 8 Bits ±5 LSB –10 6.5 70 mV 3216 3280.5 3345 mV 27/fADC∗3 6/fADC∗3 Reference input voltage VREF VIAN Max. AVREF Sleep mode Stop mode µs µs VDD – 0.3 VDD V 0 AVREF V 0.7 mA 5 µA 0.4 Fig. 6. Definition of A/D converter terms ∗1 VZT: Value at which the digital conversion value changes from 00H to 01H and vice versa. ∗2 VFT: Value at which the digital conversion value changes from FEH to FFH and vice versa. ∗3 fADC indicates the values below due to the contents of bit 6 (CKS) of the A/D control register (ADC: 00F9H). fADC = fc (CKS = "0"), fc/2 (CKS = "1") However, the selection for fADC = fc (CKS = "0") is limited in the clock range of fc = 1 to 14MHz (VDD 4.5 to 5.5V) and fc = 1 to 10MHz (VDD = 3.0 to 4.5V). Digital conversion value FFH FEH Linearity error 01H 00H VFT VZT Analog input – 21 – CXP84540/84548 (4) Interruption, reset input (Ta = –20 to +75°C, VDD = 3.0 to 5.5V, Vss = 0V reference) Item Symbol Pin External interruption High, Low level widths tIH tIL INT0 INT1 INT2 INT3 NMI Reset input Low level width tRSL RST Condition Min. Max. Unit 1 µs 32/fc µs Fig 7. Interruption input timing tIH tIL 0.8VDD INT0 INT1 INT2 INT3 NMI (Specifies NMI only for the falling edge.) 0.2VDD tIL tIH 0.8VDD 0.2VDD Fig. 8. RST input timing tRSL RST 0.2VDD (5) Power-on reset∗1 (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, VSS = 0V reference) Item Symbol tR tOFF Power supply rise time Power supply cut-off time Pin VDD Condition Power-on reset Min. Max. Unit 0.05 50 ms 1 Repetitive power-on reset ∗1 Specifies only when the power-on reset function is selected. Power-on reset function can be selected only for the supply voltage range of 4.5 to 5.5V. Fig. 9. Power-on reset 4.5V VDD 0.2V 0.2V tR tOFF Take care when turning the power on. – 22 – ms CXP84540/84548 Appendix Fig. 10. SPC700 Series recommended oscillation circuit AAAA AAAA AAAA AAAA AAAA AAAA (i) Main clock EXTAL (ii) Main clock EXTAL XTAL Rd Rd C1 XTAL C2 C 1 C2 Manufacturer MURATA MFG CO., LTD. Model CSA8.00MTZ 8.00 CSA10.0MTZ 10.00 CSA12.00MTZ CST8.00MTW∗ 12.00 C2 (pF) Rd (Ω) Circuit example (i) 30 30 0 8.00 CST10.0MT∗ 10.00 CST12.0MTW∗ 12.00 (ii) CSA16.00MXZ040 CST16.00MXZ0C1∗ 16.00 5 5 0 (i) 16.00 5 5 0 (ii) CSA20.00MXZ040 20.00 OPEN OPEN 0 CSA24.00MXZ040 24.00 3 3 0 CSA28.00MXZ040 CCR20.0MC6∗ 28.00 3 3 0 20.00 16 16 0 24.00 16 16 0 HC49/U-S 28.00 1 1 220 CX-11F 28.00 1 1 220 TDK CORPORATION. CCR24.0MC6∗ KINSEKI LTD. C1 (pF) fc (MHz) (i) (ii) (i) Models with an asterisk (∗) have the built-in ground capacitance (C1, C2). Mask option table Item Reset pin pull-up resistor Power-on reset circuit ∗1 Contents Non-existent Existent Non-existent Existent ∗1 "Existent" for power-on reset circuit cannot be selected when the supply voltage VDD of 3.0 to 4.5V. – 23 – CXP84540/84548 Characteristics Curves IDD vs. fc (VDD = 5V, Ta = 25°C, Typical) IDD vs. VDD (fc = 28MHz, Ta = 25°C, Typical) 10.0 1/16 dividing mode 20 Sleep mode IDD – Supply current [mA] 5.0 IDD – Supply current [mA] 1/2 dividing mode 1/2 dividing mode 1/4 dividing mode 20.0 1.0 0.5 0.1 (100µA) 0.05 (50µA) 15 1/4 dividing mode 10 Stop mode 1/16 dividing mode 5 Sleep mode 0.01 (10µA) 2 3 4 5 6 10 20 fc – System clock [MHz] IDD vs. VDD (fc = 20MHz, Ta = 25°C, Typical) IDD vs. fc (VDD = 3.3V, Ta = 25°C, Typical) 20.0 0 30 1/2 dividing mode 1/4 dividing mode 10.0 20 Sleep mode 1.0 0.5 0.1 (100µA) 0.05 (50µA) IDD – Supply current [mA] 1/16 dividing mode 5.0 IDD – Supply current [mA] 7 VDD – Supply voltage [V] 15 1/2 dividing mode 10 1/4 dividing mode 5 1/16 dividing mode 0.01 (10µA) Sleep mode 2 3 4 5 6 7 0 VDD – Supply voltage [V] – 24 – 10 20 fc – System clock [MHz] 30 CXP84540/84548 Unit: mm 80PIN QFP (PLASTIC) 23.9 ± 0.4 + 0.1 0.15 – 0.05 + 0.4 20.0 – 0.1 64 0.15 41 65 16.3 + 0.4 14.0 – 0.1 17.9 ± 0.4 40 A 80 + 0.2 0.1 – 0.05 1 24 0.8 0.12 + 0.15 0.35 – 0.1 M 0.8 ± 0.2 25 + 0.35 2.75 – 0.15 0° to 10° DETAIL A PACKAGE STRUCTURE SONY CODE QFP-80P-L01 EIAJ CODE ∗QFP080-P-1420-A JEDEC CODE PACKAGE MATERIAL EPOXY RESIN LEAD TREATMENT SOLDER PLATING LEAD MATERIAL COPPER / 42 ALLOY PACKAGE WEIGHT 1.6g 80PIN LQFP (PLASTIC) 14.0 ± 0.2 ∗ 12.0 ± 0.1 60 41 40 (13.0) 61 21 (0.22) 80 0.5 0.5 ± 0.2 A 1 + 0.08 0.18 – 0.03 20 0.13 M + 0.2 1.5 – 0.1 + 0.05 0.127 – 0.02 0.1 0.1 ± 0.1 0° to 10° 0.5 ± 0.2 Package Outline NOTE: Dimension “∗” does not include mold protrusion. DETAIL A PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SONY CODE LQFP-80P-L01 LEAD TREATMENT SOLDER PLATING EIAJ CODE LQFP080-P-1212 LEAD MATERIAL 42 ALLOY PACKAGE MASS 0.5g JEDEC CODE – 25 –