CYPRESS CY7C1354CV25

CY7C1354CV25
CY7C1356CV25
9-Mbit (256K x 36/512K x 18)
Pipelined SRAM with NoBL™ Architecture
Functional Description[1]
Features
• Pin-compatible with and functionally equivalent to
ZBT™
The CY7C1354CV25 and CY7C1356CV25 are 2.5V, 256K x
36 and 512K x 18 Synchronous pipelined burst SRAMs with
No Bus Latency™ (NoBL™) logic, respectively. They are
designed to support unlimited true back-to-back Read/Write
operations with no wait states. The CY7C1354CV25 and
CY7C1356CV25 are equipped with the advanced (NoBL) logic
required to enable consecutive Read/Write operations with
data being transferred on every clock cycle. This feature
dramatically improves the throughput of data in systems that
require frequent Write/Read transitions. The CY7C1354CV25
and CY7C1356CV25 are pin-compatible with and functionally
equivalent to ZBT devices.
• Supports 250-MHz bus operations with zero wait states
• Available speed grades are 250, 200, and 166 MHz
• Internally self-timed output buffer control to eliminate
the need to use asynchronous OE
• Fully registered (inputs and outputs) for pipelined
operation
• Byte Write capability
• Single 2.5V power supply (VDD)
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. The
clock input is qualified by the Clock Enable (CEN) signal,
which when deasserted suspends operation and extends the
previous clock cycle.
• Fast clock-to-output times
— 2.8 ns (for 250-MHz device)
• Clock Enable (CEN) pin to suspend operation
• Synchronous self-timed writes
• Available in lead-free 100-Pin TQFP package, lead-free
and non lead-free 119-Ball BGA package and 165-Ball
FBGA package
Write operations are controlled by the Byte Write Selects
(BWa–BWd for CY7C1354CV25 and BWa–BWb for
CY7C1356CV25) and a Write Enable (WE) input. All writes are
conducted with on-chip synchronous self-timed write circuitry.
• IEEE 1149.1 JTAG-Compatible Boundary Scan
• Burst capability–linear or interleaved burst order
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. In order to avoid bus
contention, the output drivers are synchronously tri-stated
during the data portion of a write sequence.
• “ZZ” Sleep Mode option and Stop Clock option
Logic Block Diagram–CY7C1354CV25 (256K x 36)
ADDRESS
REGISTER 0
A0, A1, A
A1
A1'
D1
Q1
A0
A0'
BURST
D0
Q0
LOGIC
MODE
CLK
CEN
ADV/LD
C
C
WRITE ADDRESS
REGISTER 1
WRITE ADDRESS
REGISTER 2
ADV/LD
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
BWa
BWb
BWc
BWd
WRITE
DRIVERS
MEMORY
ARRAY
WE
S
E
N
S
E
A
M
P
S
O
U
T
P
U
T
R
E
G
I
S
T
E
R
S
E
INPUT
REGISTER 1 E
OE
CE1
CE2
CE3
ZZ
D
A
T
A
S
T
E
E
R
I
N
G
O
U
T
P
U
T
B
U
F
F
E
R
S
DQs
DQPa
DQPb
DQPc
DQPd
E
INPUT
REGISTER 0 E
READ LOGIC
SLEEP
CONTROL
Note:
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05537 Rev. *H
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised September 14, 2006
[+] Feedback
CY7C1354CV25
CY7C1356CV25
Logic Block Diagram–CY7C1356CV25 (512K x 18)
A0, A1, A
ADDRESS
REGISTER 0
A1
A1'
D1
Q1
A0
A0'
BURST
D0
Q0
LOGIC
MODE
CLK
CEN
ADV/LD
C
C
WRITE ADDRESS
REGISTER 1
WRITE ADDRESS
REGISTER 2
ADV/LD
BWa
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
MEMORY
ARRAY
BWb
S
E
N
S
E
A
M
P
S
WE
O
U
T
P
U
T
R
E
G
I
S
T
E
R
S
D
A
T
A
S
T
E
E
R
I
N
G
E
INPUT
REGISTER 1 E
OE
CE1
CE2
CE3
ZZ
O
U
T
P
U
T
B
U
F
F
E
R
S
DQs
DQPa
DQPb
E
INPUT
REGISTER 0 E
READ LOGIC
Sleep
Control
Selection Guide
250 MHz
200 MHz
166 MHz
Unit
Maximum Access Time
2.8
3.2
3.5
ns
Maximum Operating Current
250
220
180
mA
Maximum CMOS Standby Current
40
40
40
mA
Document #: 38-05537 Rev. *H
Page 2 of 28
[+] Feedback
CY7C1354CV25
CY7C1356CV25
Pin Configurations
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
CY7C1356CV25
(512K × 18)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A
NC
NC
VDDQ
VSS
NC
DQPa
DQa
DQa
VSS
VDDQ
DQa
DQa
VSS
NC
VDD
ZZ
DQa
DQa
VDDQ
VSS
DQa
DQa
NC
NC
VSS
VDDQ
NC
NC
NC
A
A
A
A
A
A
A
NC(72M)
NC(36M)
VSS
VDD
NC(288M)
NC(144M)
A
A
A
A
A
A
A
NC(72M)
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
NC
DQPb
NC
DQb
NC
DQb
VDDQ VDDQ
VSS
VSS
NC
DQb
DQb
NC
DQb
DQb
DQb
DQb
VSS
VSS
VDDQ VDDQ
DQb
DQb
DQb
DQb
NC
VSS
VDD
NC
VDD
NC
VSS
ZZ
DQb
DQa
DQa
DQb
VDDQ VDDQ
VSS
VSS
DQa
DQb
DQa
DQb
DQa DQPb
DQa
NC
VSS
VSS
VDDQ VDDQ
NC
DQa
DQa
NC
DQPa
NC
MODE
A
A
A
A
A1
A0
Document #: 38-05537 Rev. *H
NC(36M)
VSS
DQd
DQd
VDDQ
VSS
DQd
DQd
DQd
DQd
VSS
VDDQ
DQd
DQd
DQPd
VSS
VDD
NC
CY7C1354CV25
(256K × 36)
NC(288M)
NC(144M)
DQc
DQc
NC
VDD
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
VSS
DQc
DQc
DQc
DQc
VSS
VDDQ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
MODE
A
A
A
A
A1
A0
DQPc
DQc
DQc
VDDQ
A
A
A
A
CE1
CE2
NC
NC
BWb
BWa
CE3
VDD
VSS
CLK
WE
CEN
OE
ADV/LD
NC(18M)
A
A
A
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
A
A
CE1
CE2
BWd
BWc
BWb
BWa
CE3
VDD
VSS
CLK
WE
CEN
OE
ADV/LD
NC(18M)
A
100-pin TQFP Pinout
Page 3 of 28
[+] Feedback
CY7C1354CV25
CY7C1356CV25
Pin Configurations (continued)
119-Ball BGA Pinout
CY7C1354CV25 (256K × 36)
1
2
3
4
5
6
7
A
VDDQ
A
A
NC/18M
A
A
VDDQ
B
C
D
E
F
G
H
J
K
L
M
N
P
NC/576M
NC/1G
DQc
CE2
A
DQPc
A
A
VSS
ADV/LD
VDD
NC
A
A
VSS
CE3
A
DQPb
NC
NC
DQb
CE1
VSS
DQb
DQb
OE
A
VSS
DQb
VDDQ
BWb
DQb
DQb
WE
VDD
VSS
NC
DQb
VDD
DQb
VDDQ
CLK
NC
VSS
BWa
DQa
DQa
DQa
DQa
R
T
U
DQc
DQc
VSS
VDDQ
DQc
VSS
DQc
DQc
DQc
VDDQ
DQc
VDD
BWc
VSS
NC
DQd
DQd
DQd
DQd
BWd
VDDQ
DQd
VSS
DQa
VDDQ
DQd
VSS
CEN
A1
VSS
DQd
VSS
DQa
DQa
DQd
DQPd
VSS
A0
VSS
DQPa
DQa
NC/144M
A
MODE
VDD
NC/288M
NC/72M
A
A
NC
A
A
NC
NC/36M
ZZ
VDDQ
TMS
TDI
TCK
TDO
NC
VDDQ
1
2
3
4
5
6
7
VDDQ
A
A
NC/18M
A
A
VDDQ
NC/576M
CE2
A
A
NC
A
VSS
ADV/LD
VDD
NC
A
NC/1G
DQb
A
VSS
CE3
A
DQPa
NC
NC
CE1
VSS
NC
DQa
OE
A
VSS
DQa
VDDQ
NC
DQa
VDD
DQa
NC
VDDQ
VSS
CY7C1356CV25 (512K x 18)
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
Document #: 38-05537 Rev. *H
NC
NC
DQb
VSS
VDDQ
NC
VSS
NC
DQb
VDDQ
DQb
NC
VDD
BWb
VSS
NC
WE
VDD
VSS
VSS
NC
VSS
NC
DQa
BWa
VSS
DQa
NC
NC
VDDQ
VSS
DQa
NC
NC
DQb
VSS
CLK
DQb
NC
VSS
NC
VDDQ
DQb
VSS
DQb
NC
VSS
CEN
A1
NC
DQPb
VSS
A0
VSS
NC
DQa
NC/144M
A
MODE
VDD
NC
A
NC/288M
NC/72M
A
A
NC/36M
A
A
ZZ
VDDQ
TMS
TDI
TCK
TDO
NC
VDDQ
Page 4 of 28
[+] Feedback
CY7C1354CV25
CY7C1356CV25
Pin Configurations (continued)
165-Ball FBGA Pinout
CY7C1354CV25 (256K × 36)
1
2
3
4
5
6
7
8
9
10
11
A
B
C
D
E
F
G
H
J
K
L
M
N
P
NC/576M
A
CE1
BWc
BWb
CE3
ADV/LD
A
A
NC
CLK
CEN
WE
OE
NC/18M
VSS
VSS
VSS
VDD
VDDQ
VDDQ
A
NC
DQb
DQPb
DQb
VDDQ
DQb
DQb
R
MODE
NC/1G
A
CE2
DQPc
DQc
NC
DQc
VDDQ
VDDQ
BWd
VSS
VDD
BWa
VSS
VSS
VSS
VSS
DQc
DQc
VDDQ
VDD
VSS
VSS
VSS
VDD
NC
DQc
DQc
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQb
DQb
DQc
NC
DQd
DQc
NC
DQd
VDDQ
NC
VDDQ
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDDQ
VDDQ
DQb
NC
DQa
DQb
ZZ
DQa
DQd
DQd
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
DQa
DQd
DQd
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
DQa
DQd
DQPd
DQd
NC
VDDQ
VDDQ
VDD
VSS
VSS
NC
VSS
NC
VSS
NC
VDD
VSS
VDDQ
VDDQ
DQa
NC
DQa
DQPa
A
A
TDI
A1
TDO
A
A
A
NC/288M
A
A
TMS
A0
TCK
A
A
A
A
NC/144M NC/72M
NC/36M
NC
CY7C1356CV25 (512K × 18)
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
1
2
3
4
5
6
7
8
9
10
11
NC/576M
A
CE1
BWb
NC
CE3
CEN
ADV/LD
A
A
A
NC/1G
A
CE2
NC
BWa
CLK
NC
DQb
VDDQ
VDDQ
VSS
VDD
VSS
VSS
VSS
VSS
WE
VSS
VSS
OE
VSS
VDD
NC/18M
NC
NC
VDDQ
VDDQ
A
NC
NC
DQPa
DQa
NC
DQb
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
DQa
NC
DQb
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
DQa
NC
NC
DQb
DQb
NC
NC
VDDQ
NC
VDDQ
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDDQ
VDDQ
NC
NC
DQa
DQa
ZZ
NC
DQb
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
NC
DQb
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
NC
DQb
DQPb
NC
NC
VDDQ
VDDQ
VDD
VSS
VSS
NC
VSS
NC
VSS
NC
VDD
VSS
VDDQ
VDDQ
DQa
NC
NC
NC
A
A
TDI
A1
TDO
A
A
A
A
A
TMS
A0
TCK
A
A
A
NC/144M NC/72M
MODE
NC/36M
Document #: 38-05537 Rev. *H
NC
NC
NC/288M
A
Page 5 of 28
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CY7C1354CV25
CY7C1356CV25
Pin Definitions
Pin Name
I/O Type
Pin Description
A0
A1
A
InputSynchronous
Address Inputs used to select one of the address locations. Sampled at the rising edge of
the CLK.
BWa,BWb,
BWc,BWd,
InputSynchronous
Byte Write Select Inputs, active LOW. Qualified with WE to conduct writes to the SRAM.
Sampled on the rising edge of CLK. BWa controls DQa and DQPa, BWb controls DQb and DQPb,
BWc controls DQc and DQPc, BWd controls DQd and DQPd.
WE
InputSynchronous
Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This
signal must be asserted LOW to initiate a write sequence.
ADV/LD
InputSynchronous
Advance/Load Input used to advance the on-chip address counter or load a new address.
When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a
new address can be loaded into the device for an access. After being deselected, ADV/LD should
be driven LOW in order to load a new address.
CLK
InputClock
Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN.
CLK is only recognized if CEN is active LOW.
CE1
InputSynchronous
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE2 and CE3 to select/deselect the device.
CE2
InputSynchronous
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with
CE1 and CE3 to select/deselect the device.
CE3
InputSynchronous
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE1 and CE2 to select/deselect the device.
OE
InputAsynchronous
Output Enable, active LOW. Combined with the synchronous logic block inside the device to
control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs.
When deasserted HIGH, I/O pins are tri-stated, and act as input data pins. OE is masked during
the data portion of a Write sequence, during the first clock when emerging from a deselected state
and when the device has been deselected.
CEN
InputSynchronous
Clock Enable Input, active LOW. When asserted LOW the clock signal is recognized by the
SRAM. When deasserted HIGH the clock signal is masked. Since deasserting CEN does not
deselect the device, CEN can be used to extend the previous cycle when required.
DQS
I/OSynchronous
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered
by the rising edge of CLK. As outputs, they deliver the data contained in the memory location
specified by addresses during the previous clock rise of the Read cycle. The direction of the pins
is controlled by OE and the internal control logic. When OE is asserted LOW, the pins can behave
as outputs. When HIGH, DQa–DQd are placed in a tri-state condition. The outputs are automatically tri-stated during the data portion of a write sequence, during the first clock when emerging
from a deselected state, and when the device is deselected, regardless of the state of OE.
DQPX
I/OSynchronous
Bidirectional Data Parity I/O lines. Functionally, these signals are identical to DQ[a:d]. During
write sequences, DQPa is controlled by BWa, DQPb is controlled by BWb, DQPc is controlled by
BWc, and DQPd is controlled by BWd.
MODE
Input Strap Pin
Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved burst order.
Pulled LOW selects the linear burst order. MODE should not change states during operation.
When left floating MODE will default HIGH, to an interleaved burst order.
TDO
JTAG serial output Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK.
Synchronous
TDI
JTAG serial input Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK.
Synchronous
TMS
Test Mode Select This pin controls the Test Access Port state machine. Sampled on the rising edge of TCK.
Synchronous
TCK
JTAG-Clock
VDD
Power Supply
VDDQ
VSS
Clock input to the JTAG circuitry.
Power supply inputs to the core of the device.
I/O Power Supply Power supply for the I/O circuitry.
Ground
Document #: 38-05537 Rev. *H
Ground for the device. Should be connected to ground of the system.
Page 6 of 28
[+] Feedback
CY7C1354CV25
CY7C1356CV25
Pin Definitions (continued)
Pin Name
I/O Type
Pin Description
NC
–
No connects. This pin is not connected to the die.
NC (18,
36, 72,
144, 288,
576, 1G
–
These pins are not connected. They will be used for expansion to the 18M, 36M, 72M, 144M
288M, 576M, and 1G densities.
InputAsynchronous
ZZ “sleep” Input. This active HIGH input places the device in a non-time critical “sleep” condition
with data integrity preserved. For normal operation, this pin has to be LOW or left floating.
ZZ pin has an internal pull-down.
ZZ
Functional Overview
The
CY7C1354CV25
and
CY7C1356CV25
are
synchronous-pipelined Burst NoBL SRAMs designed specifically to eliminate wait states during Write/Read transitions. All
synchronous inputs pass through input registers controlled by
the rising edge of the clock. The clock signal is qualified with
the Clock Enable input signal (CEN). If CEN is HIGH, the clock
signal is not recognized and all internal states are maintained.
All synchronous operations are qualified with CEN. All data
outputs pass through output registers controlled by the rising
edge of the clock. Maximum access delay from the clock rise
(tCO) is 2.8 ns (250-MHz device).
Accesses can be initiated by asserting all three Chip Enables
(CE1, CE2, CE3) active at the rising edge of the clock. If Clock
Enable (CEN) is active LOW and ADV/LD is asserted LOW,
the address presented to the device will be latched. The
access can either be a Read or Write operation, depending on
the status of the Write Enable (WE). BW[d:a] can be used to
conduct Byte Write operations.
Write operations are qualified by the Write Enable (WE). All
Writes are simplified with on-chip synchronous self-timed
Write circuitry.
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) simplify depth expansion.
All operations (Reads, Writes, and Deselects) are pipelined.
ADV/LD should be driven LOW once the device has been
deselected in order to load a new address for the next
operation.
Single Read Accesses
A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are ALL asserted active, (3) the Write Enable input
signal WE is deasserted HIGH, and (4) ADV/LD is asserted
LOW. The address presented to the address inputs is latched
into the address register and presented to the memory core
and control logic. The control logic determines that a read
access is in progress and allows the requested data to
propagate to the input of the output register. At the rising edge
of the next clock the requested data is allowed to propagate
through the output register and onto the data bus within 2.8 ns
(250-MHz device) provided OE is active LOW. After the first
clock of the read access the output buffers are controlled by
OE and the internal control logic. OE must be driven LOW in
order for the device to drive out the requested data. During the
second clock, a subsequent operation (Read/Write/Deselect)
can be initiated. Deselecting the device is also pipelined.
Therefore, when the SRAM is deselected at clock rise by one
Document #: 38-05537 Rev. *H
of the chip enable signals, its output will tri-state following the
next clock rise.
Burst Read Accesses
The CY7C1354CV25 and CY7C1356CV25 have an on-chip
burst counter that allows the user the ability to supply a single
address and conduct up to four Reads without reasserting the
address inputs. ADV/LD must be driven LOW in order to load
a new address into the SRAM, as described in the Single Read
Access section above. The sequence of the burst counter is
determined by the MODE input signal. A LOW input on MODE
selects a linear burst mode, a HIGH selects an interleaved
burst sequence. Both burst counters use A0 and A1 in the
burst sequence, and will wrap around when incremented sufficiently. A HIGH input on ADV/LD will increment the internal
burst counter regardless of the state of chip enables inputs or
WE. WE is latched at the beginning of a burst cycle. Therefore,
the type of access (Read or Write) is maintained throughout
the burst sequence.
Single Write Accesses
Write access are initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are ALL asserted active, and (3) the Write signal WE
is asserted LOW. The address presented to A0∠A16 is loaded
into the Address Register. The write signals are latched into
the Control Logic block.
On the subsequent clock rise the data lines are automatically
tri-stated regardless of the state of the OE input signal. This
allows the external logic to present the data on DQ and DQP
(DQa,b,c,d/DQPa,b,c,d for CY7C1354CV25 and DQa,b/DQPa,b
for CY7C1356CV25). In addition, the address for the subsequent access (Read/Write/Deselect) is latched into the
address register (provided the appropriate control signals are
asserted).
On the next clock rise the data presented to DQ and DQP
(DQa,b,c,d/DQPa,b,c,d for CY7C1354CV25 and DQa,b/DQPa,b
for CY7C1356CV25) (or a subset for byte write operations,
see Write Cycle Description table for details) inputs is latched
into the device and the Write is complete.
The data written during the Write operation is controlled by BW
(BWa,b,c,d
for
CY7C1354CV25
and
BWa,b
for
CY7C1356CV25) signals. The CY7C1354CV25/56CV25
provides Byte Write capability that is described in the Write
Cycle Description table. Asserting the Write Enable input (WE)
with the selected Byte Write Select (BW) input will selectively
write to only the desired bytes. Bytes not selected during a
Byte Write operation will remain unaltered. A synchronous
self-timed write mechanism has been provided to simplify the
Write operations. Byte Write capability has been included in
Page 7 of 28
[+] Feedback
CY7C1354CV25
CY7C1356CV25
order to greatly simplify Read/Modify/Write sequences, which
can be reduced to simple Byte Write operations.
Because the CY7C1354CV25 and CY7C1356CV25 are
common I/O devices, data should not be driven into the device
while the outputs are active. The Output Enable (OE) can be
deasserted HIGH before presenting data to the DQ and DQP
(DQa,b,c,d/DQPa,b,c,d for CY7C1354CV25 and DQa,b/DQPa,b
for CY7C1356CV25) inputs. Doing so will tri-state the output
drivers. As a safety precaution, DQ and DQP
(DQa,b,c,d/DQPa,b,c,d for CY7C1354CV25 and DQa,b/DQPa,b
for CY7C1356CV25) are automatically tri-stated during the
data portion of a write cycle, regardless of the state of OE.
Burst Write Accesses
The CY7C1354CV25/56CV25 has an on-chip burst counter
that allows the user the ability to supply a single address and
conduct up to four WRITE operations without reasserting the
address inputs. ADV/LD must be driven LOW in order to load
the initial address, as described in the Single Write Access
section above. When ADV/LD is driven HIGH on the subsequent clock rise, the chip enables (CE1, CE2, and CE3) and
WE inputs are ignored and the burst counter is incremented.
The correct BW (BWa,b,c,d for CY7C1354CV25 and BWa,b for
CY7C1356CV25) inputs must be driven in each cycle of the
burst write in order to write the correct bytes of data.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE1, CE2, and CE3, must remain inactive for
the duration of tZZREC after the ZZ input returns LOW.
Interleaved Burst Address Table
(MODE = Floating or VDD)
First
Address
A1,A0
00
01
10
11
Second
Address
A1,A0
01
00
11
10
Third
Address
A1,A0
10
11
00
01
Fourth
Address
A1,A0
11
10
01
00
Linear Burst Address Table (MODE = GND)
First
Address
A1,A0
00
01
10
11
Second
Address
A1,A0
01
10
11
00
Third
Address
A1,A0
10
11
00
01
Fourth
Address
A1,A0
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
IDDZZ
tZZS
tZZREC
tZZI
tRZZI
Truth
Description
Sleep mode standby current
Device operation to ZZ
ZZ recovery time
ZZ active to sleep current
ZZ Inactive to exit sleep current
Test Conditions
ZZ > VDD − 0.2V
ZZ > VDD − 0.2V
ZZ < 0.2V
This parameter is sampled
This parameter is sampled
Min.
Max.
50
2tCYC
2tCYC
2tCYC
0
Unit
mA
ns
ns
ns
ns
Table[2, 3, 4, 5, 6, 7, 8]
Operation
Deselect Cycle
Continue Deselect Cycle
Read Cycle (Begin Burst)
Read Cycle (Continue Burst)
NOP/Dummy Read (Begin Burst)
Dummy Read (Continue Burst)
Write Cycle (Begin Burst)
Write Cycle (Continue Burst)
Address
Used
None
None
External
Next
External
Next
External
Next
CE ZZ
H
L
X
L
L
L
X
L
L
L
X
L
L
L
X
L
ADV/LD
L
H
L
H
L
H
L
H
WE
X
X
H
X
H
X
L
X
BWx
X
X
X
X
X
X
L
L
OE
X
X
L
L
H
H
X
X
CEN
L
L
L
L
L
L
L
L
CLK
DQ
L-H
Tri-State
L-H
Tri-State
L-H Data Out (Q)
L-H Data Out (Q)
L-H
Tri-State
L-H
Tri-State
L-H
Data In (D)
L-H
Data In (D)
Notes:
2. X = “Don’t Care”, H = Logic HIGH, L = Logic LOW, CE stands for ALL Chip Enables active. BWx = L signifies at least one Byte Write Select is active, BWx =
Valid signifies that the desired Byte Write Selects are asserted, see Write Cycle Description table for details.
3. Write is defined by WE and BWX. See Write Cycle Description table for details.
4. When a write cycle is detected, all I/Os are tri-stated, even during Byte Writes.
5. The DQ and DQP pins are controlled by the current cycle and the OE signal.
6. CEN = H inserts wait states.
7. Device will power-up deselected and the I/Os in a tri-state condition, regardless of OE.
8. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs and DQPX = Tri-state when OE
is inactive or when the device is deselected, and DQs = data when OE is active.
Document #: 38-05537 Rev. *H
Page 8 of 28
[+] Feedback
CY7C1354CV25
CY7C1356CV25
Truth Table[2, 3, 4, 5, 6, 7, 8]
Operation
NOP/WRITE ABORT (Begin Burst)
WRITE ABORT (Continue Burst)
IGNORE CLOCK EDGE (Stall)
SLEEP MODE
Address
Used
None
Next
Current
None
CE ZZ
L
L
X
L
X
L
X
H
ADV/LD
L
H
X
X
WE
L
X
X
X
BWx
H
H
X
X
OE
X
X
X
X
CEN
L
L
H
X
CLK
L-H
L-H
L-H
X
DQ
Tri-State
Tri-State
–
Tri-State
Partial Write Cycle Description[2, 3, 4, 9]
Function (CY7C1354CV25)
Read
WE
H
BWd
BWc
BWb
BWa
X
X
X
X
Write –No bytes written
L
H
H
H
H
Write Byte a– (DQa and DQPa)
L
H
H
H
L
Write Byte b – (DQb and DQPb)
L
H
H
L
H
Write Bytes b, a
L
H
H
L
L
Write Byte c – (DQc and DQPc)
L
H
L
H
H
Write Bytes c, a
L
H
L
H
L
Write Bytes c, b
L
H
L
L
H
Write Bytes c, b, a
L
H
L
L
L
Write Byte d – (DQd and DQPd)
L
L
H
H
H
Write Bytes d, a
L
L
H
H
L
Write Bytes d, b
L
L
H
L
H
Write Bytes d, b, a
L
L
H
L
L
Write Bytes d, c
L
L
L
H
H
Write Bytes d, c, a
L
L
L
H
L
Write Bytes d, c, b
L
L
L
L
H
Write All Bytes
L
L
L
L
L
Partial Write Cycle Description[2, 3, 4, 9]
WE
BWb
BWa
Read
Function (CY7C1356CV25)
H
x
x
Write – No Bytes Written
L
H
H
Write Byte a − (DQa and DQPa)
L
H
L
Write Byte b – (DQb and DQPb)
L
L
H
Write Both Bytes
L
L
L
Note:
9. Table only lists a partial listing of the byte write combinations. Any combination of BWX is valid. Appropriate write will be done based on which byte write is active.
Document #: 38-05537 Rev. *H
Page 9 of 28
[+] Feedback
CY7C1354CV25
CY7C1356CV25
IEEE 1149.1 Serial Boundary Scan (JTAG)
The ball is pulled up internally, resulting in a logic HIGH level.
The CY7C1354CV25/CY7C1356CV25 incorporates a serial
boundary scan test access port (TAP) in the BGA package
only. The TQFP package does not offer this functionality. This
part operates in accordance with IEEE Standard 1149.1-1900,
but doesn’t have the set of functions required for full 1149.1
compliance. These functions from the IEEE specification are
excluded because their inclusion places an added delay in the
critical speed path of the SRAM. Note the TAP controller
functions in a manner that does not conflict with the operation
of other devices using 1149.1 fully compliant TAPs. The TAP
operates using JEDEC-standard 2.5V I/O logic levels.
Test Data-In (TDI)
The CY7C1354CV25/CY7C1356CV25 contains a TAP
controller, instruction register, boundary scan register, bypass
register, and ID register.
Test Data-Out (TDO)
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternately
be connected to VDD through a pull-up resistor. TDO should be
left unconnected. Upon power-up, the device will come up in
a reset state which will not interfere with the operation of the
device.
TEST-LOGIC
RESET
0
RUN-TEST/
IDLE
The TDO output ball is used to serially clock data-out from the
registers. The output is active depending upon the current
state of the TAP state machine. The output changes on the
falling edge of TCK. TDO is connected to the least significant
bit (LSB) of any register. (See Tap Controller State Diagram.)
TAP Controller Block Diagram
0
Bypass Register
2 1 0
TDI
TAP Controller State Diagram[10]
1
The TDI ball is used to serially input information into the
registers and can be connected to the input of any of the
registers. The register between TDI and TDO is chosen by the
instruction that is loaded into the TAP instruction register. For
information on loading the instruction register, see TAP
Controller State Diagram. TDI is internally pulled up and can
be unconnected if the TAP is unused in an application. TDI is
connected to the most significant bit (MSB) of any register.
(See Tap Controller Block Diagram.)
Selection
Circuitry
Instruction Register
31 30 29 . . . 2 1 0
Selection
Circuitry
TDO
Identification Register
x . . . . . 2 1 0
0
1
SELECT
DR-SCAN
1
SELECT
IR-SCAN
0
1
CAPTURE-DR
CAPTURE-IR
TCK
0
SHIFT-DR
0
SHIFT-IR
1
0
TMS
TAP CONTROLLER
1
EXIT1-DR
1
EXIT1-IR
0
1
Performing a TAP Reset
0
PAUSE-DR
0
PAUSE-IR
1
0
1
EXIT2-DR
0
EXIT2-IR
1
1
UPDATE-DR
1
Boundary Scan Register
0
1
0
0
1
0
UPDATE-IR
1
0
Test Access Port (TAP)
Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs
are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.Test MODE SELECT (TMS)
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to
leave this ball unconnected if the TAP is not used.
A RESET is performed by forcing TMS HIGH (VDD) for five
rising edges of TCK. This RESET does not affect the operation
of the SRAM and may be performed while the SRAM is
operating.
At power-up, the TAP is reset internally to ensure that TDO
comes up in a High-Z state.
TAP Registers
Registers are connected between the TDI and TDO balls and
allow data to be scanned into and out of the SRAM test
circuitry. Only one register can be selected at a time through
the instruction register. Data is serially loaded into the TDI ball
on the rising edge of TCK. Data is output on the TDO ball on
the falling edge of TCK.
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the
TDI and TDO balls as shown in the Tap Controller Block
Diagram. Upon power-up, the instruction register is loaded
with the IDCODE instruction.
Note:
10. The 0/1 next to each state represents the value of TMS at the rising edge of the TCK.
Document #: 38-05537 Rev. *H
Page 10 of 28
[+] Feedback
CY7C1354CV25
CY7C1356CV25
It is also loaded with the IDCODE instruction if the controller is
placed in a reset state as described in the previous section.
When the TAP controller is in the Capture-IR state, the two
least significant bits are loaded with a binary “01” pattern to
allow for fault isolation of the board-level serial test data path.
Bypass Register
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register
to be connected between the TDI and TDO pins when the TAP
controller is in a Shift-DR state. The SAMPLE Z command puts
the output bus into a High-Z state until the next command is
given during the “Update IR” state.
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between the
TDI and TDO balls. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW
(VSS) when the BYPASS instruction is executed.
SAMPLE/PRELOAD
Boundary Scan Register
The user must be aware that the TAP controller clock can only
operate at a frequency up to 20 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because
there is a large difference in the clock frequencies, it is
possible that during the Capture-DR state, an input or output
will undergo a transition. The TAP may then try to capture a
signal while in transition (metastable state). This will not harm
the device, but there is no guarantee as to the value that will
be captured. Repeatable results may not be possible.
The boundary scan register is connected to all the input and
bidirectional balls on the SRAM.
The boundary scan register is loaded with the contents of the
RAM I/O ring when the TAP controller is in the Capture-DR
state and is then placed between the TDI and TDO balls when
the controller is moved to the Shift-DR state. The EXTEST,
SAMPLE/PRELOAD and SAMPLE Z instructions can be used
to capture the contents of the I/O ring.
The Boundary Scan Order tables show the order in which the
bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected
to TDI, and the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired
into the SRAM and can be shifted out when the TAP controller
is in the Shift-DR state. The ID register has a vendor code and
other information described in the Identification Register
Definitions table.
TAP Instruction Set
Overview
Eight different instructions are possible with the three bit
instruction register. All combinations are listed in the
Instruction Codes table. Three of these instructions are listed
as RESERVED and should not be used. The other five instructions are described in detail below.
Instructions are loaded into the TAP controller during the
Shift-IR state when the instruction register is placed between
TDI and TDO. During this state, instructions are shifted
through the instruction register through the TDI and TDO balls.
To execute the instruction once it is shifted in, the TAP
controller needs to be moved into the Update-IR state.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO balls and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state.
The IDCODE instruction is loaded into the instruction register
upon power-up or whenever the TAP controller is given a test
logic reset state.
Document #: 38-05537 Rev. *H
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and output pins is
captured in the boundary scan register.
To guarantee that the boundary scan register will capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller's capture set-up plus
hold times (tCS and tCH). The SRAM clock input might not be
captured correctly if there is no way in a design to stop (or
slow) the clock during a SAMPLE/PRELOAD instruction. If this
is an issue, it is still possible to capture all other signals and
simply ignore the value of the CK and CK# captured in the
boundary scan register.
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the
boundary scan register between the TDI and TDO pins.
PRELOAD allows an initial data pattern to be placed at the
latched parallel outputs of the boundary scan register cells
prior to the selection of another boundary scan test operation.
The shifting of data for the SAMPLE and PRELOAD phases
can occur concurrently when required—that is, while data
captured is shifted out, the preloaded data can be shifted in.
BYPASS
When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO pins. The
advantage of the BYPASS instruction is that it shortens the
boundary scan path when multiple devices are connected
together on a board.
EXTEST
The EXTEST instruction enables the preloaded data to be
driven out through the system output pins. This instruction also
selects the boundary scan register to be connected for serial
access between the TDI and TDO in the shift-DR controller
state.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
Page 11 of 28
[+] Feedback
CY7C1354CV25
CY7C1356CV25
TAP Timing
1
2
Test Clock
(TCK)
3
t TH
t TMSS
t TMSH
t TDIS
t TDIH
t
TL
4
5
6
t CYC
Test Mode Select
(TMS)
Test Data-In
(TDI)
t TDOV
t TDOX
Test Data-Out
(TDO)
DON’T CARE
UNDEFINED
TAP AC Switching Characteristics Over the Operating Range[11, 12]
Parameter
Description
Min.
Max.
Unit
Clock
tTCYC
TCK Clock Cycle Time
tTF
TCK Clock Frequency
tTH
TCK Clock HIGH Time
20
ns
tTL
TCK Clock LOW Time
20
ns
50
ns
20
MHz
Output Times
tTDOV
TCK Clock LOW to TDO Valid
tTDOX
TCK Clock LOW to TDO Invalid
10
ns
0
ns
Set-up Times
tTMSS
TMS Set-up to TCK Clock Rise
5
ns
tTDIS
TDI Set-up to TCK Clock Rise
5
ns
tCS
Capture Set-up to TCK Rise
5
ns
tTMSH
TMS Hold after TCK Clock Rise
5
ns
tTDIH
TDI Hold after Clock Rise
5
ns
tCH
Capture Hold after Clock Rise
5
ns
Hold Times
Notes:
11. tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register.
12. Test conditions are specified using the load in TAP AC test Conditions. tR/tF = 1 ns.
Document #: 38-05537 Rev. *H
Page 12 of 28
[+] Feedback
CY7C1354CV25
CY7C1356CV25
2.5V TAP AC Test Conditions
2.5V TAP AC Output Load Equivalent
1.25V
Input pulse levels ............................................... VSS to 2.5V
Input rise and fall time .................................................... 1 ns
50Ω
Input timing reference levels ........................................1.25V
Output reference levels ................................................1.25V
TDO
Test load termination supply voltage.............................1.25V
Z O= 50Ω
20pF
TAP DC Electrical Characteristics And Operating Conditions
(0°C < TA < +70°C; VDD = 2.5V ±0.125V unless otherwise noted)[13]
Parameter
Description
VOH1
Output HIGH Voltage
VOH2
VOL1
Test Conditions
Min.
IOH = –1.0 mA, VDDQ = 2.5V
2.0
Output HIGH Voltage
IOH = –100 µA,VDDQ = 2.5V
2.1
Output LOW Voltage
IOL = 8.0 mA, VDDQ = 2.5V
IOL = 100 µA
VOL2
Output LOW Voltage
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
IX
Input Load Current
Max.
Unit
V
V
VDDQ = 2.5V
0.4
V
0.2
V
VDDQ = 2.5V
1.7
VDD + 0.3
V
VDDQ = 2.5V
–0.3
0.7
V
–5
5
µA
GND < VIN < VDDQ
Identification Register Definitions
CY7C1354CV25
CY7C1356CV25
Revision Number (31:29)
Instruction Field
000
000
Cypress Device ID (28:12)
01011001000100110
Cypress JEDEC ID (11:1)
00000110100
00000110100
ID Register Presence (0)
1
1
Description
Reserved for version number.
01011001000010110 Reserved for future use.
Allows unique identification of SRAM vendor.
Indicate the presence of an ID register.
Scan Register Sizes
Register Name
Instruction
Bit Size (x36)
Bit Size (x18)
3
3
Bypass
1
1
ID
32
32
Boundary Scan Order (119-ball BGA
package)
69
69
Boundary Scan Order (165-ball FBGA
package)
69
69
Identification Codes
Instruction
Code
Description
EXTEST
000
Captures the Input/Output ring contents. Places the boundary scan register between the TDI and
TDO. Forces all SRAM outputs to High-Z state.
IDCODE
001
Loads the ID register with the vendor ID code and places the register between TDI and TDO. This
operation does not affect SRAM operation.
SAMPLE Z
010
Captures the Input/Output contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a High-Z state.
RESERVED
011
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD 100
Captures the Input/Output ring contents. Places the boundary scan register between TDI and TDO.
Does not affect the SRAM operation.
RESERVED
101
Do Not Use: This instruction is reserved for future use.
RESERVED
110
Do Not Use: This instruction is reserved for future use.
BYPASS
111
Places the bypass register between TDI and TDO. This operation does not affect SRAM operation.
Note:
13. All voltages referenced to VSS (GND).
Document #: 38-05537 Rev. *H
Page 13 of 28
[+] Feedback
CY7C1354CV25
CY7C1356CV25
Boundary Scan Exit Order (256K × 36)
Bit #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
119-ball ID
K4
H4
M4
F4
B4
G4
C3
B3
D6
H7
G6
E6
D7
E7
F6
G7
H6
T7
K7
L6
N6
P7
N7
M6
L7
K6
P6
T4
A3
C5
B5
A5
C6
A6
P4
N4
R6
T5
T3
R2
R3
P2
P1
L2
K1
N2
N1
Document #: 38-05537 Rev. *H
165-ball ID
B6
B7
A7
B8
A8
A9
B10
A10
C11
E10
F10
G10
D10
D11
E11
F11
G11
H11
J10
K10
L10
M10
J11
K11
L11
M11
N11
R11
R10
P10
R9
P9
R8
P8
R6
P6
R4
P4
R3
P3
R1
N1
L2
K2
J2
M2
M1
Boundary Scan Exit Order (256K × 36) (continued)
Bit #
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
119-ball ID
M2
L1
K2
Not Bonded
(Preset to 1)
H1
G2
E2
D1
H2
G1
F2
E1
D2
C2
A2
E4
B2
L3
G3
G5
L5
B6
165-ball ID
L1
K1
J1
Not Bonded
(Preset to 1)
G2
F2
E2
D2
G1
F1
E1
D1
C1
B2
A2
A3
B3
B4
A4
A5
B5
A6
Page 14 of 28
[+] Feedback
CY7C1354CV25
CY7C1356CV25
Boundary Scan Exit Order (512K × 18)
Bit #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
119-ball ID
K4
H4
M4
F4
B4
G4
C3
B3
T2
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
D6
E7
F6
G7
H6
T7
K7
L6
N6
P7
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
T6
A3
C5
B5
A5
C6
A6
P4
N4
R6
T5
T3
R2
R3
Document #: 38-05537 Rev. *H
165-ball ID
B6
B7
A7
B8
A8
A9
B10
A10
A11
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
C11
D11
E11
F11
G11
H11
J10
K10
L10
M10
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
R11
R10
P10
R9
P9
R8
P8
R6
P6
R4
P4
R3
P3
R1
Boundary Scan Exit Order (512K × 18) (continued)
Bit #
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
69
69
68
69
66
67
68
69
119-ball ID
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
P2
N1
M2
L1
K2
Not Bonded
(Preset to 1)
H1
G2
E2
D1
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
C2
A2
E4
B2
Not Bonded
(Preset to 0
G3
Not Bonded
(Preset to 0
L5
B6
B6
B6
L5
B6
G3
Not Bonded
(Preset to 0
L5
B6
165-ball ID
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
N1
M1
L1
K1
J1
Not Bonded
(Preset to 1)
G2
F2
E2
D2
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
B2
A2
A3
B3
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
A4
B5
A6
A6
A6
B5
A6
Not Bonded
(Preset to 0)
A4
B5
A6
Page 15 of 28
[+] Feedback
CY7C1354CV25
CY7C1356CV25
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Supply Voltage on VDD Relative to GND........ –0.5V to +3.6V
Supply Voltage on VDDQ Relative to GND ...... –0.5V to +VDD
DC to Outputs in Tri-State ................... –0.5V to VDDQ + 0.5V
DC Input Voltage....................................–0.5V to VDD + 0.5V
Current into Outputs (LOW)......................................... 20 mA
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current.................................................... > 200 mA
Operating Range
Range
Commercial
Industrial
Ambient Temperature
0°C to +70°C
–40°C to +85°C
VDD/VDDQ
2.5V ± 5%
Electrical Characteristics Over the Operating Range[14, 15]
Parameter
Description
VDD
Power Supply Voltage
Test Conditions
Min.
Max.
Unit
2.375
2.625
V
2.375
VDD
VDDQ
I/O Supply Voltage
for 2.5V I/O
VOH
Output HIGH Voltage
for 2.5V I/O, IOH = −1.0 mA
VOL
Output LOW Voltage
for 2.5V I/O, IOL= 1.0 mA
0.4
V
VIH
Input HIGH Voltage
for 2.5V I/O
1.7
VDD + 0.3V
V
VIL
Input LOW Voltage[14]
for 2.5V I/O
–0.3
0.7
V
IX
Input Leakage Current
except ZZ and MODE
GND ≤ VI ≤ VDDQ
–5
5
µA
2.0
Input = VDD
Input Current of ZZ
5
Input = VSS
30
µA
5
µA
4-ns cycle, 250 MHz
250
mA
5-ns cycle, 200 MHz
220
mA
6-ns cycle, 166 MHz
180
mA
Max. VDD, Device Deselected, 4-ns cycle, 250 MHz
VIN ≥ VIH or VIN ≤ VIL, f = fMAX = 5-ns cycle, 200 MHz
1/tCYC
6-ns cycle, 166 MHz
130
mA
Input = VDD
Output Leakage Current GND ≤ VI ≤ VDDQ, Output Disabled
IDD
VDD Operating Supply
Automatic CE
Power-down
Current—TTL Inputs
µA
µA
–5
IOZ
ISB1
µA
–30
Input Current of MODE Input = VSS
V
V
VDD = Max., IOUT = 0 mA,
f = fMAX = 1/tCYC
–5
120
mA
110
mA
ISB2
Automatic CE
Max. VDD, Device Deselected, All speed grades
Power-down
VIN ≤ 0.3V or VIN > VDDQ − 0.3V,
Current—CMOS Inputs f = 0
40
mA
ISB3
Automatic CE
Max. VDD, Device Deselected, 4-ns cycle, 250 MHz
Power-down
VIN ≤ 0.3V or VIN > VDDQ − 0.3V, 5-ns cycle, 200 MHz
Current—CMOS Inputs f = fMAX = 1/tCYC
6-ns cycle, 166 MHz
120
mA
ISB4
Automatic CE
Power-down
Current—TTL Inputs
Max. VDD, Device Deselected,
VIN ≥ VIH or VIN ≤ VIL, f = 0
All speed grades
110
mA
100
mA
40
mA
Notes:
14. Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2), undershoot: VIL(AC)> –2V (Pulse width less than tCYC/2).
15. TPower-up: Assumes a linear ramp from 0V to VDD (min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
Document #: 38-05537 Rev. *H
Page 16 of 28
[+] Feedback
CY7C1354CV25
CY7C1356CV25
Capacitance[16]
Parameter
Test Conditions
100 TQFP
Max.
TA = 25°C, f = 1 MHz,
VDD = 2.5V, VDDQ = 2.5V
5
5
5
pF
5
5
5
pF
5
7
7
pF
Description
CIN
Input Capacitance
CCLK
Clock Input Capacitance
CI/O
Input/Output Capacitance
119 BGA
Max.
165 FBGA
Max.
Unit
Thermal Resistance[16]
Parameters
Description
Thermal Resistance
ΘJA
(Junction to
Ambient)
Thermal Resistance
ΘJC
(Junction to Case)
Test Conditions
Test conditions follow standard
test methods and procedures
for measuring thermal
impedance, per EIA/JESD51.
100 TQFP
Package
29.41
119 BGA
Package
34.1
165 FBGA
Package
16.8
Unit
°C/W
6.13
14
3.0
°C/W
AC Test Loads and Waveforms
2.5V I/O Test Load
R = 1667Ω
2.5V
OUTPUT
10%
(a)
INCLUDING
JIG AND
SCOPE
90%
10%
90%
GND
5 pF
VT = 1.25V
ALL INPUT PULSES
VDDQ
OUTPUT
RL = 50Ω
Z0 = 50Ω
R = 1538Ω
(b)
≤ 1 ns
≤ 1 ns
(c)
Note:
16. Tested initially and after any design or process change that may affect these parameters.
Document #: 38-05537 Rev. *H
Page 17 of 28
[+] Feedback
CY7C1354CV25
CY7C1356CV25
Switching Characteristics Over the Operating Range [18, 19]
–250
–200
Parameter
Description
Min.
[17]
VCC (typical) to the First Access Read or Write
1
1
1
ms
4.0
5
6
ns
tPower
Max.
Min.
–166
Max.
Min.
Max.
Unit
Clock
tCYC
Clock Cycle Time
FMAX
Maximum Operating Frequency
tCH
Clock HIGH
1.8
2.0
2.4
ns
tCL
Clock LOW
1.8
2.0
2.4
ns
250
200
166
MHz
Output Times
tCO
Data Output Valid after CLK Rise
2.8
3.2
3.5
ns
tEOV
OE LOW to Output Valid
2.8
3.2
3.5
ns
tDOH
Data Output Hold after CLK Rise
1.25
tCHZ
Clock to High-Z[20, 21, 22]
1.25
tCLZ
Low-Z[20, 21, 22]
1.25
Clock to
High-Z[20, 21, 22]
tEOHZ
OE HIGH to Output
tEOLZ
OE LOW to Output Low-Z[20, 21, 22]
1.5
2.8
1.5
1.5
3.2
1.5
2.8
1.5
ns
3.5
1.5
3.2
ns
ns
3.5
ns
0
0
0
ns
1.4
1.5
1.5
ns
Set-up Times
tAS
Address Set-up before CLK Rise
tDS
Data Input Set-up before CLK Rise
1.4
1.5
1.5
ns
tCENS
CEN Set-up before CLK Rise
1.4
1.5
1.5
ns
tWES
WE, BWx Set-up before CLK Rise
1.4
1.5
1.5
ns
tALS
ADV/LD Set-up before CLK Rise
1.4
1.5
1.5
ns
tCES
Chip Select Set-up
1.4
1.5
1.5
ns
tAH
Address Hold after CLK Rise
0.4
0.5
0.5
ns
tDH
Data Input Hold after CLK Rise
0.4
0.5
0.5
ns
tCENH
CEN Hold after CLK Rise
0.4
0.5
0.5
ns
Hold Times
tWEH
WE, BWx Hold after CLK Rise
0.4
0.5
0.5
ns
tALH
ADV/LD Hold after CLK Rise
0.4
0.5
0.5
ns
tCEH
Chip Select Hold after CLK Rise
0.4
0.5
0.5
ns
Notes:
17. This part has a voltage regulator internally; tpower is the time power needs to be supplied above VDD minimum initially, before a Read or Write operation can be
initiated.
18. Timing reference level is when VDDQ = 2.5V.
19. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
20. tCHZ, tCLZ, tEOLZ, and tEOHZ are specified with AC test conditions shown in (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
21. At any given voltage and temperature, tEOHZ is less than tEOLZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
22. This parameter is sampled and not 100% tested.
Document #: 38-05537 Rev. *H
Page 18 of 28
[+] Feedback
CY7C1354CV25
CY7C1356CV25
Switching Waveforms
Read/Write Timing[23, 24, 25]
1
2
3
t CYC
4
5
6
A3
A4
7
8
9
A5
A6
A7
10
CLK
tCENS
tCENH
tCH
tCL
CEN
tCES
tCEH
CE
ADV/LD
WE
BWX
A1
ADDRESS
A2
tCO
tAS
tDS
tAH
Data
tDH
D(A1)
tCLZ
D(A2)
D(A2+1)
tDOH
Q(A3)
tOEV
Q(A4)
tCHZ
Q(A4+1)
D(A5)
Q(A6)
n-Out (DQ)
tOEHZ
tDOH
tOELZ
OE
WRITE
D(A1)
WRITE
D(A2)
BURST
WRITE
D(A2+1)
READ
Q(A3)
READ
Q(A4)
DON’T CARE
BURST
READ
Q(A4+1)
WRITE
D(A5)
READ
Q(A6)
WRITE
D(A7)
DESELECT
UNDEFINED
Notes:
23. For this waveform ZZ is tied LOW.
24. When CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH,CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
25. Order of the Burst sequence is determined by the status of the MODE (0 = Linear, 1 = Interleaved). Burst operations are optional.
Document #: 38-05537 Rev. *H
Page 19 of 28
[+] Feedback
CY7C1354CV25
CY7C1356CV25
Switching Waveforms (continued)
NOP, STALL and DESELECT CYCLES[23, 24, 26]
1
2
A1
A2
3
4
5
A3
A4
6
7
8
9
10
CLK
CEN
CE
ADV/LD
WE
BWX
ADDRESS
A5
tCHZ
D(A1)
Data
Q(A2)
D(A4)
Q(A3)
Q(A5)
In-Out (DQ)
WRITE
D(A1)
READ
Q(A2)
STALL
READ
Q(A3)
WRITE
D(A4)
STALL
DON’T CARE
NOP
READ
Q(A5)
DESELECT
CONTINUE
DESELECT
UNDEFINED
Note:
26. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrated CEN being used to create a pause. A write is not performed during this cycle.
Document #: 38-05537 Rev. *H
Page 20 of 28
[+] Feedback
CY7C1354CV25
CY7C1356CV25
Switching Waveforms (continued)
ZZ Mode Timing[27, 28]
CLK
t
ZZ
I
t
t
ZZ
ZZREC
ZZI
SUPPLY
I
t RZZI
DDZZ
ALL INPUTS
(except ZZ)
Outputs (Q)
DESELECT or READ Only
High-Z
DON’T CARE
Notes:
27. Device must be deselected when entering ZZ mode. See cycle description table for all possible signal conditions to deselect the device.
28. I/Os are in High-Z when exiting ZZ sleep mode.
Document #: 38-05537 Rev. *H
Page 21 of 28
[+] Feedback
CY7C1354CV25
CY7C1356CV25
Ordering Information
Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or
visit www.cypress.com for actual products offered.
Speed
(MHz)
166
Ordering Code
CY7C1354CV25-166AXC
Package
Diagram
Operating
Range
Part and Package Type
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
Commercial
CY7C1356CV25-166AXC
CY7C1354CV25-166BGC
51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
CY7C1356CV25-166BGC
CY7C1354CV25-166BGXC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free
CY7C1356CV25-166BGXC
CY7C1354CV25-166BZC
51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)
CY7C1356CV25-166BZC
CY7C1354CV25-166BZXC 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free
CY7C1356CV25-166BZXC
CY7C1354CV25-166AXI
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
Industrial
CY7C1356CV25-166AXI
CY7C1354CV25-166BGI
51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
CY7C1356CV25-166BGI
CY7C1354CV25-166BGXI
51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free
CY7C1356CV25-166BGXI
CY7C1354CV25-166BZI
51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)
CY7C1356CV25-166BZI
CY7C1354CV25-166BZXI
51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free
CY7C1356CV25-166BZXI
Document #: 38-05537 Rev. *H
Page 22 of 28
[+] Feedback
CY7C1354CV25
CY7C1356CV25
Ordering Information (continued)
Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or
visit www.cypress.com for actual products offered.
200
CY7C1354CV25-200AXC
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
Commercial
CY7C1356CV25-200AXC
CY7C1354CV25-200BGC
51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
CY7C1356CV25-200BGC
CY7C1354CV25-200BGXC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free
CY7C1356CV25-200BGXC
CY7C1354CV25-200BZC
51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)
CY7C1356CV25-200BZC
CY7C1354CV25-200BZXC 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free
CY7C1356CV25-200BZXC
CY7C1354CV25-200AXI
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
Industrial
CY7C1356CV25-200AXI
CY7C1354CV25-200BGI
51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
CY7C1356CV25-200BGI
CY7C1354CV25-200BGXI
51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free
CY7C1356CV25-200BGXI
CY7C1354CV25-200BZI
51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)
CY7C1356CV25-200BZI
CY7C1354CV25-200BZXI
51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free
CY7C1356CV25-200BZXI
Document #: 38-05537 Rev. *H
Page 23 of 28
[+] Feedback
CY7C1354CV25
CY7C1356CV25
Ordering Information (continued)
Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or
visit www.cypress.com for actual products offered.
250
CY7C1354CV25-250AXC
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
Commercial
CY7C1356CV25-250AXC
CY7C1354CV25-250BGC
51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
CY7C1356CV25-250BGC
CY7C1354CV25-250BGXC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free
CY7C1356CV25-250BGXC
CY7C1354CV25-250BZC
51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)
CY7C1356CV25-250BZC
CY7C1354CV25-250BZXC 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free
CY7C1356CV25-250BZXC
CY7C1354CV25-250AXI
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
Industrial
CY7C1356CV25-250AXI
CY7C1354CV25-250BGI
51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
CY7C1356CV25-250BGI
CY7C1354CV25-250BGXI
51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free
CY7C1356CV25-250BGXI
CY7C1354CV25-250BZI
51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)
CY7C1356CV25-250BZI
CY7C1354CV25-250BZXI
51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free
CY7C1356CV25-250BZXI
Document #: 38-05537 Rev. *H
Page 24 of 28
[+] Feedback
CY7C1354CV25
CY7C1356CV25
Package Diagrams
100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) (51-85050)
16.00±0.20
1.40±0.05
14.00±0.10
100
81
80
1
20.00±0.10
22.00±0.20
0.30±0.08
0.65
TYP.
30
12°±1°
(8X)
SEE DETAIL
A
51
31
50
0.20 MAX.
0.10
1.60 MAX.
R 0.08 MIN.
0.20 MAX.
0° MIN.
SEATING PLANE
STAND-OFF
0.05 MIN.
0.15 MAX.
0.25
NOTE:
1. JEDEC STD REF MS-026
GAUGE PLANE
0°-7°
R 0.08 MIN.
0.20 MAX.
2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH
MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE
BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH
3. DIMENSIONS IN MILLIMETERS
0.60±0.15
0.20 MIN.
51-85050-*B
1.00 REF.
DETAIL
Document #: 38-05537 Rev. *H
A
Page 25 of 28
[+] Feedback
CY7C1354CV25
CY7C1356CV25
Package Diagrams (continued)
119-Ball BGA (14 x 22 x 2.4 mm) (51-85115)
Ø0.05 M C
Ø0.25 M C A B
A1 CORNER
Ø0.75±0.15(119X)
Ø1.00(3X) REF.
1
2
3 4
5
6
7
7
6
5
4 3 2 1
A
A
B
B
C
D
1.27
C
D
E
E
F
F
H
19.50
J
K
L
20.32
G
H
22.00±0.20
G
J
K
L
M
10.16
M
N
P
N
P
R
R
T
T
U
U
1.27
0.70 REF.
A
3.81
7.62
30° TYP.
14.00±0.20
0.15(4X)
0.15 C
2.40 MAX.
B
0.90±0.05
0.25 C
12.00
51-85115-*B
C
Document #: 38-05537 Rev. *H
0.60±0.10
0.56
SEATING PLANE
Page 26 of 28
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CY7C1354CV25
CY7C1356CV25
Package Diagrams (continued)
165-Ball FBGA (13 x 15 x 1.4 mm) (51-85180)
BOTTOM VIEW
PIN 1 CORNER
TOP VIEW
Ø0.05 M C
Ø0.25 M C A B
PIN 1 CORNER
Ø0.50 -0.06 (165X)
+0.14
1
2
3
4
5
6
7
8
9
10
11
11
9
8
7
6
5
4
3
2
1
A
B
B
C
C
1.00
A
D
D
E
F
F
G
G
H
J
14.00
E
15.00±0.10
15.00±0.10
10
H
J
K
L
L
7.00
K
M
M
N
N
P
P
R
R
A
A
1.00
5.00
10.00
B
B
13.00±0.10
13.00±0.10
1.40 MAX.
0.15 C
0.53±0.05
0.25 C
0.15(4X)
NOTES :
SOLDER PAD TYPE : NON-SOLDER MASK DEFINED (NSMD)
PACKAGE WEIGHT : 0.475g
JEDEC REFERENCE : MO-216 / DESIGN 4.6C
PACKAGE CODE : BB0AC
0.35±0.06
0.36
SEATING PLANE
C
51-85180-*A
NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. ZBT is a trademark of Integrated Device
Technology, Inc. All product and company names mentioned in this document are the trademarks of their respective holders
Document #: 38-05537 Rev. *H
Page 27 of 28
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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CY7C1354CV25
CY7C1356CV25
Document History Page
Document Title: CY7C1354CV25/CY7C1356CV25 9-Mbit (256K x 36/512K x 18)
Pipelined SRAM with NoBL™ Architecture
Document Number: 38-05537
REV.
ECN No.
Issue Date
Orig. of
Change
Description of Change
**
242032
See ECN
RKF
New data sheet
*A
278969
See ECN
RKF
Changed Boundary Scan order to match the B Rev of these devices
*B
284929
See ECN
RKF
VBL
Included DC Characteristics Table
Changed ISB1 and ISB3 from DC Characteristic table as follows:
ISB1: 225 MHz -> 130 mA, 200 MHz -> 120 mA, 167 MHz -> 110 mA
ISB3: 225 MHz -> 120 mA, 200 MHz -> 110 mA, 167 MHz -> 100 mA
Changed IDDZZ to 50mA.
Added BG and BZ pkg lead-free part numbers to ordering info section.
*C
323636
See ECN
PCI
Changed frequency of 225 MHz into 250 MHz
Added tCYC of 4.0 ns for 250 MHz
Changed ΘJA and ΘJC for TQFP Package from 25 and 9 °C/W to 29.41 and
6.13 °C/W respectively
Changed ΘJA and ΘJC for BGA Package from 25 and 6 °C/W to 34.1 and
14.0 °C/W respectively
Changed ΘJA and ΘJC for FBGA Package from 27 and 6 °C/W to 16.8 and
3.0 °C/W respectively
Modified address expansion as per JEDEC Standard
Removed comment of Lead-free BG and BZ packages availability
*D
332879
See ECN
PCI
Unshaded 200 and 166 MHz speed bin in the AC/DC Table and Selection
Guide
Added Address Expansion pins in the Pin Definition Table
Removed description of Extest Output Bus Tri-state on page # 11
Modified VOL, VOH test conditions
Updated Ordering Information Table
*E
357258
See ECN
PCI
Changed from Preliminary to Final
Changed ISB2 from 35 to 40 mA
Removed Shading on 250MHz Speed Bin in Selection Guide and AC/DC
Table
Updated Ordering Information Table
*F
377095
See ECN
PCI
Modified test condition in note# 15 from VDDQ < VDD to VDDQ ≤ VDD
*G
408298
See ECN
RXU
Changed address of Cypress Semiconductor Corporation on Page# 1 from
“3901 North First Street” to “198 Champion Court”
Changed three-state to tri-state.
Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in
the Electrical Characteristics Table.
Replaced Package Name column with Package Diagram in the Ordering
Information table.
Updated the Ordering Information Table.
*H
501793
See ECN
VKN
Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND
Changed tTH, tTL from 25 ns to 20 ns and tTDOV from 5 ns to 10 ns in TAP
AC Switching Characteristics table.
Updated the Ordering Information table.
Document #: 38-05537 Rev. *H
Page 28 of 28
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