2.5V 8BIT 2MSPS DAC GENERAL DESCRIPTION FEATURES The DAC1252X_JVC is a CMOS 8BIT D/A converter for general application. This digital to analog converter has a R2R structure. Its settling time is 500ns (Typical value). TYPICAL APPLICATIONS • • • • DAC1252X_JVC Hard Disk Drive (HDD) Battery Operated Instruments Motor Control Systems General Applications • • • • • • • • Resolution : 8BIT Differential Linearity Error : ± 1.0 LSB Integral Linearity Error : ± 1.0 LSB Settling Time : 500ns Low Power Consumption : 890uA Power Down Mode Operation Temperature Range : 0ºC ~ 70ºC Power Supply : 2.5V Single and 1.8V single FUNCTIONAL BLOCK DIAGRAM AVDD18D AVBB25A AVSS25D AVDD25D VRT AVSS25A AVDD25A D[7:0] Level Shifter R2R + VRB AMP _ PD Ver 1.0 (June 2000) This datasheet is a preliminary version. No responsibility is assumed by SEC for its use nor for any infringements of patents or other rights of third parties that may result from its use. The content of this datasheet is subject to change without any notice. SAMSUNG ELECTRONICS Co. LTD VOUT DAC1252X_JVC 2.5V 8BIT 2MSPS DAC CORE PIN DESCRIPTION I/O TYPE NAME I/O PAD PIN DESCRIPTION D[7:0] DI picc_abb Digital Input Data (8BIT) D[7] : MSB , D[0] : LSB PD DI picc_abb Power Down (Active Low) VRT AB pia_abb Voltage Reference Top VRB AB pia_abb Voltage Reference Bottom VOUT AO poa_abb Analog Voltage Output AVDD25A AP vdd2t_abb Analog Power (+2.5V) AVSS25A AG vdd2t_abb Analog Ground (0.0V) AVDD25D DP vdd2t_abb Digital Power (+2.5V) AVSS25D DG vss2t_abb Digital Ground (0.0V) AVDD18D DP vss1t_abb Digital power (+1.8V) AVBB25A AG vbb_abb Analog Sub Bias (0.0V) I/O TYPE ABBR. • • • • • • AI : Analog Input DI : Digital Input AO : Analog Output DO : Digital Output AB : Analog Bidirectional DB : Digital Bidirectional • • • • AP DP AG DG : : : : Analog Power Digital Power Analog Ground Digital Ground CORE CONFIGURATION AVDD18D AVBB25A AVSS25D AVDD25D AVSS25A AVDD25A dac1252X_jvc D[7:0] VRT SEC ASIC VRB VOUT PD 2 / 10 ANALOG DAC1252X_JVC 2.5V 8BIT 2MSPS DAC ABSOLUTE MAXIMUM RATINGS Characteristics Symbol Value Unit VDD (AVDD25A,AVDD25D) 3.3 V Analog Output Voltage VOUT AVSS25A to AVDD25A V Digital Input Voltage D[7:0] VSS25D to AVDD18D V Reference Voltage VRT VRB AVDD25A AVSS25A V Operating Temperature Range Topr 0 to 70 °C Supply Voltage NOTES : 1. ABSOLUTE MAXIMUM RATING specifies the values beyond which the device may be damaged permanently. Exposure to ABSOLUTE MAXIMUM RATING conditions for extended periods may affect reliability. Each condition value is applied with the other values kept within the following operating conditions and function operation under any of these conditions is not implied. 2. All voltages are measured with respect to VSS(AVSS25A or VSS25AD0 or AVBB25A) unless otherwise specified. 3. 100pF capacitor is discharged through a 1.5kΩ resistor (Human body model) RECOMMENDED OPERATING CONDITIONS Symbol Min Typ Max Unit Supply Voltage AVDD25A - AVSS25A AVDD25D - VSS25AD0 2.375 2.5 2.625 V Supply Voltage Difference AVDD25A - AVDD25D -0.1 0.0 0.1 V Reference Voltage VRT VRB 0.0 - 2.5 - V Digital Input 'Low' Voltage Digital Input 'High' Voltage VIL VIH - - 0.3×ΑVDD18D 0.7×AVDD18D - V Operating Temperature Topr 0 - 70 °C Characteristics NOTE : It is strongly recommended that to avoid power latch-up all the supply pins(AVDD25A,AVDD25D) be driven from the same source. SEC ASIC 3 / 10 ANALOG DAC1252X_JVC 2.5V 8BIT 2MSPS DAC DC ELECTRICAL CHARACTERISTICS (Converter Specifications : AVDD25A=AVDD25D=2.5V, AVSS25A=VSS25AD0=AVBB25A=0V, PD=High, Top=25°C, VRT=2.5V, VRB=0.0V unless otherwise specified.) Symbol Min Typ Max Unit Bit - 8 - Bits - Differential Linearity Error DLE - 1.0 - LSB - Integral Linearity Error ILE - 1.0 - LSB - Zero Scale Error1 VZSE - 5 - mV Full Scale Voltage Error2 VFSE - 5 - mV Maximum Output Voltage VoMAX - 2.499 - V VLSB - 0.61 - mV Characteristics Resolution Conditions VRT=2.5V , VRB=0.0V LSB Size NOTE VoMAX = VOUT(D[7:0]=High) VLSB = VoMAX / 256 1 : VZSE=VOUT(D[7:0]=Low) - VRB 2 : VFSE=VOUT(D[7:0]=High) - {(VRT-VRB) × 255/256 + VRB} AC ELECTRICAL CHARACTERISTICS (Converter Specifications : AVDD25A=AVDD25D=2.5V, AVSS25A=VSS25AD0=AVBB25A=0V, load cap=25pF Top=25°C, PD=High, VRT=2.45V, VRB=0.05V unless otherwise specified.) Symbol Min Typ Max Unit Ivdd1 - 0.89 - mA Ivdd1 = IVDD28AA0 + IAVDD25D VRT=2.5V , VRB = 0.0V Data Input : All Low or All High Ivdd2 - 1.22 - mA Ivdd2 = IAVDD25A + IAVDD25D Data Input : All Low or All High Supply Current (Power Down Mode) Ivdd3 - - 10 uA Ivdd3 = IAVDD25A + IAVDD25D Data Rate = 2MHz Load cap = 25pF , PWDN=LOW Short Circuit Current ISC - 12 - mA VOUT : AVSS25A or AVDD25A Data Input : All High or All Low Analog Output Delay Td - 65 - ns Data Rate = 2MHz Data : All LOW → All HIGH Analog Output Rise Time Tr - 100 - ns Data Rate = 2MHz Data : All LOW → All HIGH Analog Output Fall Time Tf - 100 - ns Data Rate = 2MHz Data : All HIGH → All LOW Analog Output Settling Time Ts - 500 - ns Data Rate = 2MHz Data : All LOW → All HIGH Power Down Off Time Ton - 500 - ns PD : HIGH → LOW Power Down On Time Toff - 500 - ns PD : LOW → HIGH Characteristics Supply Current SEC ASIC 4 / 10 Conditions ANALOG DAC1252X_JVC 2.5V 8BIT 2MSPS DAC TIMING DIAGRAM DATA 00000000 00000000 11111111 11111111 00000000 90% VOUT DATA 50% 10% Td VOUT Tf Tr DATA 50% 00000000 11111111 00000000 ± 0.5LSB VOUT 50% Ts PD 50% 50% Toff Ton ± 0.5LSB VOUT ± 0.5LSB 0.0V 1. Output delay measured from the 50% point of the rising edge of input data to the full scale transition. 2. Settling time measured from the 50% point of full scale transition to the output remaining within ±1/2 LSB. 3. Output rise/fall time measured between the 10% and 90% points of full scale transition. FUNCTIONAL DESCRIPTION 1. The DAC1252X_JVC has a 8BIT R-2R block, two decoders, two OP amps, and control block. 2. The digital outputs of two decoders decide the voltage level of R2R block. V Rstring = VRT − VRB 8 n ( 2 * Dn) ∑ 8 2 n=0 3. Normal Conditions : VRT=2.45V , VRB=0.05V, PD=High You can change the voltages of VRT and VRB to 2.5V and 0.0V , but the performance of DAC1252X_JVC will be degraded. SEC ASIC 5 / 10 ANALOG DAC1252X_JVC 2.5V 8BIT 2MSPS DAC CORE EVALUATION GUIDE HOST DSP CORE 8 8 MUX TEST PATH 8 Cc VRT Ct 2.5V AVSS25A GND AVDD25D 2.5V Ct Cc Cc Ct GND AVSS25D AVBB25A Cc Ct VRB Ct Cc 0.05V GND Dac1252x_jvc 2.45V GND D[11:0] PD AVDD25A 1.8V AVDD18D VOUT VOUT LOCATION DESCRIPTION Ct 10uF TANTALUM CAPACITOR Cc 0.1uF CERAMIC CAPACITOR TESTABILITY Whether you use MUX or the internal logic for testability, it is required to be able to select the values of digital inputs ( D[7:0] ). See above figure. Only if it is, you can check the main functon. ( Linearity ) Normal Test Condition : VRT=2.45V , VRB=0.05V , PD=High SEC ASIC 6 / 10 ANALOG DAC1252X_JVC 2.5V 8BIT 2MSPS DAC CORE LAYOUT GUIDE PD AVDD25A AVSS25A AVBB25A VOUT OPAMP R2R Ladder & AVSS25D AVDD18D Level Shifter P+ Guardring NWELL Guardring VRB VRT D[7:0] 1. It is recommended that you use thick analog power metal. when connecting to PAD, the path should be kept as short as possible. 2. Digital power and analog power are separately used. 3. When the core block is connected to other blocks, it must be double guard-ring using N-well and P+ active to remove the substrate and coupling noise. In that case, the power metal should be connected to PAD directly. 4. The Bulk power is used to reduce the influence of substrate noise. 5. Digital input signal lines must be same length to reduce the difference of delay. SEC ASIC 7 / 10 ANALOG DAC1252X_JVC 2.5V 8BIT 2MSPS DAC PC BOARD LAYOUT CONSIDERATION 1. PC Board Considerations To minimize noise on the power lines and the ground lines, the digital inputs need to be shielded and decoupled. This trace length between groups of VDD (AVDD25A,AVDD25D) and VSS (AVSS25A,VSS25AD0) pins should be as short as possible so as to minimize inductive ringing. 2. Supply Decoupling and Planes For the decoupling capacitor between the power line and the ground line, 0.1uF ceramic capacitor is used in parallel with a 10uF tantalum capacitor. The digital power plane(AVDD25D) and analog power plane(AVDD25A) are connected through a ferrite bead, and also the digital ground plane(VSS25AD0) and the analog ground plane(AVSS25A). This ferrite bead should be located within 3inches of the DAC1252X_JVC. The analog power plane supplies power to the DAC1252X_JVC of the analog output pin and related devices. SEC ASIC 8 / 10 ANALOG DAC1252X_JVC 2.5V 8BIT 2MSPS DAC FEEDBACK REQUEST We appreciate your interest in out products. If you have further questions, please specify in the attached form. Thank you very much. DC / AC ELECTRICAL CHARACTERISTIC Characteristics Min Typ Max Unit Supply Voltage V Power dissipation mW Resolution Bits Analog Output Voltage V Operating Temperature °C Output Load Capacitor pF Output Load Resistor °C Integral Non-Linearity Error LSB Differential Non-Linearity Error LSB Maximum Conversion Rate MHz Remarks VOLTAGE OUTPUT DAC Reference Voltage TOP BOTTOM V Analog Output Voltage Range Digital Input Format V Binary Code or 2's Complement Code CURRENT OUTPUT DAC - Analog Output Maximum Current mA Analog Output Maximum Signal Frequency kHz Reference Voltage V External Resistor for Current Setting(RSET) W Pipeline Delay sec Do you want to Power Do you want to Interal Which do you want to Do you need 3.3V and down mode? Reference Voltage(BGR)? Serial Input TYPE or parallel Input TYPE? 5V power supply in your system? SEC ASIC 9 / 10 ANALOG DAC1252X_JVC 2.5V 8BIT 2MSPS DAC HISTORY CARD Version 1.0 Date Jun.00 Modified Items Comments New generate dac1252x_jvc SEC ASIC ANALOG