ETC DM512K64DT6-12

DM512K64DT6/DM512K72DT6 Multibank EDO
EDRAM
512Kb x 64/512Kb x 72 Enhanced DRAM DIMM
Enhanced
Memory Systems Inc.
Product Specification
Features
■
8Kbytes SRAM Cache Memory for 12ns Random Reads Within Four
Active Pages (Multibank Cache)
■ Fast 4Mbyte DRAM Array for 30ns Access to Any New Page
■ Write Posting Registers for 12ns Random Writes and Burst Writes
Within a Page (Hit or Miss)
■ 2Kbyte Wide DRAM to SRAM Bus for 113.6 Gigabytes/Second
Cache Fill Rate
■ A Hit Pin Outputs Status on On-chip Page Hit/Miss Comparators to
Simplify Control
■
Description
Architecture
The Enhanced Memory Systems 4MB enhanced DRAM
(EDRAM)DIMM module provides a single memory module solution
for the main memory or local memory of fast 64-bit embedded
computers, communications switches, and other high performance
systems. Due to its fast non-interleave architecture, the EDRAM DIMM
module supports zero-wait-state burst read or write operation to
83MHz. The EDRAM outperforms conventional SRAM plus DRAM or
synchronous DRAM memory systems by minimizing wait states on
initial reads (hit or miss) and eliminating writeback delays.
Each 4Mbyte DIMM module has 8Kbytes of SRAM cache
organized as four 256 x 72 row registers with 12ns initial access
time. On a cache miss, the fast DRAM array reloads an entire 2Kbyte
row register over a 2Kbyte-wide bus in just 18ns for an effective cache
fill rate of 113.6 Gbytes/second. During write cycles, a write posting
register allows the initial write to be posted as early as 5ns after
column address is available. EDRAM supports direct non-interleave
page writes at up to 83MHz. An on-chip hit/miss comparator
automatically maintains cache coherency during writes.
The DM512K72DT6 achieves
512Kb x 72 density by mounting
nine 512Kx8 EDRAMs, packaged
in low profile 44-pin TSOP-II
packages on one side of the multilayer substrate. Three high drive
series terminated buffer chips
buffer address and control lines.
Twelve surface mount capacitors
are used to decouple the power
supply bus. The DM512K64DT
contains eight 512Kx8 EDRAMs.
The parity data component is not
populated.
The EDRAM memory module architecture is very similar to two
standard 2MB DRAM SIMM modules configured in a 64-bit wide,
non-interleave configuration. The EDRAM module adds an integrated
cache and cache control logic which allow the cache to operate much
like a page mode or static column DRAM.
The EDRAM’s SRAM cache is
integrated into the DRAM array as tightly
coupled row registers. Memory reads
always occur from the 256 x 72 cache
row register associated with a 1MB
segment of DRAM. When the on-chip
comparator detects a page hit, only the
/QLE
SRAM is accessed and data is available
/G
in 12ns from column address (the /HIT
I/O
output is low to indicate a page hit).
Control
DQ
and
When a page miss is detected, the entire
0-71
Data
Latches
new DRAM row is loaded into cache and
/S
data is available at the output within
30ns from row enable (the /HIT output
/WE
is high to indicate a page miss).
Subsequent reads within a page (burst
reads or random reads) will continue at
V
12ns cycle time. Since reads occur from
C
the SRAM cache, the DRAM precharge
V
can occur simultaneously without
PD
degrading performance. The on-chip
refresh counter with independent
Functional Diagram
Column
Add
Latch
CAL 0-8
A 0-7
Column Decoder
4- 256 X 72 Cache Pages
(Row Register)
4-Bit
Comp
Sense Amps
& Column Write Select
Row
Add
Latch
/F
W/R
/RE
Row Add
and
Refresh
Control
Row Decoder
4- Last
Row
Read
Add
Latches
A 0-10
Memory
Array
(4 Mbyte + Parity)
A 0-9
Refresh
Counter
The information contained herein is subject to change without notice.
Enhanced reserves the right to change or discontinue this product without notice.
On-chip Cache Hit/Miss Comparators Automatically Maintain Cache
Coherency on Writes
■ Hidden Precharge & Refresh Cycles
■ Extended 64ms Refresh Period for Low Standby Power
■ CMOS/TTL Compatible I/O and +5 Volt Power Supply
■ Output Latch Enable Allows Extended Data Output (EDO) for
Faster System Operation
CC
1-12
SS
© 1996 Enhanced Memory Systems Inc. 1850 Ramtron Drive, Colorado Springs, CO
Telephone (800) 545-DRAM; Fax (719) 488-9095; http://www.csn.net/ramtron/enhanced
80921
38-2123-000
refresh bus allows the EDRAM to be refreshed during cache reads.
Memory writes can be posted as early as 6.5ns after row
enable and are directed to the DRAM array. During a write hit, the
on-chip address comparator activates a parallel write path to the
SRAM cache to maintain coherency. Memory writes do not affect
the contents of the cache row register except during write hits.
By integrating the SRAM cache as row registers in the DRAM
array and keeping the on-chip control simple, the EDRAM is able
to provide superior system performance at less cost, power, and
area than systems implemented with complex synchronous SRAM
cache, cache controllers, and multilevel data busses.
Functional Description
The EDRAM is designed to provide optimum memory
performance with high speed microprocessors. As a result, it is
possible to perform simultaneous operations to the DRAM and
SRAM cache sections of the EDRAM. This feature allows the EDRAM
to hide precharge and refresh operation during reads and
maximize hit rate by maintaining page cache contents during write
operations even if data is written to another memory page. These
capabilities, in conjunction with the faster basic DRAM and cache
speeds of the EDRAM, minimize processor wait states.
EDRAM Basic Operating Modes
The EDRAM operating modes are specified in the table.
Hit and Miss Terminology
In this datasheet, “hit” and “miss” always refer to a hit or miss
to any of the four pages of data contained in the SRAM cache row
registers. There are four cache row registers, one for each of the
four banks of DRAM. These registers are specified by the bank
select row address bits A8 and A9. The contents of these cache row
registers is always equal to the last row that was read from each of
the four internal DRAM banks (as modified by any write hit data).
DRAM Read Hit
A DRAM read request is initiated by clocking /RE with W/R low
and /F high. The EDRAM will compare the new row address to the
last row read address latch for the bank specified by row address
bits A8-9 (LRR: a 9-bit row address latch for each internal DRAM
bank which is reloaded on each /RE active read miss cycle). If the
row address matches the LRR, the requested data is already in the
SRAM cache and no DRAM memory reference is initiated. The data
specified by the row and column address is available at the output
pins at the greater of times tAC or tGQV. The /HIT output is driven
low at time tHV after /RE to indicate the shorter access time to the
Four Bank Cache Architecture
HIT0
HIT1
HIT2
HIT3
/HIT
Bank 3
Bank 2
Bank 1
A0-10
Column Address Latch
Row Address Latch
Bank 0
Last
Row
Read
Address
Latch
+ 9-Bit
Compare
RA0-10
CA0-7
1M Array
1M Array
1M Array
1M Array
D0-71
Data-In
Latch
CA0-7
256 x 72
Cache
Bank 0
(0,0)
256 x 72
Cache
256 x 72
Cache
Bank 1
Bank 2
(0,1)
(1,0)
1 of 4 Selector
RA8, RA9
Data-Out
Latch
CAL
QLE
G
S
Q0-71
2-138
256 x 72
Cache
Bank 3
(1,1)
external control logic. Since no DRAM activity is initiated, /RE can
be brought high after time tRE1, and a shorter precharge time, tRP1,
is required. Additional locations within the currently active page
may be accessed concurrently with precharge by providing new
column addresses to the multiplex address inputs. New data is
available at the output at time tAC after each column address change
in static column mode. During any read cycle, it is possible to
operate in either static column mode with /CAL=high or page
mode with /CAL clocked to latch the column address. In page
mode, data valid time is determined by either tAC and tCQV.
DRAM Read Miss
A DRAM read request is initiated by clocking /RE with W/R low
and /F high. The EDRAM will compare the new row address to the
LRR address latch for the bank specified by row address bits A8-9
(LRR: a 9-bit row address latch for each internal DRAM bank
which is reloaded on each /RE active read miss cycle). If the row
address does not match the LRR, the requested data is not in SRAM
cache and a new row is fetched from the DRAM. The EDRAM will
load the new row data into the SRAM cache and update the LRR
latch. The data at the specified column address is available at the
output pins at the greater of times tRAC, tAC, and tGQV. The /HIT
output is driven high at time tHV after /RE to indicate the longer
access time to the external control logic. /RE may be brought high
after time tRE since the new row data is safely latched into SRAM
cache. This allows the EDRAM to precharge the DRAM array while
data is accessed from SRAM cache. Additional locations within the
currently active page may be accessed by providing new column
addresses to the multiplex address inputs. New data is available at
the output at time tAC after each column address change in static
column mode. During any read cycle, it is possible to operate in
either static column mode with /CAL=high or page mode with /CAL
clocked to latch the column address. In page mode, data valid time
is determined by either tAC and tCQV.
by bringing /WE low (both /CAL and /WE must be high when
initiating the write cycle with the falling edge of /RE). The write
address and data can be latched very quickly after the fall of /RE
(tRAH + tASC for the column address and tDS for the data). During a
write burst sequence, the second write data can be posted at time
tRSW after /RE. Subsequent writes within a page can occur with write
cycle time tPC. With /G enabled and /WE disabled, read operations
may be performed while /RE is activated in write hit mode. This
allows read-modify-write, write-verify, or random read-write
sequences within the page with 12ns cycle times. During a write hit
sequence, the /HIT output is driven low. At the end of any write
sequence (after /CAL and /WE are brought high and tRE is satisfied),
/RE can be brought high to precharge the memory. Cache reads can
be performed concurrently with precharge (see “/RE Inactive
Operation”). When /RE is inactive, the cache reads will occur from
the page accessed during the last /RE active read cycle.
DRAM Write Miss
A DRAM write request is initiated by clocking /RE while W/R,
/CAL, /WE, and /F are high. The EDRAM will compare the new row
address to the LRR address latch for the bank specified for row
address bits A8-9 (LRR: a 9-bit row address latch for each internal
DRAM bank which is reloaded on each /RE active read miss cycle).
If the row address does not match any of the LRRs, the EDRAM will
write data to the DRAM page in the appropriate bank and the
contents of the current cache is not modified. The write address and
data are posted to the DRAM as soon as the column address is
latched by bringing /CAL low and the write data is latched by
bringing /WE low (both /CAL and /WE must be high when initiating
the write cycle with the falling edge of /RE). The write address and
data can be latched very quickly after the fall of /RE (tRAH + tASC for
the column address and tDS for the data). During a write burst
sequence, the second write data can be posted at time tRSW after
/RE. Subsequent writes within a page can occur with write cycle
time tPC. During a write miss sequence, the /HIT output is driven
high, cache reads are inhibited, and the output buffers are disabled
(independently of /G) until time tWRR after /RE goes high. At the end
of a write sequence (after /CAL and /WE are brought high and tRE is
satisfied), /RE can be brought high to precharge the memory. Cache
reads can be performed concurrently with the precharge (see “/RE
Inactive Operation”). When /RE is inactive, the cache reads will
occur from the page accessed during the last /RE active read cycle.
DRAM Write Hit
A DRAM write request is initiated by clocking /RE while W/R,
/CAL, /WE, and /F are high. The EDRAM will compare the new row
address to the LRR address latch for the bank specified by row
address bits A8-9 (LRR: a 9-bit row address latch for each internal
DRAM bank which is reloaded on each /RE active read miss cycle).
If the row address matches the LRR, the EDRAM will write data to
both the DRAM page in the appropriate bank and its corresponding
SRAM cache simultaneously to maintain coherency. The write
/RE Inactive Operation
address and data are posted to the DRAM as soon as the column
Data may be read from the SRAM cache without clocking /RE.
address is latched by bringing /CAL low and the write data is latched This capability allows the EDRAM to perform cache read
EDRAM Basic Operating Modes
Function
/S
/RE
W/R
/F
A0-10
Read Hit
L
↓
L
H
Row = LRR
No DRAM Reference, Data in Cache
Read Miss
L
↓
L
H
Row ≠ LRR
DRAM Row to Cache
Write Hit
L
↓
H
H
Row = LRR
Write to DRAM and Cache, Reads Enabled
Write Miss
L
↓
H
H
Row ≠ LRR
Write to DRAM, Cache Not Updated, Reads Disabled
Internal Refresh
X
↓
X
L
X
Low Power Standby
H
H
X
X
X
Unallowed Mode
H
L
X
H
X
H = High; L = Low; X = Don’t Care; ↓ = High-to-Low Transition; LRR = Last Row Read
2-139
Comment
Standby Current
operations during precharge and refresh cycles to minimize wait
states. It is only necessary to select /S and /G and provide the
appropriate column address to read data as shown in the table
below. In this mode of operation, the cache reads will occur from
the page and bank accessed during the last /RE active read cycle.
To perform a cache read in static column mode, /CAL is held high,
and the cache contents at the specified column address will be
valid at time tAC after address is stable. To perform a cache read in
page mode, /CAL is clocked to latch the column address. When /RE
is inactive, the hit pin is not driven and is in a high impedance
state.
This option is desirable when the external control logic is
capable of fast hit/miss comparison. In this case, the controller can
avoid the time required to perform row/column multiplexing on hit
cycles.
Internal Refresh
If /F is active (low) on the assertion of /RE, an internal refresh
cycle is executed. This cycle refreshes the row address supplied by
an internal refresh counter. This counter is incremented at the end
of the cycle in preparation for the next /F refresh cycle. At least
1,024 /F cycles must be executed every 64ms. /F refresh cycles can
be hidden because cache memory can be read under column
address control throughout the entire /F cycle. /F cycles are the
only active cycles where /S can be disabled.
/RE Only Refresh Operation
Although /F refresh using the internal refresh counter is the
recommended method of EDRAM refresh, an /RE only refresh may
be performed using an externally supplied row address. /RE
refresh is performed by executing a write cycle (W/R, /G, and /F
are high) where /CAL is not clocked. This is necessary so that the
current cache contents and LRR are not modified by the refresh
Function
/S
/G
/CAL
A0-7
operation. All combinations of addresses A0-9 must be sequenced
every 64ms refresh period. A10 does not need to be cycled. Read
Cache Read (Static Column)
L
L
H
Col Adr
refresh cycles are not allowed because a DRAM refresh cycle does
Cache Read (Page Mode)
L
L
↕
Col Adr
not occur when a read refresh address matches the LRR address
latch.
EDO Mode and Output Latch Enable Operation
The QLE and /CAL inputs can be used to create extended data Low Power Mode
The EDRAM enters its low power mode when /S is high. In this
output (EDO) mode timings in either static column or page modes.
mode,
the internal DRAM circuitry is powered down to reduce
The DM512K32DT6 has an output latch enable (QLE) that can be
standby
current.
used to extend the data output valid time. The output latch enable
operates as shown in the following table.
Initialization Cycles
When QLE is low, the latch is transparent and the EDRAM
A minimum of eight /RE active initialization cycles (read,
operates identically to the standard EDRAMs. When /CAL is high
write, or refresh) are required before normal operation is
during a static column mode read, the QLE input can be used to
guaranteed. Following these start-up cycles, two read cycles to
latch the output to extend the data output valid time. QLE can be
different row addresses must be performed for each of the four
held high during page mode reads. In this case, the data outputs
internal banks of DRAM to initialize the internal cache logic. Row
are latched while /CAL is high and open when /CAL is not high.
address bits A8 and A9 define the four internal DRAM banks.
Unallowed Mode
QLE
/CAL
Comments
Read, write, or /RE only refresh operations must not be
performed to unselected memory banks by clocking /RE when /S is
L
X
Output Transparent
high.
↕
H
Output Latched When QLE=H (Static Column EDO)
Reduced Pin Count Operation
Although it is desirable to use all EDRAM control pins to
H
↕
Output Latched When /CAL=H (Page Mode EDO)
optimize system performance, the interface to the EDRAM may be
simplified to reduce the number of control lines by either tying pins
Write-Per-Bit Operation
to ground or by tying one or more control inputs together. The /S
The DM512K72 DIMM offers a write-per-bit capability to
input can be tied to ground if the low power standby mode is not
selectively modify individual parity bits (DQ8, 17, 26, 35, 44, 53, 62, 71)
required. The QLE input can be tied low if output latching is not
for byte write operations. The parity device (DM2213) is selected
required, or it can be tied high if “extended data out” (hyper page
via /CAL8. Byte write selection to non-parity bits is accomplished via mode) is required. The /HIT output pin is not necessary for device
/CAL0-7. The bits to be written are determined by a bit mask data
operation. The W/R and /G inputs can be tied together if reads are
word which is placed on the parity I/O data pins prior to clocking not required during a write hit cycle. The simplified control interface
/RE. The logic one bits in the mask data select the bits to be
still allows the fast page read/write cycle times, fast random read/
written. As soon as the mask is latched by /RE, the mask data is
write times, and hidden precharge functions available with the EDRAM.
removed and write data can be placed on the data bus. The mask is
only specified on the /RE transition. During page mode burst write Pin Descriptions
operations, the same mask is used for all write operations.
/RE — Row Enable
These inputs are used to initiate DRAM read and write
ECC Operation
operations and latch a row address. It is not necessary to clock /RE
The DM512K72DT6-xxN supports error correction coding
to read data from the EDRAM SRAM row register. On read
(ECC) by replacing the parity chip with a normal DM2203 device.
operations, /RE can be brought high as soon as data is loaded into
This version does not support write-per-bit parity operation.
cache to allow early precharge.
2-140
/CAL0-8 — Column Address Latch
These inputs are used to latch the column address and in
combination with /WE to trigger write operations. When /CAL is
high, the column address latch is transparent. When /CAL is low,
the column address latch contains the address present at the time
/CAL went low. Individual /CAL inputs are provided for each byte of
EDRAM to allow byte write capability.
W/R — Write/Read
This input along with /F input specifies the type of DRAM
operation initiated on the low going edge of /RE. When /F is high,
W/R specifies either a write (logic high) or read operation (logic
low).
/F — Refresh
This input will initiate a DRAM refresh operation using the
internal refresh counter as an address source when it is low on the
low going edge of /RE.
/WE — Write Enable
This input controls the latching of write data on the input data
pins. A write operation is initiated when both the /CAL for the
specified byte and /WE are low.
/G — Output Enable
This input controls the gating of read data to the output data
pins during read operations.
/S — Chip Select
This input is used to power up the I/O and clock circuitry.
When /S is high, the EDRAM remains in a powered-down condition.
Read or write cycles must not be executed when /S is high. /S must
remain low throughout any read or write operation. Only /F refresh
operation can be executed when, /S is not enabled.
DQ0-71 — Data Input/Output
These CMOS/TTL bidirectional data pins are used to read and
write data to the EDRAM. On the DM2213 write-per-bit memory,
these pins are also used to specify the bit mask used during write
operations.
A0-10 — Multiplex Address
These inputs are used to specify the row and column
addresses of the EDRAM data. The 11-bit row address is latched on
the falling edge of /RE. The 8-bit column address can be specified
at any other time to select read data from the SRAM cache or to
specify the write column address during write cycles.
QLE — Output Latch Enable
This input enables the EDRAM output latches. When QLE is
low, the output latch is transparent. Data is latched when both /CAL
and QLE are high. This allows output data to be extended during
either static column or page mode read cycles.
/HIT — Hit Pin
This output pin will be driven during /RE active read or write
cycles to indicate the hit/miss status of the cycle.
PD — Presence Detect
This output will indicate if the DIMM module is inserted in a
socket. When a DIMM is inserted, this pin is grounded. When no
DIMM is present, the pin is open.
VCC Power Supply
These inputs are connected to the +5 volt power supply.
VSS Ground
These inputs are connected to the power supply ground
connection.
2-141
Pinout
Interconnect
Pin No. Function (Component Pin)
Interconnect
Pin No. Function (Component Pin)
Organization
Organization
Ground
85
V SS
U1-4
Byte 0, I/O 0
86
DQ36
U2-4
Byte 4, I/O 0
DQ1
U1-6
Byte 0, I/O 1
87
DQ37
U2-6
Byte 4, I/O 1
4
DQ2
U1-7
Byte 0, I/O 2
88
DQ 38
U2-7
Byte 4, I/O 2
5
DQ3
U1-9
Byte 0, I/O 3
89
DQ 39
U2-9
Byte 4 I/O 3
6
VDD
+5 Volts
90
V DD
7
DQ4
U1-13
Byte 0, I/O 4
91
DQ 40
U2-13
Byte 4 I/O 4
8
DQ5
U1-15
Byte 0, I/O 5
92
DQ 41
U2-15
Byte 4 I/O 5
9
DQ6
U1-16
Byte 0, I/O 6
93
DQ 42
U2-16
Byte 4, I/O 6
10
DQ7
U1-18
Byte 0, I/O 7
94
DQ 43
U2-18
Byte 4, I/O 7
Parity, I/O 0
95
DQ 44
U5-13
Parity, I/O 4
Ground
96
V SS
1
Vss
2
DQ0
3
U5-4
Ground
+5 Volts
11
DQ8
12
V SS
13
DQ 9
U3-4
Byte 1, I/O 0
97
DQ 45
U4-4
Byte 5, I/O 0
14
DQ 10
U3-6
Byte 1, I/O 1
98
DQ 46
U4-6
Byte 5, I/O 1
15
DQ11
U3-7
Byte 1, I/O 2
99
DQ47
U4-7
Byte 5, I/O 2
16
DQ12
U3-9
Byte 1, I/O 3
100
DQ48
U4-9
Byte 5, I/O 3
17
DQ13
U3-13
Byte 1, I/O 4
101
DQ49
U4-13
Byte 5, I/O 4
18
V DD
+5 Volts
102
VDD
19
DQ14
U3-15
Byte 1, I/O 5
103
DQ50
U4-15
Byte 5, I/O 5
20
DQ15
U3-16
Byte 1 I/O 6
104
DQ51
U4-16
Byte 5, I/O 6
21
DQ16
U3-18
Byte 1 I/O 7
105
DQ52
U4-18
Byte 5, I/O 7
Parity, I/O 1
106
DQ53
U5-15
Parity, I/O 5
U5-6
Ground
+5 Volts
22
DQ17
23
VSS
Ground
107
VSS
Ground
24
VSS
Ground
108
VSS
Ground
25
VDD
+5 Volts
109
VDD
+5 Volts
26
VDD
+5 Volts
110
VDD
+5 Volts
27
/WE
Write Enable
111
/F
U10D-49
Refresh Pin
/CAL1
U3-32
Byte 1 /CAL
Byte 3 /CAL
U10A-8
28
/CAL0
U1-32
Byte 0 /CAL
112
29
/CAL2
U6-32
Byte 2 /CAL
113
/CAL3
U8-32
30
/S
U10A-14
Chip Select
114
N.C.
N.C.
31
/G
U10B-15
Output Enable
115
W/R
U10D-43
32
V SS
Ground
116
VSS
33
A0
Address 0
117
A1
U10C-42
Address 1
A3
U10C-36
Address 3
U10B-21
Write/Read Mode
Ground
34
A2
U11A-8
Address 2
118
35
A4
U11A-14
Address 4
119
A5
U11D-49
Address 5
36
A6
U11B-15
Address 6
120
A7
U11D-43
Address 7
37
A8
U11B-21
Address 8
121
A9
U11C-42
Address 9
38
A 10
U11C-36
Address 10
122
N.C.
123
N.C.
39
N.C.
40
V DD
+5 Volts
124
VDD
41
V DD
+5 Volts
125
N.C.
N.C.
42
QLE
Output Latch Enable
126
N.C.
N.C.
U12A-8
2-142
+5 Volts
Pinout
Interconnect
Pin No. Function (Component Pin)
43
VSS
44
N.C.
N.C.
45
/RE
U12A-14
46
/CAL4
47
Interconnect
Pin No. Function (Component Pin)
Organization
Ground
Organization
127
V SS
Ground
128
V SS
Ground
Row Enable
129
N.C.
N.C.
U2-32
Byte 4 /CAL
130
/CAL5
U4-32
Byte 5
/CAL6
U7-32
Byte 6 /CAL
131
/CAL7
U9-32
Byte 7
48
N.C.
N.C.
132
/CAL8
U5-32
Parity
49
VDD
+5 Volts
133
V DD
+5 Volts
50
VDD
+5 Volts
134
VDD
+5 Volts
51
VSS
Ground
135
VSS
DQ 54
U7-4
Byte 6, I/O 0
U7-6
Byte 6, I/O 1
52
DQ18
U6-4
Byte 2, I/O 0
136
53
DQ19
U6-6
Byte 2, I/O 1
137
DQ 55
54
VSS
Ground
138
V SS
55
DQ20
U6-7
Byte 2, I/O 2
139
DQ
56
DQ 21
U6-9
Byte 2, I/O 3
140
57
DQ 22
U6-13
Byte 2, I/O 4
58
DQ23
59
VDD
60
DQ24
61
PD
62
N.C.
63
N.C.
U6-15
U6-16
Ground
Ground
U7-7
Byte 6, I/O 2
DQ 57
U7-9
Byte 6, I/O 3
141
DQ 58
U7-13
Byte 6, I/O 4
Byte 2, I/O 5
142
DQ59
U7-15
+5 Volts
143
VDD
Byte 2, I/O 6
144
DQ60
U7-16
Byte 6, I/O 6
Ground
145
/Hit
U12C-36
Hit Output
146
N.C.
U12C-42
U12B-15
N.C.
56
147
N.C.
Ground
148
VSS
U12B-21
Byte 6, I/O 5
+5 Volts
Ground
64
VSS
65
DQ25
U6-18
Byte 2, I/O 7
149
DQ61
U7-18
Byte 6, I/O 7
66
DQ26
U5-7
Parity, I/O 2
150
DQ62
U5-16
Parity, I/O 6
67
DQ27
U8-4
Byte 3, I/O 0
151
DQ63
U9-4
Byte 7, I/O 0
68
VSS
Ground
152
VSS
DQ64
U9-6
Byte 7, I/O 1
Ground
69
DQ28
U8-6
Byte 3, I/O 1
153
70
DQ
U8-7
Byte 3, I/O 2
154
DQ65
U9-7
Byte 7, I/O 2
71
DQ
U8-9
Byte 3, I/O 3
155
DQ66
U9-9
Byte 7, I/O 3
72
DQ
U8-13
Byte 3, I/O 4
156
DQ
U9-13
Byte 7, I/O 4
73
V DD
+5 Volts
157
VSS
74
DQ
Byte 3, I/O 5
158
DQ68
U9-15
Byte 7, I/O 5
75
DQ
U8-16
Byte 3, I/O 6
159
DQ69
U9-16
Byte 7, I/O 6
76
DQ34
U8-18
Byte 3, I/O 7
160
DQ70
U9-18
Byte 7, I/O 7
77
DQ35
U5-9
Parity, I/O 3
161
DQ71
U5-18
Parity, I/O 7
78
V SS
Ground
162
VSS
79
N.C.
N.C.
163
N.C.
N.C.
N.C.
N.C.
29
30
31
32
33
U8-15
67
+5 Volts
Ground
80
N.C.
N.C.
164
81
N.C.
N.C.
165
N.C.
N.C.
82
N.C.
N.C.
166
N.C.
N.C.
83
VDD
+5 Volts
167
VDD
+5 Volts
84
VDD
+5 Volts
168
VDD
+5 Volts
2-143
Buffer Diagrams
DIMM Edge
Connector
U12A
U12D
2 QLE Bank0A
48
N.C.
47
N.C.
5 QLE Bank0C
45
N.C.
6 QLE Bank0D
44
N.C.
9
55
N.C.
54
N.C.
12 /RE Bank0C
52
N.C.
13 /RE Bank0D
51
58
N.C.
3 QLE Bank0B
42 QLE 8
43
/RE Bank0A
10 /RE Bank0B
45 /RE 14
49
1
U12B
U11A
16 BMO Bank0A
2
A2 Bank0A
3
A2 Bank0B
5
A2 Bank0C
20 BMO Bank0D
6
A2 Bank0D
23 BE Bank0A
9
A4 Bank0A
17 BMO Bank0B
147
15
19 BMO Bank0C
34
A2 8
24 BE Bank0B
63
21
26 BE Bank0C
10 A4 Bank0B
35 A4 14
12 A4 Bank0C
27 BE Bank0D
VDD
13 A4 BankOD
28
1
U12C
U11B
34 BM2 Bank0A
16 A6 Bank0A
33 BM2 Bank0B
145
36
31 BM2 Bank0C
17 A6 Bank0B
36 A6 15
19 A6 Bank0C
30 BM2 Bank0d
20 A6 Bank0D
41 BM1 Bank0A
23 A8 Bank0A
40 BM1 Bank0B
146
42
38 BM1 Bank0C
24 A8 Bank0B
37 A8 21
26 A8 Bank0C
37 BM1 Bank0D
VDD
27 A8 BankOD
29
28
Note: Address and control buffers add a minimum of 1.5ns and a maximum of 3.8ns delay to each signal path.
2-144
Buffer Diagrams
DIMM Edge
Connector
U11C
U10B
34 A10 Bank0A
33 A10 Bank0B
38 A10 36
31 A10 Bank0C
/G Bank0A
17
/G Bank0B
19
/G Bank0C
31 /G 15
30 A10 Bank0D
20 /G Bank0D
41 A9 Bank0A
23 A0 Bank0A
40 A9 Bank0B
121 A9 42
16
38 A9 Bank0C
24 A0 Bank0B
33 A0 21
37 A9 Bank0D
26 A0 Bank0C
27 A0 Bank0D
28
29
U11D
U10C
48 A7 Bank0A
34 A3 Bank0A
47 A7 Bank0B
120 A7 43
45 A7 Bank0C
33 A3 Bank0B
118 A3 36
31 A3 Bank0C
44 A7 Bank0D
30 A3 Bank0D
55 A5 Bank0A
41 A1 Bank0A
54 A5 Bank0B
119 A5 49
52 A5 Bank0C
40 A1 Bank0B
117 A1 42
51 A5 Bank0D
37 A1 Bank0D
29
58
30
IDT74FCT162344ETPA
U10D
U10A
27 /WE 8
38 A1 Bank0C
2 /WE Bank0A
48 W/R Bank0A
3 /WE Bank0B
47 W/R Bank0B
5 /WE Bank0C
115 W/R 43
45 W/R Bank0C
6 /WE Bank0D
44 W/R Bank0D
9
/S Bank0A
55
/F Bank0A
10
/S Bank0B
54
/F Bank0B
52
/F Bank0C
/S 14
12
/S Bank0C
VDD
111 /F 49
7 Vcc
11
22 Vcc
18
35 Vcc
25
50 Vcc
32
39
.22µf
13
51
/S Bank0D
/F BankOD
58
1
Note: Address and control buffers add a minimum of 1.5ns and a maximum of 3.8ns delay to each signal path.
2-145
4
46
53
W/R
/WE
/F
/S
/G
QLE
/RE
43
26
2
42
12
10
33
W/R
/WE
/F
/S
/G
QLE
/RE
HIT
32
DM2203T
/CAL
DM2203T
DM2203T
DM2203T
/CAL
Byte 5
Bank 0B
2-146
DM2203T
DM2203T
Bank 0C
DM2213T
4
6
7
9
13
15
16
18
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
4
6
7
9
13
15
16
18
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
4
6
7
9
13
15
16
18
U8
Byte 3
Bank 0C
DM2203T
/CAL0
/CAL4
/CAL1
/CAL5
/CAL2
/CAL6
/CAL8
/CAL3
/CAL 7
Note: For reference to buffer connection, append bank name to address or clock name, i.e., A10 + Bank 0A = A10BANK0A. Refer to Buffer Interconnect Diagram for
detailed buffer connections. DQ0-71 and /CAL0-8 are directly connected to pins.
* Not Present on DM512K64
/CAL
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
4
6
7
9
13
15
16
18
Parity
/CAL
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
4
6
7
9
13
15
16
18
U5*
32
Byte 2
Bank 0C
Byte 6
32
Bank 0B
U7
/CAL
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
4
6
7
9
13
15
16
18
U4
/CAL
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
U3
U6
32
Bank 0A
32
Bank 0A
32
Byte 4
Byte 1
/CAL
U2
/CAL
Byte 0
32
/HIT
U1
32
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
/CAL
27
28
29
30
35
36
37
38
39
40
41
HIT 24
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
32
4
6
7
9
13
15
16
18
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
4
6
7
9
13
15
16
18
4
6
7
9
13
15
16
18
0
1
2
3
4
5
6
7
DQ 63
DQ 64
DQ 65
DQ 66
DQ 67
DQ 68
DQ 69
DQ 70
DQ 27
DQ 28
DQ 29
DQ 30
DQ 31
DQ 32
DQ 33
DQ 34
DQ 8
DQ 17
DQ 26
DQ 35
DQ 44
DQ 53
DQ 62
DQ 71
DQ 54
DQ 55
DQ 56
DQ 57
DQ 58
DQ 59
DQ 60
DQ 61
DQ 18
DQ 19
DQ 20
DQ 21
DQ 22
DQ 23
DQ 24
DQ 25
DQ 45
DQ 46
DQ 47
DQ 48
DQ 49
DQ 50
DQ 51
DQ 52
DQ 9
DQ 10
DQ 11
DQ 12
DQ 13
DQ 14
DQ 15
DQ 16
DQ 36
DQ 37
DQ 38
DQ 39
DQ 40
DQ 41
DQ 42
DQ 43
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
Interconnect Diagram
DQ0-71
U9
Byte
* 7
Bank 0D
Bank 0D
DM2203T
Pin Names
Pin Names
Function
Pin Names
Function
A0-10
Address Inputs
/WE
Write Enable
/RE
Row Enable
/G
Output Enable
DQ0-71
Data In/Data Out
/F
Refresh Control
/CAL0-8
Column Address Latch
/S
Chip Select
W/R
Write/Read Control
/HIT
Hit Output
VCC
Power (+5V)
QLE
Output Latch Enable
VSS
Ground
NC
Not Connected
Absolute Maximum Ratings
Capacitance
(Beyond Which Permanent Damage Could Result)
Description
Ratings
Description
Input Voltage (VIN)
- 1 ~ VCC+1
Input Capacitance
14pf
A0-10
Output Voltage (VOUT)
- 1 ~ VCC+1
Input Capacitance
14pf
/CAL0-8
Input Capacitance
10pf
/G, QLE
Input Capacitance
14pf
W/R, /F
I/O Capacitance
15pf
DQ0-71
- 1 ~ 7v
Power Supply Voltage (VCC)
Ambient Operating Temperature (TA)
-40 ~ +70°C
Storage Temperature (TS)
-55 ~ 150°C
Max
Pins
Static Discharge Voltage
(Per MIL-STD-883 Method 3015)
Class 1
Input Capacitance
12pf
/RE, /S
Short Circuit O/P Current (IOUT)
50mA*
Input Capacitance
12pf
/HIT
*One output at a time; short duration.
AC Test Load and Waveforms
VIN Timing Reference Point at VIL and VIH
VOUT Timing Referenced to 1.5 Volts
5.0V
R1 = 828Ω
VIH
VIH
Output
R2 = 295Ω
CL = 50pf
GND
VIL
VIL
≤5ns
Load Circuit
Input Waveforms
2-147
≤5ns
Electrical Characteristics
TA = 0 - 70°C (Commercial)
Symbol
Parameters
Min
Max
VCC
Supply Voltage
4.75V
5.25V
VIH
Input High Voltage
2.4V
VCC+1
VIL
Input Low Voltage
-1.0V
0.8V
VOH
Output High Level
2.4V
VOL
Output Low Level
Vi(L)
Input Leakage Current
V0(L)
Output Leakage Current
Test Conditions
All Voltages Referenced to VSS
IOUT = - 5mA
0.4V
IOUT = 4.2mA
-90µA
90µA
0V ≤ VIN ≤ 6.5V, All Other Pins Not Under Test = 0V
-90µA
90µA
0V ≤ VIN, 0V ≤ VOUT ≤ 5.5V
DM512K72DT6
Symbol
Operating Current
33MHz Typ(1)
-12 Max
-15 Max
Test Condition
Notes
ICC1
Random Read
1166mA
2465mA
1970mA
/RE, /CAL, /G and Addresses Cycling: tC = tC Minimum
2, 3
ICC2
Fast Page Mode Read
761mA
1745mA
1385mA
/CAL, /G and Addresses Cycling: tPC = tPC Minimum
2, 4
ICC3
Static Column Read
671mA
1430mA
1160mA
/G and Addresses Cycling: tAC = tAC Minimum
2, 4
ICC4
Random Write
1391mA
2150mA
1700mA
/RE, /CAL, /WE and Addresses Cycling: tC = tC Minimum
2, 3
ICC5
Fast Page Mode Write
626mA
1655mA
1295mA
/CAL, /WE and Addresses Cycling: tPC = tPC Minimum
2, 4
ICC6
Standby
11mA
11mA
11mA
All Control Inputs Stable ≥ VCC - 0.2V, Outputs Driven
ICCT
Average Typical
Operating Current
446mA
—
—
See "Estimating EDRAM Operating Power" Application Note
1
33MHz Typ(1)
-12 Max
-15 Max
Test Condition
Notes
DM512K64DT6
Symbol
Operating Current
ICC1
Random Read
1056mA
2240mA
1790mA
/RE, /CAL, /G and Addresses Cycling: tC = tC Minimum
2, 3
ICC2
Fast Page Mode Read
696mA
1600mA
1270mA
/CAL, /G and Addresses Cycling: tPC = tPC Minimum
2, 4
ICC3
Static Column Read
616mA
1320mA
1070mA
/G and Addresses Cycling: tAC = tAC Minimum
2, 4
ICC4
Random Write
1256mA
1960mA
1550mA
/RE, /CAL, /WE and Addresses Cycling: tC = tC Minimum
2, 3
ICC5
Fast Page Mode Write
576mA
1520mA
1190mA
/CAL, /WE and Addresses Cycling: tPC = tPC Minimum
2, 4
ICC6
Standby
10mA
10mA
10mA
All Control Inputs Stable ≥ VCC - 0.2V, Outputs Driven
ICCT
Average Typical
Operating Current
416mA
—
—
See "Estimating EDRAM Operating Power" Application Note
1
(1) “33MHz Typ” refers to worst case ICC expected in a system operating with a 33MHz memory bus. See power applications note for further details. This parameter is not 100% tested
or guaranteed.
(2) ICC is dependent on cycle rates and is measured with CMOS levels and the outputs open.
(3) ICC is measured with a maximum of one address change while /RE = VIL
(4) ICC is measured with a maximum of one address change while /CAL = VIH
2-148
Switching Characteristics
Note: These parameters do not include buffer delays. See pages 2-144-5 for derating factors.VCC = 5V ± 5%, TA = 0 to 70°C, CL = 50pf
-12
Symbol
Description
Min
-15
Max
Min
Max
Units
tAC(1)
Column Address Access Time
tACH
Column Address Valid to /CAL Inactive (Write Cycle)
12
15
ns
tACI
Address Valid to /CAL Inactive (QLE High)
12
15
ns
tAHQ
Column Address Hold From QLE High (/CAL=H)
0
0
ns
tAQH
Address Valid to QLE High
12
15
ns
tAQX
Column Address Change to Output Data Invalid
5
5
ns
tASC
Column Address Setup Time
5
5
ns
tASR
Row Address Setup Time
5
5
ns
tC
Row Enable Cycle Time
55
65
ns
tC1
Row Enable Cycle Time, Cache Hit (Row=LRR), Read Cycle Only
20
25
ns
tCAE
Column Address Latch Active Time
5
6
ns
tCAH
Column Address Hold Time
0
0
ns
tCH
Column Address Latch High Time (Latch Transparent)
5
5
ns
tCHR
/CAL Inactive Lead Time to /RE Inactive (Write Cycles Only)
-2
-2
ns
tCHW
Column Address Latch High to Write Enable Low (Multiple Writes)
0
0
ns
tCLV
Column Address Latch Low to Data Valid (QLE High)
tCQH
Column Address Latch Low to Data Invalid (QLE High)
tCQV
Column Address Latch High to Data Valid
tCQX
Column Address Latch Inactive to Data Invalid
5
5
ns
tCRP
Column Address Latch Setup Time to Row Enable
5
5
ns
tCWL
/WE Low to /CAL Inactive
5
5
ns
tDH
Data Input Hold Time
0
0
ns
tDMH
Mask Hold Time From Row Enable (Write-Per-Bit)
1
1.5
ns
tDMS
Mask Setup Time to Row Enable (Write-Per-Bit)
5
5
ns
tDS
Data Input Setup Time
5
5
ns
tGQV(1)
(2,3)
12
15
7
0
7
0
15
ns
ns
15
5
Output Enable Access Time
ns
ns
5
ns
tGQX
Output Enable to Output Drive Time
0
5
0
5
ns
tGQZ(4,5)
Output Turn-Off Delay From Output Disabled (/G↑)
0
5
0
5
ns
tHV
Hit Valid From Row Enable
5
ns
tHZ
Hit Turn-Off From Row Enable Going High
0
0
ns
tMH
/F and W/R Mode Select Hold Time
0
0
ns
tMSU
/F and W/R Mode Select Setup Time
5
5
ns
tNRH
/CAL, /G, and /WE Hold Time For /RE-Only Refresh
0
0
ns
tNRS
/CAL, /G, and /WE Setup Time For /RE-Only Refresh
5
5
ns
tPC
Column Address Latch Cycle Time
12
15
ns
tQCI
QLE High to /CAL Inactive
0
0
ns
tQH
QLE High Time
5
5
ns
5
2-149
Switching Characteristics
Note: These parameters do not include buffer delays. See pages 2-144-5 for derating factors.VCC = 5V ± 5%, TA = 0 to 70°C, CL = 50pf
Symbol
-12
Description
Min
-15
Max
Min
Max
Units
tQL
QLE Low Time
5
5
ns
tQQH
Data Hold From QLE Inactive
2
2
ns
tQQV
Data Valid From QLE Low
7.5
7.5
ns
Row Enable Access Time, On a Cache Miss
30
35
ns
tRAC1
Row Enable Access Time, On a Cache Hit (Limit Becomes tAC)
15
17
ns
tRAH
Row Address Hold Time
1
tRE
Row Enable Active Time
30
tRE1
Row Enable Active Time, Cache Hit (Row=LRR) Read Cycle
tREF
Refresh Period
tRGX
Output Enable Don't Care From Row Enable (Write, Cache Miss), DQ = Hi-Z
9
tRQX1(2,5)
Row Enable High to Output Turn-On After Write Miss
0
tRP
Row Precharge Time
tRP1
tRAC(1)
(1)
1.5
100000
8
35
ns
100000
10
64
ns
64
10
12
ns
ms
ns
15
ns
20
25
ns
Row Precharge Time, Cache Hit (Row=LRR) Read Cycle
8
10
ns
tRRH
Write Enable Don’t Care From Row Enable (Write Only)
0
0
ns
tRSH
Last Write Address Latch to End of Write
12
15
ns
tRSW
Row Enable to Column Address Latch Low For Second Write
35
40
ns
tRWL
Last Write Enable to End of Write
12
15
ns
tSC
Column Address Cycle Time
12
15
ns
tSHR
Select Hold From Row Enable
0
0
ns
tSQV(1)
Chip Select Access Time
tSQX(2,3)
Output Turn-On From Select Low
0
12
(4,5)
tSQZ
Output Turn-Off From Chip Select
0
8
tSSR
Select Setup Time to Row Enable
5
tT
Transition Time (Rise and Fall)
1
tWC
Write Enable Cycle Time
tWCH
12
15
ns
0
15
ns
0
10
ns
5
10
1
ns
10
ns
12
15
ns
Column Address Latch Low to Write Enable Inactive Time
5
5
ns
tWHR(6)
Write Enable Hold After /RE
0
0
ns
tWI
Write Enable Inactive Time
5
5
ns
tWP
Write Enable Active Time
5
5
ns
(1)
tWQV
Data Valid From Write Enable High
tWQX(2,5)
Data Output Turn-On From Write Enable High
0
12
tWQZ(3,4)
Data Turn-Off From Write Enable Low
0
12
tWRP
Write Enable Setup Time to Row Enable
5
tWRR
Write to Read Recovery (Following Write Miss)
12
15
ns
0
15
ns
0
15
ns
ns
5
12
15
ns
(1) VOUT Timing Reference Point at 1.5V; (2) Parameter Defines Time When Output is Enabled (Sourcing or Sinking Current) and is Not Referenced to VOH or VOL; (3) Minimum Specification is Referenced from VIH and Maximum
Specification is Referenced from VIL on Input Control Signal; (4) Parameter Defines Time When Output Achieves Open-Circuit Condition and is Not Referenced to VOH or VOL; (5) Minimum Specification is Referenced from VIL and
Maximum Specification is Referenced from VIH on Input Control Signal; (6) On DM2213, tWHR Minimum is tDS
2-150
/RE Inactive Cache Read Hit (Static Column Mode)
/RE
/F
W/R
A0-7
A0-10
Column 1
Column 2
Column 3
t SC
t SC
t SC
Column 4
/CAL0-8
/WE
t AC
t AC
t AQX
t AQX
DQ0-71
Open
Data 1
t AC
t AC
t AQX
Data 2
Data 3
Data 4
t GQZ
t GQX
t GQV
/G
t SQX
t SQV
t SQZ
/S
/HIT
Open
Don’t Care or Indeterminate
NOTES: 1. Data accessed during /RE inactive read is from the row address specified during the last /RE active read cycle.
2-151
/RE Inactive Cache Read Hit (Page Mode)
/RE
/F
W/R
t CAH
A0-7
A0-10
Column 1
Column 2
t ASC
t CAH
t CAE
/CAL0-8
Row
t ASC
t CH
t PC
t CQV
/WE
t AC
t CQX
DQ0-71
Data 1
Data 2
t AC
t GQX
t GQZ
t GQV
/G
t SQX
t SQV
t SQZ
/S
/HIT
Open
Don’t Care or Indeterminate
NOTES: 1. Data accessed during /RE inactive read is from the row address specified during the last /RE active read cycle.
2-152
/RE Active Cache Read Hit (Static Column Mode)
t C1
t RE1
/RE
t RP1
t MSU
t MH
/F
t MSU
t MH
W/R
t ASR
t RAH
A0-10
A0-7
Row
Column 1
Column 2
t SC
Column 3
t SC
t SC
Column 4
t CRP
/CAL0-8
/WE
t AC
t RAC1
DQ0-71
t AC
t AQX
t AQX
Open
Data 1
t AC
t AC
t AQX
Data 2
Data 3
Data 4
t GQX
t GQZ
t GQV
/G
t SHR
t SSR
t SQZ
/S
t HV
/HIT
t HZ
Open
Open
Don’t Care or Indeterminate
2-153
/RE Active Cache Read Hit (Page Mode)
t C1
t RE1
/RE
t RP1
t MSU
t MH
/F
t MSU
t MH
W/R
t ASR
t RAH
A0-10
Row
t CAH
A0-7
Column 1
Column 2
t ASC
t CRP
t CAH
t CAE
/CAL0-8
Row
t ASC
t CH
t PC
t CQV
/WE
t AC
t RAC1
DQ0-71
t CQX
Open
Data 1
Data 2
t AC
t GQX
t GQZ
t GQV
/G
t SHR
t SSR
t SQZ
/S
t HV
/HIT
t HZ
Open
Open
Don’t Care or Indeterminate
2-154
/RE Active Cache Read Miss (Static Column Mode)
tC
t RE
/RE
t RP
t MSU
t MH
/F
t MSU
t MH
W/R
t ASR
A0-10
t RAH
t SC
A0-7
Row
A0-10
A0-7
Column 1
A0-10
Column 2
Row
t CRP
/CAL0-8
t AQX
/WE
t AC
t AC
t RAC
DQ0-71
t AQX
Open
Data 1
Data 2
t GQX
t GQV
t GQZ
/G
t SHR
t SSR
t SQZ
/S
t HV
/HIT
t HZ
Open
Open
Don’t Care or Indeterminate
2-155
/RE Active Cache Read Miss (Page Mode)
tC
t RE
/RE
t RP
t MSU
t MH
/F
t MSU
t MH
W/R
t ASR
A0-10
t RAH
Row
A0-10
A0-7
t CAH
A0-7
Column 1
A0-10
Column 2
t ASC
Row
t ASC
t CRP
t CAH
t CAE
/CAL
t CH
t PC
t CQV
/WE
t AC
t CQX
t RAC
Open
DQ0-71
Data 1
Data 2
t AC
t GQZ
/G
t SSR
t GQX
t SHR
t GQV
t SQZ
/S
t HV
/HIT
t HZ
Open
Open
Don’t Care or Indeterminate
2-156
Output Latch Enable Operation (Static Column EDO Mode Read)
/CAL0-8
t AC
A 0-7
t AC
Column 1
Column 2
t AQX
t AHQ
DQ 0-71
t QQH
Data 1
t AQH
Data 2
t QQV
t QL
QLE
t QH
Output Latch Enable Operation (Page Mode EDO Read)
t PC
t QCI
t CAE
/CAL0-8
t ACI
t CLV
t AC
A 0-7
t CH
t AC
Column 1
Column 2
t AQX
t CQH
DQ 0-71
Data 1
Data 2
t CQV
QLE
Output Latch Enable Operation (Asynchronous Access)
t PC
t CAE
t CH
/CAL0-8
t QCI
t ACI
A 0-7
t ACI
t ACI
Column 1
Column 2
t CQV
Column 3
t CQV
t AC
t AC
t AC
DQ 0-71
Data 1
t QQH
t QQV
Data 2
t QQV
t QQV
QLE
t QQH
Data 3
t QL
t QH
2-157
Burst Write (Hit or Miss) Followed By /RE Inactive Cache Reads
t RE
/RE
t MSU
t RP
t MH
/F
t MSU
t MH
W/R
t ASR
t RAH
A0-7
A0-10
Row
t CAH
t RSW
A0-7
Column 1
A0-10
t ASC
t CRP
t CAH
/CAL0-8
t ACH
t CAE
t WCH
t WRP
DQ0-71
Open
t CAE
t CH
t PC
t CHW
t CWL
t CHR
t WCH
t RRH
t WP
/WE
t DS
Column n
t RSH
t CWL
t WP
t WHR
A0-7
Column 2
t ACH
t WC
t DH
t WI
t RWL
t DH
t DS
Data 1
Data 2
t WRR
t AC
Cache (Column n)
t GQX
/G
t GQV
t SSR
/S
t HV
/HIT
t HZ
Open
Open
Don’t Care or Indeterminate
NOTES: 1. /G becomes a don’t care after tRGX during a write miss.
2-158
Read/Write During Write Hit Cycle (Can Include Read-Modify-Write)
tC
t RE
/RE
t RP
t MSU
t MH
/F
t MSU
t MH
W/R
t ASR
t RAH
A0-10
Row
A0-7
Column 1
t CRP
t AC
t CAH
Column 2
t ACH
t ASC
Column 3
t RSH
t CAE
/CAL0-8
t CHR
t WCH
t CQV
t CWL
t WRP
/WE
t WHR
t AC
DQ0-71
t AQX
t RWL
t DS
Read Data
t GQX
t RRH
t WP
t WQV
Write Data
t DH
t GQZ
t GQV
Read Data
t GQZ
t WQX
t GQV
/G
t SSR
/S
t HV
/HIT
t HZ
Open
Open
Don’t Care or Indeterminate
NOTES: 1. If column address one equals column address two, then a read-modify-write cycle is performed.
2-159
Write-Per-Bit Cycle (/G=High)
t RE
t RP
/RE
t CHR
t RSH
t ACH
t CAE
/CAL
0-8
t RAH
t ASR
A0-10
t ASC
t CAH
A0-7
Row
Column
t MSU
t MH
t CWL
W/R
t DMS
DQ0-71
t RWL
t WCH
t DMH
Mask
Data
t DS
t WRP
t DH
/WE
t RRH
t WP
t WHR
t MSU
/F
t SSR
t MH
t SHR
/S
t HV
/HIT
t HZ
Open
Open
Don’t Care or Indeterminate
NOTES: 1. Data mask bit high (1) enables bit write; data mask bit low (0) inhibits bit write.
2. Write-per-bit cycle valid only for DM512K72DT6.
2-160
/F Refresh Cycle
t RE
/RE
t MSU
t RP
t MH
/F
Don’t Care or Indeterminate
NOTES: 1. During /F refresh cycles, the status of W/R, /WE, A0-10, /CAL, /S, and /G is a don’t care.
2. /RE inactive cache reads may be performed in parallel with /F refresh cycles.
/RE-Only Refresh
t RE
/RE
tC
t RP
t ASR
t RAH
A0-10
ROW
t NRS
t NRH
/CAL , /WE, /G
0-8
t MSU
W/R, /F
t MH
t SSR
t SHR
/S
t HV
/HIT
t HZ
Open
Open
Don’t Care or Indeterminate
NOTES: 1. All binary combinations of A0-9 must be refreshed every 64ms interval. A10 does not have to be cycled, but must remain valid
during row address setup and hold times.
2. /RE refresh is write cycle with no /CAL active cycle.
2-161
Mechancial Data
168 Pin DIMM Module Configuration
Inches (mm)
5.250(133.35)
U1
C1
U1
U2
C2
U3
U2
C3
U4
U3
C4
U4
U5
C5
U5
U6
C6
U77
U6
C7
U7
U8
C8
U9
U8
C9
.104 (2.64)
U9
C12
R3
U11
R1
U12
C12
C11
U10
C11
C10
C10
1.500
R2
0.700
.050 (1.27)
2.585 (65.66)
0.050 (1.27)
0.040 (1.04)
U1-4, U6-9 —
U5 —
U10-12 —
C1-12 —
Socket —
Enhanced DM2203T-xx, 512Kx8 EDRAM, 300 Mil TSOP
Enhanced DM2213T-xx, 512Kx8 EDRAM with Write-per-bit (not present on DM512K64DT)
IDT 74FCT162344ETPA Address/Clock Driver or Equivalent
0.22µF Chip Capacitor
Robinson Nugent DIMS - 168BD5-TR or Equivalent
Part Numbering System
DM512K72DT 6- 12 N
Error Check Mode (72-bit Only)
Blank - Write-per-bit Parity
N - ECC (No Write-per-bit)
Access Time from Cache in Nanoseconds
12ns
15ns
Packaging System
T = 300 Mil, Plastic TSOP - II
Memory Module Configuration
D= DIMM
I/O Width
64 = 64 Bits
72 = 72 Bits
Memory Depth
512K
1M
Dynamic Memory
The information contained herein is subject to change without notice. Enhanced Memory Systems Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in
an Enhanced product, nor does it convey or imply any license under patent or other rights.
2-162