Rev 1; 4/05 Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors and Password Protection The DS1856 dual, temperature-controlled, nonvolatile (NV) variable resistors with three monitors consists of two 256-position, linear, variable resistors; three analog monitor inputs (MON1, MON2, MON3); and a direct-todigital temperature sensor. The device provides an ideal method for setting and temperature-compensating bias voltages and currents in control applications using minimal circuitry. The variable resistor settings are stored in EEPROM memory and can be accessed over the 2-wire serial bus. Relative to other members of the family, the DS1856 is essentially a DS1859 with a DS1852-friendly memory map. In particular, the DS1856 can be configured so the 128 bytes of internal Auxiliary EEPROM memory is mapped into Main Device Table 00h and Table 01h, maintaining compatibility between both the DS1858/DS1859 and the DS1852. The DS1856 also features password protection equivalent to the DS1852, further enhancing compatibility between the two. Applications Features ♦ SFF-8472 Compatible ♦ Five Monitored Channels (Temperature, VCC, MON1, MON2, MON3) ♦ Three External Analog Inputs (MON1, MON2, MON3) That Support Internal and External Calibration ♦ Scalable Dynamic Range for External Analog Inputs ♦ Internal Direct-to-Digital Temperature Sensor ♦ Alarm and Warning Flags for All Monitored Channels ♦ Two Linear, 256-Position, Nonvolatile TemperatureControlled Variable Resistors ♦ Resistor Settings Changeable Every 2°C ♦ Three Levels of Security ♦ Access to Monitoring and ID Information Configurable with Separate Device Addresses ♦ 2-Wire Serial Interface ♦ Two Buffers with TTL/CMOS-Compatible Inputs and Open-Drain Outputs ♦ Operates from a 3.3V or 5V Supply ♦ -40°C to +95°C Operating Temperature Range Optical Transceivers Ordering Information Optical Transponders Instrumentation and Industrial Controls RES0/RES1 RESISTANCE (kΩ) PART RF Power Amps Diagnostic Monitoring Typical Operating Circuit VCC VCC = 3.3V 4.7kΩ 4.7kΩ 1 2-WIRE INTERFACE 2 3 Tx-FAULT 4 0.1µF VCC SDA H1 SCL L1 OUT1 H0 IN1 5 LOS OUT2 DS1856 L0 6 7 8 IN2 MON3 N.C. MON2 GND MON1 16 15 14 13 12 DS1856E-050 50/50 16 TSSOP DS1856E-050/T&R 50/50 16 TSSOP DS1856B-050 50/50 16-Ball CSBGA Ordering Information continued at end of data sheet. +Denotes lead free. *Future product—contact factory for availability. T&R denotes tape-and-reel. All parts operate at the -40°C to +95°C temperature range. DECOUPLING CAPACITOR TO LASER BIAS CONTROL TO LASER MODULATION CONTROL Pin Configurations TOP VIEW A B IN1 OUT2 SCL SDA VCC H0 H1 9 Tx BIAS* 16 VCC SCL 2 15 H1 OUT1 3 14 L1 IN1 4 DIAGNOSTIC INPUTS C D *SATISFIES SFF-8472 COMPATIBILITY SDA 1 L1 11 Rx POWER* 10 Tx POWER* PIN-PACKAGE N.C. GND 1 IN2 L0 2 OUT1 MON1 3 MON3 MON2 DS1856 13 H0 12 L0 OUT2 5 IN2 6 11 MON3 N.C. 7 10 MON2 GND 8 9 MON1 4 CSBGA (4mm x 4mm) 1.0mm PITCH TSSOP ______________________________________________ Maxim Integrated Products For pricing delivery, and ordering information please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 DS1856 General Description DS1856 Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors and Password Protection ABSOLUTE MAXIMUM RATINGS Voltage Range on VCC Relative to Ground ...........-0.5V to +6.0V Voltage Range on Inputs Relative to Ground* ..............................................-0.5V to (VCC + 0.5V) Voltage Range on Resistor Inputs Relative to Ground* ..............................................-0.5V to (VCC + 0.5V) Current into Resistors............................................................5mA Operating Temperature Range ...........................-40°C to +95°C Programming Temperature Range .........................0°C to +70°C Storage Temperature Range .............................-55°C to +125°C Soldering Temperature .......................................See IPC/JEDEC J-STD-020A *Not to exceed 6.0V. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS (TA = -40°C to +95°C, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 5.50 V VCC + 0.3 V -0.3 +0.3 x VCC V -0.3 VCC + 0.3 V +3 mA Supply Voltage VCC (Note 1) 2.85 Input Logic 1 (SDA, SCL) VIH (Note 2) 0.7 x Vcc Input Logic 0 (SDA, SCL) VIL (Note 2) Resistor Inputs (L0, L1, H0, H1) Resistor Current High-Impedance Resistor Current IRES -3 IROFF 0.001 Input logic 1 Input Logic Levels (IN1, IN2) 0.1 1.6 Input logic 0 0.9 µA V DC ELECTRICAL CHARACTERISTICS (VCC = 2.85V to 5.5V, TA = -40°C to +95°C, unless otherwise noted.) PARAMETER Supply Current Input Leakage SYMBOL ICC CONDITIONS MIN (Note 3) MAX 2 UNITS mA nA -200 +200 VOL1 3mA sink current 0 0.4 VOL2 6mA sink current 0 0.6 Full-Scale Input (MON1, MON2, MON3) At factory setting (Note 4) 2.4875 2.5 2.5125 V Full-Scale VCC Monitor At factory setting (Note 5) 6.5208 6.5536 6.5864 V Low-Level Output Voltage (SDA, OUT1, OUT2) IIL TYP 1 V I/O Capacitance CI/O 10 pF Digital Power-On Reset POD 1.0 2.2 V Analog Power-On Reset POA 2.0 2.6 V 2 _____________________________________________________________________ Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors and Password Protection DS1856 ANALOG RESISTOR CHARACTERISTICS (VCC = 2.85V to 5.5V, TA = -40°C to +95°C, unless otherwise noted.) MIN TYP MAX Position 00h Resistance (50kΩ) PARAMETER TA = +25°C CONDITIONS 0.65 1.0 1.35 UNITS kΩ Position FFh Resistance (50kΩ) TA = +25°C 40 50 60 kΩ Position 00h Resistance (30kΩ) TA = +25°C 0.40 Position FFh Resistance (30kΩ) TA = +25°C 30 Position 00h Resistance (20kΩ) TA = +25°C 0.20 Position FFh Resistance (20kΩ) TA = +25°C 15 Position 00h Resistance (10kΩ) TA = +25°C 0.40 kΩ Position FFh Resistance (10kΩ) TA = +25°C 10 kΩ Position 00h Resistance (2.5kΩ) TA = +25°C 0.1 0.175 0.250 Position FFh Resistance (2.5kΩ) TA = +25°C 2.0 2.50 3.0 kΩ Absolute Linearity (Note 6) -2 +2 LSB Relative Linearity (Note 7) -1 Temperature Coefficient (Note 8) kΩ kΩ 0.40 0.55 kΩ 20 25 kΩ +1 50 kΩ LSB ppm/°C ANALOG VOLTAGE MONITORING (VCC = 2.85V to 5.5V, TA = -40°C to +95°C, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS ∆VMON 610 µV Supply Resolution ∆VCC 1.6 mV Input/Supply Accuracy (MON1, MON2, MON3, VCC) ACC Input Resolution Update Rate for MON1, MON2, MON3, Temp, or VCC At factory setting tframe Input/Supply Offset (MON1, MON2, MON3, VCC) VOS (Note 14) 0.25 0.5 % FS (full scale) 47 60 ms 0 5 LSB TYP MAX UNITS ±3.0 °C DIGITAL THERMOMETER (VCC = 2.85V to 5.5V, TA = -40°C to +95°C, unless otherwise noted.) PARAMETER Thermometer Error SYMBOL TERR CONDITIONS MIN -40°C to +95°C NONVOLATILE MEMORY CHARACTERISTICS (VCC = 2.85V to 5.5V) PARAMETER EEPROM Writes SYMBOL CONDITIONS +70°C (Note 14) MIN 50,000 TYP MAX UNITS Writes _____________________________________________________________________ 3 DS1856 Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors and Password Protection AC ELECTRICAL CHARACTERISTICS (VCC = 2.85V to 5.5V, TA = -40°C to +95°C, unless otherwise noted. See Figure 6.) PARAMETER SYMBOL SCL Clock Frequency (Note 9) fSCL Bus Free Time Between STOP and START Condition (Note 9) tBUF Hold Time (Repeated) START Condition (Notes 9, 10) tHD:STA LOW Period of SCL Clock (Note 9) tLOW HIGH Period of SCL Clock (Note 9) tHIGH Data Hold Time (Notes 9, 11, 12) tHD:DAT Data Setup Time (Note 9) tSU:DAT START Setup Time (Note 9) tSU:STA Rise Time of Both SDA and SCL Signals (Note 13) tR Fall Time of Both SDA and SCL Signals (Note 13) tF Setup Time for STOP Condition tSU:STO Capacitive Load for Each Bus Line CB EEPROM Write Time tW Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8: Note 9: 4 CONDITIONS MIN TYP MAX Fast mode 0 400 Standard mode 0 100 Fast mode 1.3 Standard mode 4.7 Fast mode 0.6 Standard mode 4.0 Fast mode 1.3 Standard mode 4.7 Fast mode 0.6 Standard mode 4.0 Fast mode 0 Standard mode 0 Fast mode 100 Standard mode 250 Fast mode 0.6 Standard mode 4.7 µs µs µs 0.9 µs 300 Standard mode 20 + 0.1CB 1000 Fast mode 20 + 0.1CB 300 Standard mode 20 + 0.1CB 300 0.6 4.0 µs ns 20 + 0.1CB Standard mode kHz µs Fast mode Fast mode UNITS ns ns µs (Note 13) 10 400 pF 20 ms All voltages are referenced to ground. I/O pins of fast-mode devices must not obstruct the SDA and SCL lines if VCC is switched off. SDA and SCL are connected to VCC and all other input signals are connected to well-defined logic levels. Full scale is user programmable. The maximum voltage that the MON inputs read is approximately full scale, even if the voltage on the inputs is greater than full scale. This voltage defines the maximum range of the analog-to-digital converter voltage, not the maximum V CC voltage. Absolute linearity is the difference of measured value from expected value at DAC position. The expected value is a straight line from measured minimum position to measured maximum position. Relative linearity is the deviation of an LSB DAC setting change vs. the expected LSB change. The expected LSB change is the slope of the straight line from measured minimum position to measured maximum position. See the Typical Operating Characteristics. A fast-mode device can be used in a standard-mode system, but the requirement tSU:DAT > 250ns must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tRMAX + tSU:DAT = 1000ns + 250ns = 1250ns before the SCL line is released. _____________________________________________________________________ Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors and Password Protection Typical Operating Characteristics (VCC = 5.0V, TA = +25°C, for both 50kΩ and 20kΩ versions, unless otherwise noted.) SUPPLY CURRENT vs. VOLTAGE 700 50kΩ VERSION 50 700 RESISTANCE (kΩ) SUPPLY CURRENT (µA) 750 SDA = SCL = VCC 750 RESISTANCE vs. SETTING 60 DS1856 toc02 DS1856 toc01 SDA = SCL = VCC 650 600 550 30 20 500 650 10 450 600 400 -20 0 20 40 60 80 100 0 3.0 3.5 4.0 4.5 5.0 TEMPERATURE (°C) VOLTAGE (V) RESISTANCE vs. SETTING ACTIVE SUPPLY CURRENT vs. SCL FREQUENCY 15 10 5 0 50 100 150 200 250 SETTING (DEC) 800 RESISTOR 0 INL (LSB) 1.0 SDA = VCC 780 0.8 0.6 RESISTOR 0 INL (LSB) 20kΩ VERSION 5.5 DS1856 toc05 DS1856 toc04 20 ACTIVE SUPPLY CURRENT (µA) -40 RESISTANCE (kΩ) 40 760 740 DS1856 toc06 SUPPLY CURRENT (µA) 800 DS1856 toc03 SUPPLY CURRENT vs. TEMPERATURE 800 0.4 0.2 0 -0.2 -0.4 -0.6 720 -0.8 0 -1.0 700 0 50 100 150 SETTING (DEC) 200 250 0 100 200 300 SCL FREQUENCY (kHz) 400 0 25 50 75 100 125 150 175 200 225 250 SETTING (DEC) _____________________________________________________________________ 5 DS1856 Note 10: After this period, the first clock pulse is generated. Note 11: The maximum tHD:DAT only has to be met if the device does not stretch the LOW period (tLOW) of the SCL signal. Note 12: A device must internally provide a hold time of at least 300ns for the SDA signal (see the VIH MIN of the SCL signal) to bridge the undefined region of the falling edge of SCL. Note 13: CB—total capacitance of one bus line, timing referenced to 0.9 x VCC and 0.1 x VCC. Note 14: Guaranteed by design. Typical Operating Characteristics (continued) (VCC = 5.0V, TA = +25°C, for both 50kΩ and 20kΩ versions, unless otherwise noted.) RESISTOR 0 DNL (LSB) RESISTOR 1 INL (LSB) 0 -0.2 -0.4 0.8 0.6 0.4 0.2 0 -0.2 -0.4 0.4 0.2 0 -0.2 -0.4 -0.6 -0.6 -0.6 -0.8 -0.8 -0.8 -1.0 -1.0 25 50 75 100 125 150 175 200 225 250 25 50 75 100 125 150 175 200 225 250 0 SETTING (DEC) SETTING (DEC) RESISTANCE vs. POWER-UP VOLTAGE RESISTANCE vs. POWER-UP VOLTAGE POSITION 00h RESISTANCE vs. TEMPERATURE PROGRAMMED RESISTANCE (80h) 60 100 RESISTANCE (kΩ) 90 80 50 40 30 20 10 0 20kΩ VERSION 1.01 50kΩ VERSION 1.00 90 80 RESISTANCE (kΩ) 100 >1MΩ 110 DS1856 toc11 50kΩ VERSION 70 120 DS1856 toc10 >1MΩ 70 60 PROGRAMMED RESISTANCE (80h) 50 40 30 20 1 2 3 POWER-UP VOLTAGE (V) 4 5 0.99 0.98 0.97 10 0 0 25 50 75 100 125 150 175 200 225 250 SETTING (DEC) 120 110 -1.0 0 DS1856 toc12 0.2 DS1856 toc09 0.6 RESISTOR 1 DNL (LSB) 0.4 0 6 0.8 RESISTOR 1 INL (LSB) RESISTOR 0 DNL (LSB) 0.6 1.0 DS1856 toc08 0.8 RESISTOR 1 DNL (LSB) 1.0 DS1856 toc07 1.0 RESISTANCE (kΩ) DS1856 Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors and Password Protection 0.96 0 1 2 3 4 5 POWER-UP VOLTAGE (V) _____________________________________________________________________ -40 -25 -10 5 20 35 50 TEMPERATURE (°C) 65 80 95 Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors and Password Protection POSITION FFh RESISTANCE vs. TEMPERATURE 20kΩ VERSION 0.37 50kΩ VERSION 49.75 20.00 DS1856 toc14 50.00 DS1856 toc13 0.38 POSITION FFh RESISTANCE vs. TEMPERATURE 20kΩ VERSION 19.80 RESISTANCE (kΩ) RESISTANCE (kΩ) 0.35 49.25 49.00 48.75 19.60 19.40 48.50 0.34 19.20 48.25 0.33 48.00 5 20 35 50 65 95 80 19.00 -40 -25 -10 TEMPERATURE (°C) 5 20 35 50 -40 -25 -10 50kΩ VERSION 350 300 250 +25°C TO +95°C +25°C TO -40°C 200 150 100 50 0 -50 -100 100 150 200 5 20 35 50 65 80 95 TEMPERATURE (°C) 800 TEMPERATURE COEFFICIENT (ppm/°C) DS1856 toc16 TEMPERATURE COEFFICIENT (ppm/°C) 95 TEMPERATURE COEFFICIENT vs. SETTING TEMPERATURE COEFFICIENT vs. SETTING 50 80 TEMPERATURE (°C) 400 0 65 DS1856 toc17 -40 -25 -10 20kΩ VERSION 700 600 500 +25°C TO +95°C +25°C TO -40°C 400 300 200 100 0 -100 250 0 SETTING (DEC) 50 100 150 250 200 SETTING (DEC) LSB ERROR vs. FULL-SCALE INPUT LSB ERROR vs. FULL-SCALE INPUT +3 SIGMA DS1856 toc19 3 DS1856 toc18 6 5 4 3 2 1 0 -1 -2 -3 -4 -5 -6 -7 -8 +3 SIGMA 2 1 LSB ERROR LSB ERROR RESISTANCE (kΩ) 49.50 0.36 DS1856 toc15 POSITION 00h RESISTANCE vs. TEMPERATURE MEAN MEAN 0 -1 -2 -3 SIGMA -3 -3 SIGMA -4 0 25 50 75 NORMALIZED FULL SCALE (%) 100 0 3.125 6.250 9.375 12.500 NORMALIZED FULL SCALE (%) _______________________________________________________________________________________ 7 DS1856 Typical Operating Characteristics (continued) (VCC = 5.0V, TA = +25°C, for both 50kΩ and 20kΩ versions, unless otherwise noted.) DS1856 Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors and Password Protection Pin Description PIN BALL NAME FUNCTION 1 B2 SDA 2 A2 SCL 3 C3 OUT1 4 A1 IN1 5 B1 OUT2 6 C2 IN2 TTL/CMOS-Compatible Input to Buffer 7 C1 N.C. No Connection 8 D1 GND Ground 9 D3 MON1 External Analog Input 10 D4 MON2 External Analog Input 11 C4 MON3 External Analog Input 12 D2 L0 Low-End Resistor 0 Terminal. It is not required that the low-end terminals be connected to a potential less than the high-end terminals of the corresponding resistor. Voltage applied to any of the resistor terminals cannot exceed the power-supply voltage, VCC, or go below ground. 13 B3 H0 High-End Resistor 0 Terminal. It is not required that the high-end terminals be connected to a potential greater than the low-end terminals of the corresponding resistor. Voltage applied to any of the resistor terminals cannot exceed the power-supply voltage, VCC, or go below ground. 14 B4 L1 Low-End Resistor 1 Terminal 15 A4 H1 High-End Resistor 1 Terminal 16 A3 VCC Supply Voltage 2-Wire Serial Data I/O Pin. Transfers serial data to and from the device. 2-Wire Serial Clock Input. Clocks data into and out of the device. Open-Drain Buffer Output TTL/CMOS-Compatible Input to Buffer Open-Drain Buffer Output Detailed Description The user can read the registers that monitor the VCC, MON1, MON2, MON3, and temperature analog signals. After each signal conversion, a corresponding bit is set that can be monitored to verify that a conversion has occurred. The signals also have alarm and warning flags that notify the user when the signals go above or below the user-defined value. Interrupts can also be set for each signal. 8 The position values of each resistor can be independently programmed. The user can assign a unique value to each resistor for every 2°C increment over the -40°C to +102°C range. Two buffers are provided to convert logic-level inputs into open-drain outputs. Typically, these buffers are used to implement transmit (Tx) fault and loss-of-signal (LOS) functionality. Additionally, OUT1 can be asserted in the event that one or more of the monitored values go beyond user-defined limits. _____________________________________________________________________ Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors and Password Protection MD MD DS1856 AD MD AD (AUXILIARY DEVICE ENABLE A0h) EEPROM 128 x 8 BIT STANDARDS TABLE SELECT DEVICE ADDRESS MD (MAIN DEVICE ENABLE) DEVICE ADDRESS IF ADEN = 0, [00h - 7Fh OF AD] IF ADEN = 1, [80h-FFh OF MD, TABLE 00/01h] ADDRESS R/W ADEN ADFIX SDA TABLE SELECT TABLE SELECT EEPROM 72 x 8 BIT 80h-C7h ADDRESS ADDRESS TABLE 04 RESISTOR 0 LOOK-UP TABLE R/W EEPROM 72 x 8 BIT 80h-C7h TABLE 05 RESISTOR 1 LOOK-UP TABLE R/W ADDRESS 2-WIRE INTERFACE ADEN (BIT) TEMP INDEX DATA BUS SCL TEMP INDEX R/W TxF Tx FAULT MD OUT1 MINT R/W EEPROM 96 x 8 BIT 00h-5Fh LIMITS TxF SRAM 32 x 8 BIT 60h-7Fh MONITORS LIMIT LOW H0 REGISTER MONITORS LIMIT HIGH ADDRESS RESISTOR 0 256 POSITIONS L0 TEMP INDEX INV1 RxL OUT2 LOS H1 REGISTER IN1 MINT (BIT) RESISTOR 1 256 POSITIONS L1 TABLE SELECT MEASUREMENT INV2 RIGHT SHIFTING WARNING FLAGS MD R/W ALARM FLAGS INV1 (BIT) IN2 TABLE SELECT VCC INTERNAL CALIBRATION INTERNAL TEMP ADDRESS DEVICE ADDRESS VENDOR DS1856 MUX MON1 ADC 12-BIT INV2 (BIT) TABLE 03 EEPROM 80h-B7h ADEN (BIT) ADFIX (BIT) MON2 MON3 MONITORS LIMIT HIGH A/D CTRL VCC MUX CTRL MONITORS LIMIT LOW MINT MEASUREMENT INTERRUPT VCC GND MASKING (TMP, VCC, MON1, MON2, MON3) COMP CTRL WARNING FLAGS COMPARATOR ALARM FLAGS Figure 1. Block Diagram _____________________________________________________________________ 9 DS1856 Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors and Password Protection Table 1. Scales for Monitor Channels at Factory Setting Table 3. Look-Up Table Address for Corresponding Temperature Values +FS SIGNAL +FS (hex) -FS SIGNAL -FS (hex) TEMPERATURE (°C) Temperature +127.984° 7FFC -128°C 8000 SIGNAL <-40 80h VCC 6.5528V FFF8 0V 0000 -40 80h MON1 2.4997V FFF8 0V 0000 -38 81h MON2 2.4997V FFF8 0V 0000 -36 82h MON3 2.4997V FFF8 0V 0000 -34 83h — — Table 2. Signal Comparison SIGNAL FORMAT VCC Unsigned MON1 Unsigned MON2 Unsigned MON3 Unsigned Temperature Two’s complement +98 C5h +100 C6h +102 C7h >+102 C7h Monitor Conversion Example Monitored Signals Each signal (VCC, MON1, MON2, MON3, and temperature) is available as a 16-bit value with 12-bit accuracy (left-justified) over the serial bus. See Table 1 for signal scales and Table 2 for signal format. The four LSBs should be masked when calculating the value. The 3 LSBs are internally masked with 0s. The signals are updated every frame rate (tframe) in a round-robin fashion. The comparison of all five signals with the high and low user-defined values are done automatically. The corresponding flags are set to 1 within a specified time of the occurrence of an out-of-limit condition. Calculating Signal Values The LSB = 100µV for VCC, and the LSB = 38.147µV for the MON signals when using factory default settings. Monitor/VCC Bit Weights MSB 215 214 213 212 211 210 29 28 LSB 27 26 25 24 23 22 21 20 VCC Conversion Examples 10 CORRESPONDING LOOK-UP TABLE ADDRESS MSB (BIN) LSB (BIN) VOLTAGE (V) 11000000 00000000 1.875 10000000 10000000 1.255 To calculate VCC, convert the unsigned 16-bit value to decimal and multiply by 100µV. To calculate MON1, MON2, or MON3, convert the unsigned 16-bit value to decimal and multiply by 38.147µV. To calculate the temperature, treat the two’s complement value binary number as an unsigned binary number, then convert to decimal and divide by 256. If the result is greater than or equal to 128, subtract 256 from the result. Temperature: high byte: -128°C to +127°C signed; low byte: 1/256°C. Temperature Bit Weights S 26 25 24 23 22 21 20 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 Temperature Conversion Examples MSB (BIN) LSB (BIN) TEMPERATURE (°C) 01000000 00000000 +64 00001111 +64.059 MSB (BIN) LSB (BIN) VOLTAGE (V) 01000000 10000000 10000000 3.29 01011111 00000000 +95 11000000 11111000 4.94 11110110 00000000 -10 11011000 00000000 -40 ____________________________________________________________________ Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors and Password Protection ADEN (ADDRESS ENABLE) NO. OF SEPARATE DEVICE ADDRESSES ADDITIONAL INFORMATION 0 2 See Figure 2 1 1 (Main Device Only) See Figure 3 DEC HEX 2-WIRE ADDRRESS A0h 0 0 00h DEC HEX 0 0 AUXILIARY DEVICE AUXILIARY DEVICE ADEN ADFIX AUXILIARY ADDRESS MAIN ADDRESS 0 0 A0h A2h 0 1 A0h EEPROM (Table 03, 8Ch) 1 0 — A2h 1 1 — EEPROM (Table 03, 8Ch) 2-WIRE ADDRESS A2h (DEFAULT) 00h MAIN DEVICE MAIN DEVICE EEPROM AUXILIARY MEMORY (128 BYTES) Table 5. ADEN and ADFIX Bits LOWER MEMORY NOTE 1: ADEN BIT = 0. AUXILIARY MEMORY IS ADDRESSED USING THE AUXILIARY DEVICE NOTE 1. 2-WIRE SLAVE ADDRESS OF A0h, AND THE REMAINDER OF THE MEMORY IS NOTE 1. ADDRESSED USING THE MAIN DEVICE 2-WIRE SLAVE ADDRESS OF A2h NOTE 1. (WHEN ADFIX = 0). NOTE 2: TABLES 00h, 01h, AND 02h DO NOT EXIST. PASSWORD ENTRY (PWE) (4 BYTES) 127 7F 7Fh 127 7F 128 80 183 B7 199 200 C7 C8 TABLE SELECT BYTE 7Fh 80h 80h 80h TABLE 03h TABLE 04h TABLE 05h CONFIGURATION TABLE RESISTOR 0 LOOK-UP TABLE (72 BYTES) RESISTOR 1 LOOK-UP TABLE (72 BYTES) B7h C7h F0h F0h RESERVED AND CALIBRATION CONSTANTS 255 FF C7h RESERVED AND CALIBRATION CONSTANTS FFh FFh Figure 2. Memory Organization, ADEN = 0 Variable Resistors The value of each variable resistor is determined by a temperature-addressed look-up table, which can assign a unique value (00h to FFh) to each resistor for every 2°C increment over the -40°C to +102°C range (see Table 3). See the Temperature Conversion section for more information. The variable resistors can also be used in manual mode. If the TEN bit equals 0, the resistors are in manual mode and the temperature indexing is disabled. The user sets the resistors in manual mode by writing to addresses 82h and 83h in Table 03 to control resistors 0 and 1, respectively. Memory Description The memory of the DS1856 is divided into two areas referred to as the Main Device and the Auxiliary Device. The Main Device comprises all of the DS1856 specific memory while the Auxiliary Device consists of 128 bytes of general-purpose EEPROM and is especially useful in GBIC applications. Main and Auxiliary ____________________________________________________________________ 11 DS1856 Table 4. ADEN Address Configuration DS1856 Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors and Password Protection DEC HEX 2-WIRE ADDRRESS A2h (DEFAULT) 0 0 00h NOTE 1: ADEN BIT = 1. ALL MEMORY (INCLUDING THE AUXILIARY MEMORY) IS ADDRESSED USING THE NOTE 1: MAIN DEVICE 2-WIRE SLAVE ADDRESS. NOTE 2: TABLES 00h AND 01h ACCESS THE SAME PHYSICAL MEMORY. NOTE 3: TABLE 02h DOES NOT EXIST. LOWER MEMORY PASSWORD ENTRY (PWE) (4 BYTES) 127 7F 128 80 80h TABLE SELECT BYTE 7Fh 80h TABLE 00h/01h 183 B7 199 200 C7 C8 EEPROM AUXILIARY MEMORY (128 BYTES) 80h 80h TABLE 03h TABLE 04h TABLE 05h CONFIGURATION TABLE RESISTOR 0 LOOK-UP TABLE (72 BYTES) RESISTOR 1 LOOK-UP TABLE (72 BYTES) B7h C7h F0h F0h RESERVED AND CALIBRATION CONSTANTS 255 FF FFh C7h RESERVED AND CALIBRATION CONSTANTS FFh FFh Figure 3. Memory Organization, ADEN = 1 memories can be accessed by two separate 2-wire slave addresses (see Table 4). The Main Device address is A2h (or determined by the value in Table 03, byte 8Ch, when ADFIX = 1) and the Auxiliary Device address is A0h (fixed). A configuration bit, ADEN (Table 03, byte 89h, bit 5), determines whether the DS1856 uses one or two 2-wire slave addresses. This feature can be used to save component count in SFF applications or other applications where both GBIC and monitoring functions are implemented and two device addresses are needed. The memory organization for ADEN = 0 is shown in Figure 2. In this configuration, the 128 bytes of Auxiliary Device EEPROM are located at memory locations 00h to 7Fh and accessed using the Auxiliary Device 2-wire slave address of A0h (fixed). The remainder of the DS1856’s memory is accessed using the Main Device address. The memory organization of the second configuration, ADEN = 1, is shown in Figure 3. In this configuration, all 12 of the DS1856’s memory including the Auxiliary memory is accessed using only the Main Device address. The Auxiliary Device memory is mapped into Table 00 and Table 01 in the Main Device. Both tables map to the same block of physical memory. This is done to improve the compatibility between previous members of this IC family such as the DS1858/DS1859 and the DS1852. In this configuration, the DS1856 ignores communication using the Auxiliary Device address. The value of the Main Device address can be changed to a value other than the default value of A2h (see data sheet Table 5). There can be up to 128 devices sharing a common 2-wire bus, with each device having its own unique address. To change the Main Device address, first write the desired value to the Chip Address byte (Table 03, byte 8Ch). Then, enable the new address by setting ADFIX to a 1. Subsequent 2-wire communication must be performed using the new Main Device address. When ADFIX = 0, the Chip Address byte is ignored, and the Main Device address is set to A2h. ____________________________________________________________________ Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors and Password Protection (PWE) bytes located in the Main Device at 7Bh to 7Eh. The value entered is compared to both the PW1 and PW2 settings located in Table 03, bytes B0h to B3h and Table 03, bytes B4h to B7h, respectively, to determine if access should be granted. Access is granted until the password is changed or until power is cycled. Writing PWE can be done with any level of access, although PWE can never be read. Table 6. Table Select Byte The following table is the legend used in the memory map to indicate the access level required for read and write access. Each table in the following memory map begins with a higher level view of a particular portion of the memory showing information such as row (8 bytes) and byte names. The tables are then followed, where applicable, by an Expanded Bytes table, which shows bit names and values. Furthermore, both tables use the permission legend to indicate the access required on a row, byte, and bit level. TABLE SELECT BYTE 00 TABLE NAME 01 Auxiliary Device Memory (When ADEN = 1) 02 Does Not Exist 03 Configuration 04 Resistor 0 Look-up Table 05 Resistor 1 Look-up Table Before attempting to read and write any of the bits or bytes mentioned in this section, it is important to look at the memory map provided in a subsequent section to verify what level of password is required. Password protection is described in the following section. Writing PW1 and PW2 requires PW2 access. However, PW1 and PW2 can never be read, even with PW2 access. On power-up, PWE is set to all 1s (FFFFh). As long as neither of the passwords are ever changed to FFFFh, then User access is the power-up default. Likewise, password protection can be intentionally disabled by setting the PW2 password to FFFFh. Memory Map The memory map is followed by a Register Description section, which describes bytes and bits in further detail. Table 7. Password Permission PERMISSION Password Protection The DS1856 uses two 4-byte passwords to achieve three levels of access to various memory locations. The three levels of access are: User Access: This is the default state after power-up. It allows read access to standard monitoring and status functions. Level 1 Access: This allows access to customer data table (Tables 00 and 01) in addition to everything granted by User access. This level is granted by entering Password 1 (PW1). Level 2 Access: This allows access to all memory, settings, and features, in addition to everything granted by Level 1 and User access. This level is granted by entering Password 2 (PW2). To obtain a particular level of access, the corresponding password must be entered in the Password Entry <0> READ WRITE At least one byte in the row is different than the rest of the row, so look at each byte separately for permissions. <1> all PW2 <2> all NA <3> all all (The part also writes to this byte.) <4> PW2 PW2 + mode_bit <5> all all <6> NA all <7> PW1 PW1 <8> PW2 PW2 PW2 <9> NA <10> PW2 NA <11> all PW1 ____________________________________________________________________ 13 DS1856 The DS1856 2-wire interface uses 8-bit addressing, which allows up to 256 bytes to be addressed traditionally on a given 2-wire slave address. However, since the Main Device contains more than 256 bytes, a table scheme is used. The lower 128 bytes of the Main Device, memory locations 00h to 7Fh, function as expected and are independent of the currently selected table. Byte 7Fh is the Table Select byte. This byte determines which memory table will be accessed by the 2-wire interface when address locations 80h to FFh are accessed. Memory locations 80h to FFh are accessible only through the Main Device address. The Auxiliary Device address has no access to the tables, but the Auxiliary Device memory can be mapped into the Main Device’s memory space (by setting ADEN = 1). Valid values for the Table Select byte are shown in the table below. DS1856 Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors and Password Protection Memory Map LOWER MEMORY Row (hex) Row Name Word 0 Byte 0/8 Word 1 Byte 1/9 Byte 2/A Word 2 Byte 3/B Byte 4/C Word 3 Byte 5/D Byte 6/E Byte 7/F 00 <1> Temp Alarm Hi Temp Alarm Lo Temp Warn Hi 08 <1> VCC Alarm Hi VCC Alarm Lo VCC Warn Hi VCC Warn Lo 10 <1> Mon1 Alarm Hi Mon1 Alarm Lo Mon1 Warn Hi Mon1 Warn Lo 18 <1> Mon2 Alarm Hi Mon2 Alarm Lo Mon2 Warn Hi Mon2 Warn Lo 20 <1> Mon3 Alarm Hi Mon3 Alarm Lo Mon3 Warn Hi Threshold0 Threshold1 Threshold2 Threshold3 Threshold4 Temp Warn Lo Mon3 Warn Lo 28 <1> EE EE EE EE EE EE EE EE 30 <1> EE EE EE EE EE EE EE EE 38 <1> EE EE EE EE EE EE EE EE 40 <1> EE EE EE EE EE EE EE EE 48 <1> EE EE EE EE EE EE EE EE 50 <1> EE EE EE EE EE EE EE EE 58 <1> EE EE EE EE EE EE EE EE user ROM user ROM user ROM user ROM user ROM user ROM user ROM <2> 60 Values0 Temp Value <0> 68 <2> Values1 Alrm Wrn <0> 78 Table Select Alarm1 Reserved Reserved <6> Reserved Warn1 Status Warn0 <6> Reserved <0> Reserved Reserved <6> Mon2 Value <2> Reserved Alarm0 <6> Mon1 Value <2> Mon3 Value <2> 70 Vcc Value Reserved <6> PWE msb <3> Update Reserved <5> PWE lsb Tbl Sel EXPANDED BYTES Byte (hex) Byte Name Bit7 bit15 User EE bit13 EE Bit5 bit12 bit11 EE Bit4 bit10 bit9 EE Bit3 bit8 bit7 EE Bit2 bit6 bit5 EE Bit1 bit4 bit3 EE Bit0 bit2 bit1 EE bit0 EE S 26 25 24 23 22 21 20 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 Temp Warn S 6 2 5 2 4 2 3 2 2 2 1 2 0 2 -1 2 -2 -3 -4 -5 -6 -7 2-8 Volt Alarm 215 214 213 212 211 210 29 28 27 26 25 24 23 22 21 20 Volt Warn 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 20 Temp Alarm 14 Bit6 bit14 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 28 User ROM EE EE EE EE EE EE EE EE 30 User ROM EE EE EE EE EE EE EE EE 38 User ROM EE EE EE EE EE EE EE EE 40 User ROM EE EE EE EE EE EE EE EE 48 User ROM EE EE EE EE EE EE EE EE 50 User ROM EE EE EE EE EE EE EE EE 58 User ROM EE EE EE EE EE EE EE EE ____________________________________________________________________ Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors and Password Protection 60 Temp Value S 26 25 24 23 22 21 20 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 62 VCC Value 215 214 213 212 211 210 29 28 27 26 25 24 23 22 21 20 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 20 1 20 1 20 64 66 68 Mon1 Value Mon2 Value Mon3 Value 2 2 15 14 2 2 15 14 2 2 <2> 2 12 2 2 13 2 10 2 2 SoftHiz <2> 2 2 11 12 2 <11> 2 11 10 2 2 9 8 2 2 9 8 2 2 <2> 2 7 2 6 2 2 7 4 2 6 2 2 5 2 5 2 4 2 <2> 2 Temp Rdy VCC Rdy 70 Alarm1 Temp Hi Temp Lo VCC Hi VCC Lo Mon1 Hi 71 Alarm0 Mon3 Hi Mon3 Lo Reserved Reserved Reserved 74 Warn1 Temp Hi Temp Lo VCC Hi VCC Lo Mon1 Hi Mon1 Lo Warn0 PWE msb 7D PWE lsb 7F Tbl Sel Mon3 Hi Reserved Mon3 Rdy 2 3 2 2 2 3 2 2 2 2 2 2 <2> Status Mon2 Rdy 2 <2> Update Mon1 Rdy Reserved 2 6F 75 Reserved 2 6E 7B Rhiz 2 13 TxF <2> RxL Reserved Rdyb Reserved Reserved Mon1 Lo Mon2 Hi Mon2 Lo Reserved Reserved Mint Mon2 Hi Mon2 Lo Mon3 Lo Reserved Reserved Reserved Reserved Reserved Reserved 231 230 229 228 227 226 225 223 221 219 217 15 14 13 12 11 10 2 2 2 27 2 26 2 2 224 9 8 2 25 2 24 222 7 6 2 220 5 2 4 2 23 2 22 218 3 2 2 2 216 1 20 2 21 20 AUXILIARY (VALID WHEN ADEN = 0) Row (hex) 00–7F Row Name <1> EE Word 0 Word 1 Word 2 Word 3 Byte 0/8 Byte 1/9 Byte 2/A Byte 3/B Byte 4/C Byte 5/D Byte 6/E Byte 7/F EE EE EE EE EE EE EE EE TABLE 00/01 (VALID WHEN ADEN = 1) Row (hex) 80–FF Row Name <7> EE Word 0 Word 1 Word 2 Word 3 Byte 0/8 Byte 1/9 Byte 2/A Byte 3/B Byte 4/C Byte 5/D Byte 6/E Byte 7/F EE EE EE EE EE EE EE EE ____________________________________________________________________ 15 DS1856 Memory Map (continued) DS1856 Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors and Password Protection Memory Map (continued) TABLE 03 (CONFIGURATION) Row (hex) Row Name 80 <0> 88 <8> Config0 Config1 Word 0 Byte 0/8 <8> Word 1 Byte 1/9 Byte 2/A <4> Mode <4> Tindex Int Enable Config Word 2 Byte 3/B <4> Res0 <8> Res1 Reserved Byte 4/C Reserved Reserved chip addr Word 3 Byte 5/D <8> Reserved Byte 6/E <8> Reserved Reserved Byte 7/F <8> Reserved Rshift1 Rshift0 <8> Reserved Vcc Scale Mon1 Scale Mon2 Scale 98 <8> Mon3 Scale Reserved Reserved Reserved A0 <8> Reserved Vcc Offset MON1 Offset MON2 Offset A8 <8> Offset1 MON3 Offset Reserved Reserved Internal Temp Offset* Pwd Value PW1 msb PW1 lsb PW2 msb PW2 lsb 90 B0 Scale0 Scale1 Offset0 <9> EXPANDED BYTES Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Byte (hex) Byte Name 80 Mode Reserved Reserved Reserved Reserved Reserved Reserved TEN AEN 81 Tindex 27 26 25 24 23 22 21 20 7 6 5 4 3 2 1 20 1 82 bit15 Res0 bit14 bit13 2 bit12 bit11 2 7 bit9 2 6 Reserved Reserved Reserved Reserved Inv 1 Inv 2 23 22 21 20 Mon10 Reserved Mon22 Mon21 Mon20 0 Vcc Mon1 Mon2 Reserved Reserved ADEN ADFIX 8C Chip Addr 27 26 25 24 8E Rshift1 Reserved Mon12 Mon11 Reserved 2 1 96 98 Mon2 Scale Mon3 Scale 2 2 bit0 Mon3 Temp Config Mon1 Scale bit1 Reserved Int Enable 94 2 bit2 20 2 2 Reserved Reserved Reserved Reserved 215 214 213 212 211 210 29 28 27 26 25 24 23 22 21 20 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 20 1 20 1 20 3 2 15 2 15 2 2 14 2 14 2 2 13 2 13 2 2 12 2 12 2 11 2 11 2 10 2 10 2 9 2 9 2 8 2 8 2 7 2 7 2 6 2 6 2 5 2 5 2 4 2 4 2 3 2 3 2 2 2 2 2 2 2 2 2 2 2 2 2 22 A4 Mon1 Offset S S 215 214 213 212 211 210 29 28 27 26 25 24 23 22 S 15 14 13 12 11 10 9 8 7 6 5 4 3 22 3 22 -5 2-6 17 216 1 20 17 A8 AE B0 B2 Mon3 Offset Temp Offset* PW1 msb PW1 lsb B4 PW2 msb B6 PW2 lsb S S S 8 31 2 15 2 31 2 30 2 14 2 30 2 7 2 29 2 13 2 29 2 6 2 28 2 12 2 28 2 5 2 27 2 11 2 27 2 4 2 26 2 10 2 26 2 11 2 3 2 25 2 9 2 25 2 10 2 2 2 24 2 8 2 24 2 9 2 1 2 23 2 7 2 23 2 8 2 0 2 22 2 6 2 22 7 2 -1 2 21 2 5 2 6 2 -2 2 20 2 4 2 20 2 5 2 -3 2 19 2 3 2 19 2 4 2 -4 2 18 2 2 2 18 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 216 215 214 213 212 211 210 29 28 27 26 25 24 23 22 21 20 ____________________________________________________________________ 21 2 2 *The final result must be XOR’ed with BB40h. 16 2 4 2 2 12 5 2 2 2 6 2 2 13 7 2 2 2 8 2 2 14 9 2 2 2 10 2 2 15 11 2 S 2 12 2 S S 13 2 VCC Offset Mon2 Offset 14 2 Mon3 A2 A6 15 Mon3 bit3 2 2 Mon3 bit4 2 89 Rshift0 bit5 3 88 VCC Scale bit6 2 4 Res1 92 bit7 2 5 2 bit8 83 8F 2 bit10 Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors and Password Protection TABLE 04 (LOOKUP TABLE FOR RESISTOR 0) Row (hex) Row Name Word 0 Word 1 Word 2 Word 3 Byte 0/8 Byte 1/9 Byte 2/A Byte 3/B Byte 4/C Byte 5/D Byte 6/E Byte 7/F C8 Empty Empty Empty Empty Empty Empty Empty Empty D0 Empty Empty Empty Empty Empty Empty Empty Empty D8 Empty Empty Empty Empty Empty Empty Empty Empty E0 Empty Empty Empty Empty Empty Empty Empty Empty E8 Empty Empty Empty Empty Empty Empty Empty Empty Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 80 <8> 88 <8> 90 <8> 98 <8> A0 <8> A8 <8> B0 <8> B8 <8> C0 <8> LUT LUT LUT LUT LUT LUT LUT LUT LUT F0 F8 <10> Res0 data Resistor 0 Calibration Constants (see data sheet Table 8) EXPANDED BYTES Byte (hex) Byte Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 80–C7 Res0 27 26 25 24 23 22 21 20 F8–FF Res0 data Resistor 0 Calibration Constants (see data sheet Table 8 for weighting) ____________________________________________________________________ 17 DS1856 Memory Map (continued) DS1856 Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors and Password Protection Memory Map (continued) TABLE 05 (LOOKUP TABLE FOR RESISTOR 1) Row (hex) Row Name Word 0 Word 1 Word 2 Word 3 Byte 0/8 Byte 1/9 Byte 2/A Byte 3/B Byte 4/C Byte 5/D Byte 6/E Byte 7/F C8 Empty Empty Empty Empty Empty Empty Empty Empty D0 Empty Empty Empty Empty Empty Empty Empty Empty D8 Empty Empty Empty Empty Empty Empty Empty Empty E0 Empty Empty Empty Empty Empty Empty Empty Empty 80 <8> 88 <8> 90 <8> 98 <8> A0 <8> A8 <8> B0 <8> B8 <8> C0 <8> LUT LUT LUT LUT LUT LUT LUT LUT LUT E8 Empty Empty Empty Empty Empty Empty Empty Empty F0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved <10> F8 Res1 data Resistor 1 Calibration Constants (see data sheet Table 8) EXPANDED BYTES Byte (hex) Byte Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 80–C7 Res1 27 26 25 24 23 22 21 20 F8–FF Res1 data 18 Resistor 1 Calibration Constants (see data sheet Table 8 for weighting) ____________________________________________________________________ Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors and Password Protection Name of Row • • Name of Byte............. <Read/Write><Volatile><Power-On-Value> Name of Byte............. <Read/Write><Nonvolitile><Factory-Default-Setting> Threshold0 • • • • Temp High Alarm ..... <R-all/W-pw2><NV><7FFFh> Temperature measurements above this two's complement threshold set its corresponding alarm bit. Measurements below this threshold clear the alarm bit. Temp Low Alarm....... <R-all/W-pw2><NV><8000h> Temperature measurements below this two's complement threshold set its corresponding alarm bit. Measurements above this threshold clear the alarm bit. Temp High Warning . <R-all/W-pw2><NV><7FFFh> Temperature measurements above this two's complement threshold set its corresponding warning bit. Measurements below this threshold clear the warning bit. Temp Low Warning .. <R-all/W-pw2><NV><8000h> Temperature measurements below this two's complement threshold set its corresponding warning bit. Measurements above this threshold clear the warning bit. Threshold1 • • • • VCC High Alarm........ <R-all/W-pw2><NV><FFFFh> Voltage measurements of the VCC input above this unsigned threshold set its corresponding alarm bit. Measurements below this threshold clear the alarm bit. VCC Low Alarm.......... <R-all/W-pw2><<NV><0000h> Voltage measurements of the VCC input below this unsigned threshold set its corresponding alarm bit. Measurements above this threshold clear the alarm bit. VCC High Warning.... <R-all/W-pw2><NV><FFFFh> Voltage measurements of the VCC input above this unsigned threshold set its corresponding warning bit. Measurements below this threshold clear the warning bit. VCC Low Warning..... <R-all/W-pw2><<NV><0000h> Voltage measurements of the VCC input below this unsigned threshold set its corresponding warning bit. Measurements above this threshold clear the warning bit. Threshold2 • • • • Mon1 High Alarm ..... <R-all/W-pw2><NV><FFFFh> Voltage measurements of the Mon1 input above this unsigned threshold set its corresponding alarm bit. Measurements below this threshold clear the alarm bit. Mon1 Low Alarm ...... <R-all/W-pw2><NV><0000h> Voltage measurements of the Mon1 input below this unsigned threshold set its corresponding alarm bit. Measurements above this threshold clear the alarm bit. Mon1 High Warning. <R-all/W-pw2><NV><FFFFh> Voltage measurements of the Mon1 input above this unsigned threshold set its corresponding warning bit. Measurements below this threshold clear the warning bit. Mon1 Low Warning .. <R-all/W-pw2><NV><0000h> Voltage measurements of the Mon1 input below this unsigned threshold set its corresponding warning bit. Measurements above this threshold clear the warning bit. ____________________________________________________________________ 19 DS1856 Register Descriptions DS1856 Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors and Password Protection Register Descriptions (continued) Threshold3 • • • • Mon2 High Alarm ..... <R-all/W-pw2><NV><FFFFh> Voltage measurements of the Mon2 input above this unsigned threshold set its corresponding alarm bit. Measurements below this threshold clear the alarm bit. Mon2 Low Alarm ...... <R-all/W-pw2><NV><0000h> Voltage measurements of the Mon2 input below this unsigned threshold set its corresponding alarm bit. Measurements above this threshold clear the alarm bit. Mon2 High Warning. <R-all/W-pw2><NV><FFFFh> Voltage measurements of the Mon2 input above this unsigned threshold set its corresponding warning bit. Measurements below this threshold clear the warning bit. Mon2 Low Warning .. <R-all/W-pw2><NV><0000h> Voltage measurements of the Mon2 input below this unsigned threshold set its corresponding warning bit. Measurements above this threshold clear the warning bit. Threshold4 • • • • Mon3 High Alarm ..... <R-all/W-pw2><NV><FFFFh> Voltage measurements of the Mon3 input above this unsigned threshold set its corresponding alarm bit. Measurements below this threshold clear the alarm bit. Mon3 Low Alarm ...... <R-all/W-pw2><NV><0000h> Voltage measurements of the Mon3 input below this unsigned threshold set its corresponding alarm bit. Measurements above this threshold clear the alarm bit. Mon3 High Warning. <R-all/W-pw2><NV><FFFFh> Voltage measurements of the Mon3 input above this unsigned threshold set its corresponding warning bit. Measurements below this threshold clear the warning bit. Mon3 Low Warning .. <R-all/W-pw2><NV><0000h> Voltage measurements of the Mon3 input below this unsigned threshold set its corresponding warning bit. Measurements above this threshold clear the warning bit. User ROM • User ROM ................. <R-all/W-pw2><NV><00h> Nonvolatile EEPROM memory. A2D Value0 • • • • 20 Temp Meas ................ <R-all><W-NA><0000h> The signed two's complement Direct-toTemperature measurement. VCC Meas................... <R-all><W-NA><0000h> Unsigned voltage measurement. Mon1 Meas................ <R-all><W-NA><0000h> Unsigned voltage measurement. Mon2 Meas................ <R-all><W-NA><0000h> Unsigned voltage measurement. ____________________________________________________________________ Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors and Password Protection A2D Value1 • • • Mon3 Meas................ Reserved .................... Status ......................... a) Rhiz.................... b) Soft Hiz.............. c) Reserved ............ d) TxF ................... e) RxL ................... f) Rdyb................... • Update ....................... a) b) c) d) Temp Rdy .......... VCC Rdy............. Mon1 Rdy.......... Mon2 Rdy.......... e) Mon3 Rdy.......... Status • • • • Alarm0 ....................... a) Temp Hi............. b) Temp Lo ............ c) VCC Hi .............. d) VCC Lo .............. e) MON1 Hi........... f) MON1 Lo .......... g) MON2 Hi........... h) MON2 Lo .......... Alarm1 ....................... a) MON3 HI........... b) MON3 Lo .......... c) Mint ................... Reserved .................... Warning0 ................... a) Temp Hi............. b) Temp Lo ............ c) VCC Hi ............. <R-all><W-NA><0000h> Unsigned voltage measurement. <R-all><W-NA><0000h> <R-all><W-see bits><conditional> <R-all><W-NA><1b> High when resistor outputs are high impedance. <R-all><W-all><0b> Setting this bit will make resistor outputs high impedance. <R-all><W-NA><0b> <R-all><W-NA><conditional> Reflects the logic level to be output on pin Out1. <R-all><W-NA><conditional> Reflects the logic level to be output on pin Out2. <R-all><W-NA>< VCC dependant > Ready Bar. When the supply is above the Power-On-Analog (POA) trip point, this bit is active LOW. Thus, this bit reads a logic One if the supply is below POA or too low to communicate over the 2-wire bus. <R-all/W-all><00h> Status of completed conversions. At Power-On, these bits are cleared and will be set as each conversion is completed. These bits can be cleared so that a completion of a new conversion may be verified. Temperature conversion is ready. VCC conversion is ready. Mon1 conversion is ready. Mon2 conversion is ready. Mon3 conversion is ready. <R-all><W-NA><10h> High Alarm Status bits. High Alarm Status for Temperature measurement. Low Alarm Status for Temperature measurement. High Alarm Status for VCC measurement. Low Alarm Status for VCC measurement. This bit is set when theVCC supply is below the POA trip point value. It clears itself when a VCC measurement is completed and the value is above the low threshold. High Alarm Status for MON1 measurement. Low Alarm Status for MON1 measurement. High Alarm Status for MON2 measurement. Low Alarm Status for MON2 measurement. <R-all><W-NA><00h> Low Alarm Status bits. High Alarm Status for MON3 measurement. Low Alarm Status for MON3 measurement. Maskable Interrupt. If an alarm is present and the alarm is enabled then this bit is high. Otherwise this bit is a zero. <R-all><W-NA><00h>. <R-all><W-NA><00h> High Warning Status bits. High Warning Status for Temperature measurement. Low Warning Status for Temperature measurement. High Warning Status for VCC measurement. ____________________________________________________________________ 21 DS1856 Register Descriptions (continued) DS1856 Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors and Password Protection Register Descriptions (continued) d) VCC Lo .............. Low Warning Status for VCC measurement. This bit is set when the VCC supply is below the POA trip point value. It clears itself when a VCC measurement is completed and the value is above the low threshold. e) MON1 Hi........... High Warning Status for MON1 measurement. f) MON1 Lo .......... Low Warning Status for MON1 measurement. g) MON2 Hi........... High Warning Status for MON2 measurement. h) MON2 Lo .......... Low Warning Status for MON2 measurement. • Warning1 ................... <R-all><W-NA><00h> Low warning Status bits. a) MON3 HI........... High Warning Status for MON3 measurement. b) MON3 Lo........... Low Warning Status for MON3 measurement. Table Select • • • Config0 • • 22 Reserved .................... <R-NA><W-all><00h> PWE........................... <R-NA><W-all><FFFFFFFFh> Password Entry. There are two passwords for the DS1856. The lower level password (PW1) has all the access of a normal user plus those made available with PW1. The higher level password (PW2) has all of the access of PW1 plus those made available with PW2. The value of the password reside in EE inside of PW2 memory. TBL Sel...................... <R-all/W-all><00h> Table Select. The upper memory tables of the DS1856 are accessible by writing the correct table value in this register. If the device is configured to have a Table 01h then writing a 00h ora 01h in this byte will access that table. Mode.......................... <R-pw2/W-pw2><NV><03h> a) TEN.................... At Power-On this bit is HIGH, which enables autocontrol of the LUT. If this bit is written to a ZERO then the resistor values are writeable by the user and the LUT recalls are disabled. This allows the user to interactively test their modules by manually writing resistor values. The resistors will update with the new value at the end of the write cycle. Thus both registers (Res0 and Res1) should be written in the same write cycle. The 2-wire Stop condition is the end of the write cycle. b) AEN ................... At Power-On this bit is HIGH, which enables autocontrol of the LUT. If this bit is cleared to a ZERO then the temperature calculated index value ( T index ) is writeable by the user and the updates of calculated indexes are disabled. This allows the user to interactively test their modules by controlling the indexing for the look-up tables. The recalled values from the LUTs will appear in the resistor registers after the next completion of a temperature conversion (just like it would happen in auto mode). Both pots will update at the same time (just like it would happen in auto mode). . T Index....................... <R-pw2><W-pw2+AENb><00h> Holds the calculated index based on the Temperature Measurement. This index is used for the address during Look-up of Tables 4 and 5. ____________________________________________________________________ Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors and Password Protection • • • Config . Res0 ........................... <R-pw2><W-pw2+TENb><FFh> The base value used for Resistor 0 and recalled from Table 4 at the memory address found in T Index. This register is updated at the end of the Temperature conversion. Res1 ........................... <R-pw2><W-pw2+TENb><FFh> The base value used for Resistor 1 and recalled from Table 5 at the memory address found in T Index. This register is updated at the end of the Temperature conversion. Reserved .................... <R-pw2><W-pw2><00h> SRAM. 1 • • • • • Int Enable.................. <R-pw2/W-pw2><NV><F8h> Configures the maskable interrupt for the Out1 pin. a) Temp Enable...... Temperature measurements, outside of the threshold limits, are enabled to create an active interrupt on the Out1 pin. b) VCC Enable......... VCC measurements, outside of the threshold limits, are enabled to create an active interrupt on the Out1 pin. c) MON1 Enable.... MON1 measurements, outside of the threshold limits, are enabled to create an active interrupt on the Out1 pin. d) MON2 Enable.... MON2 measurements, outside of the threshold limits, are enabled to create an active interrupt on the Out1 pin. e) MON3 Enable.... MON3 measurements, outside of the threshold limits, are enabled to create an active interrupt on the Out1 pin. f) Reserved ............ EE. Config........................ <R-pw2/W-pw2><NV><00h> Configure the memory location and the polarity of the digital outputs. a) Reserved ............ EE. b) ADEN ................ Auxiliary Device ENable. 128 bytes of EE are addressable depending on the value of this bit. When set to a 1, the memory is located in or as Table 01h. When set to a 0, the memory is addressed by using a Device address of A0h and the locations in memory are 00h to 7Fh. c) ADFIX ............... Device Fixable Address. When this bit is set to a 1, the main memory of the DS1856 is a Device Address equal to the value found in byte chip_address. When this bit is set to a 0 the main memory of the DS1856 is a Device Address of A2h. d) Inv1 .................... Enable the inversion of the relationship between IN1 and OUT1. e) Inv2 .................... Enable the inversion of the relationship between IN2 and OUT2. Chip Address............. This value becomes the Device address for the main memory when ADFIX bit is set. Right Shift1 ................ Allows for right-shifting the final answer of some voltage measurements. This allows for scaling the measurements to the smallest full-scale voltage and then right-shifting the final result so the reading is weighted to the correct lsb. Right Shift0 ................ Allows for right-shifting the final answer of some voltage measurements. This allows for scaling the measurements to the smallest full-scale voltage and then right-shifting the final result so the reading is weighted to the correct lsb. ____________________________________________________________________ 23 DS1856 Register Descriptions (continued) DS1856 Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors and Password Protection Register Descriptions (continued) Scale0 • • • Scale1 VCC Scale................... <R-pw2/W-pw2><NV><6.5535V> Controls the Scaling or Gain of the VCC measurements. MON1 Scale .............. <R-pw2/W-pw2><NV><2.500V> Controls the Scaling or Gain of the MON1 measurements. MON2 Scale .............. <R-pw2/W-pw2><2.500V> Controls the Scaling or Gain of the MON2 measurements. • MON3 Scale .............. <R-pw2/W-pw2><NV><2.500V> Controls the Scaling or Gain of the MON3 measurements. • VCC Offset.................. <R-pw2/W-pw2><NV><0000h> Allows for offset control of VCC measurement if desired. MON1 Offset ............. <R-pw2/W-pw2><NV><0000h> Allows for offset control of MON1 measurement if desired. MON2 Offset ............. <R-pw2/W-pw2><NV><0000h> Allows for offset control of MON2 measurement if desired. Offset0 • • Offset1 • • MON3 Offset ............. <R-pw2/W-pw2><NV><0000h> Allows for offset control of MON3 measurement if desired. Temp Offset ............... <R-pw2/W-pw2><NV><0000h> Allows for offset control of Temp measurement if desired. PWD Value • • LUT 24 • • Password 1................ <R-NA/W-pw2><NV><FFFFFFFFh> The PWE value is compared against the value written to this location to enable PW1 access. At power-on, the PWE value is set to all ones. Thus writing these bytes to all ones grants PW1 access on power-up without writing the password entry. Password 2................ <R-NA/W-pw2><NV><FFFFFFFFh> The PWE value is compared against the value written to this location to enable PW2 access. At power-on, the PWE value is set to all ones. Thus writing these bytes to all ones grants PW2 access on power-up without writing the password entry. Res0 ........................... The unsigned value for Resistor 0. Res1 ........................... The unsigned value for Resistor 1. ____________________________________________________________________ Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors and Password Protection 2 R − u x 1 + v x (C − 25) + w x (C − 25) − pos(α, R, C) = 2 (x) x 1 + y x (C − 25) + z x (C − 25) R = the resistance desired at the output terminal C = temperature in degrees Celsius u, v, w, x1, x0, y, z, and α are calculated values found in the corresponding look-up tables. The variable x from the equation above is separated into x1 (the MSB of x) and x0 (the LSB of x). Their addresses and LSB values are given below. The variable y is assigned a value. All other variables are unsigned. Resistor 0 variables are found in Table 04, and Resistor 1 variables are found in Table 05. When shipped from the factory, all other memory locations in the LUTs are programmed to FFh. Table 8. Calibration Constants ADDRESS VARIABLE LSB F8h u 20 F9h v 20E-6 FAh w 100E-9 FBh x1 21 FCh x0 2-7 FDh y FEh z 10E-9 FFh α 2-2 2E-6 (signed) 8E-6 (signed) for 2.5k resistor Internal Calibration The DS1856 has two methods for scaling an analog input to a digital result. The two methods are gain and offset. Each of the inputs (V CC, MON1, MON2, and MON3) has a unique register for the gain and the offset found in Table 03h, 92h to 99h, and A2h to A9h. To scale the gain and offset of the converter for a specific input, you must first know the relationship between the analog input and the expected digital result. The input that would produce a digital result of all zeros is the null value (normally this input is GND). The input that would produce a digital result of all ones is the fullscale (FS) value. The FS value is also found by multiplying an all-ones digital answer by the weighted LSB (e.g., since the digital reading is a 16-bit register, let us assume that the LSB of the lowest weighted bit is 50µV, then the FS value is 65,535 x 50µV = 3.27675V). A binary search is used to scale the gain of the converter. This requires forcing two known voltages to the input pin. It is preferred that one of the forced voltages is the null input and the other is 90% of FS. Since the LSB of the least significant bit in the digital reading register is known, the expected digital results are also known for both inputs (null/LSB = CNT1 and 90%FS/ LSB = CNT2). The user might not directly force a voltage on the input. Instead they have a circuit that transforms light, frequency, power, or current to a voltage that is the input to the DS1856. In this situation, the user does not need to know the relationship of voltage to expected digital result but instead knows the relationship of light, frequency, power, or current to the expected digital result. An explanation of the binary search used to scale the gain is best served with the following example pseudocode: /* Assume that the null input is 0.5V. */ /* In addition, the requirement for LSB is 50µV. */ FS = 65535 x 50E-6; /* 3.27675 */ CNT1 = 0.5 / 50E-6; CNT2 = 0.90 x FS / 50E-6; /* 10000 */ /* 58981.5 */ /* Thus the null input 0.5V and the 90% of FS input is 2.949075V. */ Set the trim-offset-register to zero; Set Right-Shift register to zero (typically zero. See the Right-Shifting section); gain_result = 0h; Clamp = FFF8h/2^(Right_Shift_Register); For n = 15 down to 0 begin ____________________________________________________________________ 25 DS1856 Programming the Look-up Table (LUT) The following equation can be used to determine which resistor position setting, 00h to FFh, should be written in the LUT to achieve a given resistance at a specific temperature. Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors and Password Protection DS1856 gain_result = gain_result + 2^n; Force the 90% FS input (2.949075V); Meas2 = read the digital result from the part; If Meas2 >= Clamp then gain_result = gain_result – 2^n; Else Force the null input (0.5V); Meas1 = read the digital result from the part; if (Meas2 – Meas1) > (CNT2 – CNT1) then gain_result = gain_result – 2^n; end; Set the gain register to gain_result; The gain register is now set and the resolution of the conversion will best match the expected LSB. The next step is to calibrate the offset of the DS1856. With the correct gain value written to the gain register, again force the null input to the pin. Read the digital result from the part (Meas1). The offset value is equal to the negative value of Meas1. value can be right-shifted four times without losing resolution. Table 9 shows when the right-shifting method can be used. Temperature Conversion The direct-to-digital temperature sensor measures temperature through the use of an on-chip temperature measurement technique with a -40°C to +102°C operating range. Temperature conversions are initiated upon power-up, and the most recent conversion is stored in memory locations 60h and 61h of the Main Device, which are updated every tframe. Temperature conversions do not occur during an active read or write to memory. The value of each resistor is determined by the temperature-addressed look-up table. The look-up table assigns a unique value to each resistor for every 2°C increment with a 1°C hysteresis at a temperature transition over the operating temperature range (see Figure 4). Table 9. Right Shifting OUTPUT RANGE USED WITH ZERO RIGHT-SHIFTS NUMBER OF RIGHT-SHIFTS NEEDED 0h....FFFFh 0 0h....7FFFh 1 0h....3FFFh 2 0h....1FFFh 3 0h....0FFFh 4 Meas1 Offset _Re gister = 4 The calculated offset is now written to the DS1856 and the gain and offset scaling is now complete. M6 Right-Shifting A/D Conversion Result (Scalable Dynamic Ranging) If the maximum desired digital output is less than 7FFFh, then the calibrated system is using less than 1/2 of the ADC’s range. Similarly, if the maximum desired digital output is less than 1FFFh, then the calibrated system is only using 1/8 of the ADC’s range. For example, if using a zero for the right-shift during internal calibration and the maximum expected input results in a maximum digital output less than 1FFCh, only 1/8 of the ADC’s range is used. If left like this, the three MS bits of the ADC will never be used. In this example, a value of 3 for the rightshifting maximizes the ADC range. No resolution is lost since this is a 12-bit converter that is left justified. The 26 M5 MEMORY LOCATION The right-shifting method is used to regain some of the lost ADC range of a calibrated system. If a system is calibrated so the maximum expected input results in a digital output value of less than 7FFFh (1/2 FS), then it is a candidate for using the right-shifting method. DECREASING TEMPERATURE M4 M3 INCREASING TEMPERATURE M2 M1 2 4 6 8 TEMPERATURE (°C) Figure 4. Look-Up Table Hysteresis ____________________________________________________________________ 10 12 Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors and Password Protection Furthermore, as the device powers up, the VCClo alarm flag (bit 4 of 70h in Main Device) defaults to a 1 until the first VCC analog-to-digital conversion occurs and sets or clears the flag accordingly. 2-Wire Operation Clock and Data Transitions: The SDA pin is normally pulled high with an external resistor or device. Data on the SDA pin may only change during SCL-low time periods. Data changes during SCL-high periods will indicate a START or STOP condition depending on the conditions discussed below. See the timing diagrams in Figures 5 and 6 for further details. START Condition: A high-to-low transition of SDA with SCL high is a START condition that must precede any other command. See the timing diagrams in Figures 5 and 6 for further details. STOP Condition: A low-to-high transition of SDA with SCL high is a STOP condition. After a read or write sequence, the stop command places the DS1856 into a low-power mode. See the timing diagrams in Figures 5 and 6 for further details. Acknowledge: All address and data bytes are transmitted through a serial protocol. The DS1856 pulls the SDA line low during the ninth clock pulse to acknowledge that it has received each word. Standby Mode: The DS1856 features a low-power mode that is automatically enabled after power-on, after a STOP command, and after the completion of all internal operations. Device Addressing: The DS1856 must receive an 8-bit device address, the slave address byte, following a START condition to enable a specific device for a read or write operation. The address is clocked into this part MSB to LSB. The address byte consists of either A2h or the value in Table 03, 8Ch for the Main Device or A0h for the Auxiliary Device, then the R/W bit. This byte must match the address programmed into Table 03, 8Ch or A0h (for the Auxiliary Device). If a device address match occurs, this part will output a zero for one clock cycle as an acknowledge and the corresponding block of memory is enabled (see the Memory Organization section). If the R/W bit is high, a read operation is initiated. If the R/W is low, a write operation is initiated (see the Memory Organization section). If the address does not match, this part returns to a lowpower mode. Write Operations After receiving a matching address byte with the R/W bit set low, if there is no write protect, the device goes into the write mode of operation (see the Memory Organization section). The master must transmit an 8bit EEPROM memory address to the device to define the address where the data is to be written. After the byte has been received, the DS1856 transmits a zero for one clock cycle to acknowledge the address has been received. The master must then transmit an 8-bit data word to be written into this address. The DS1856 again transmits a zero for one clock cycle to acknowledge the receipt of the data. At this point, the master must terminate the write operation with a STOP condition. The DS1856 then enters an internally timed write process tw to the EEPROM memory. All inputs are disabled during this byte write cycle. Page Write The DS1856 is capable of an 8-byte page write. A page is any 8-byte block of memory starting with an address evenly divisible by eight and ending with the starting address plus seven. For example, addresses 00h through 07h constitute one page. Other pages would be addresses 08h through 0Fh, 10h through 17h, 18h through 1Fh, etc. ____________________________________________________________________ 27 DS1856 Power-Up and Low-Voltage Operation During power-up, the device is inactive until V CC exceeds the digital power-on-reset voltage (POD). At this voltage, the digital circuitry, which includes the 2-wire interface, becomes functional. However, EEPROMbacked registers/settings cannot be internally read (recalled into shadow SRAM) until VCC exceeds the analog power-on-reset voltage (POA), at which time the remainder of the device becomes fully functional. Once VCC exceeds POA, the RDYB bit in byte 6Eh of the Main Device memory is timed to go from a 1 to a 0 and indicates when analog-to-digital conversions begin. If VCC ever dips below POA, the RDYB bit reads as a 1 again. Once a device exceeds POA and the EEPROM is recalled, the values remain active (recalled) until VCC falls below POD. For 2-wire device addresses sourced from EEPROM (ADFIX = 1), the device address defaults to A2h until VCC exceeds POA and the EEPROM values are recalled. The Auxiliary Device (A0h) is always available within this voltage window (between POD and the EEPROM recall) regardless of the programmed state of ADEN. DS1856 Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors and Password Protection A page write is initiated the same way as a byte write, but the master does not send a STOP condition after the first byte. Instead, after the slave acknowledges the data byte has been received, the master can send up to seven more bytes using the same nine-clock sequence. The master must terminate the write cycle with a STOP condition or the data clocked into the DS1856 will not be latched into permanent memory. The address counter rolls on a page during a write. The counter does not count through the entire address space as during a read. For example, if the starting address is 06h and 4 bytes are written, the first byte goes into address 06h. The second goes into address 07h. The third goes into address 00h (not 08h). The fourth goes into address 01h. If 9 bytes or more are written before a STOP condition is sent, the first bytes sent are overwritten. Only the last 8 bytes of data are written to the page. Acknowledge Polling: Once the internally timed write has started and the DS1856 inputs are disabled, acknowledge polling can be initiated. The process involves transmitting a START condition followed by the device address. The R/W bit signifies the type of operation that is desired. The read or write sequence will only be allowed to proceed if the internal write cycle has completed and the DS1856 responds with a zero. Read Operations After receiving a matching address byte with the R/W bit set high, the device goes into the read mode of operation. There are three read operations: current address read, random read, and sequential address read. Current Address Read The DS1856 has an internal address register that maintains the address used during the last read or write operation, incremented by one. This data is maintained as long as VCC is valid. If the most recent address was the last byte in memory, then the register resets to the first address. Once the device address is clocked in and acknowledged by the DS1856 with the R/W bit set to high, the current address data word is clocked out. The master does not respond with a zero, but does generate a STOP condition afterwards. Single Read A random read requires a dummy byte write sequence to load in the data byte address. Once the device and data address bytes are clocked in by the master and acknowledged by the DS1856, the master must generate another START condition. The master now initiates a current 28 address read by sending the device address with the R/W bit set high. The DS1856 acknowledges the device address and serially clocks out the data byte. Sequential Address Read Sequential reads are initiated by either a current address read or a random address read. After the master receives the first data byte, the master responds with an acknowledge. As long as the DS1856 receives this acknowledge after a byte is read, the master can clock out additional data words from the DS1856. After reaching address FFh, it resets to address 00h. The sequential read operation is terminated when the master initiates a STOP condition. The master does not respond with a zero. The following section provides a detailed description of the 2-wire theory of operation. 2-Wire Serial-Port Operation The 2-wire serial-port interface supports a bidirectional data transmission protocol with device addressing. A device that sends data on the bus is defined as a transmitter, and a device that receives data as a receiver. The device that controls the message is called a master. The devices that are controlled by the master are slaves. The bus must be controlled by a master device that generates the serial clock (SCL), controls the bus access, and generates the START and STOP conditions. The DS1856 operates as a slave on the 2-wire bus. Connections to the bus are made through the open-drain I/O lines SDA and SCL. The following I/O terminals control the 2-wire serial port: SDA, SCL. Timing diagrams for the 2-wire serial port can be found in Figures 5 and 6. Timing information for the 2-wire serial port is provided in the AC Electrical Characteristics table for 2-wire serial communications. The following bus protocol has been defined: • Data transfer may be initiated only when the bus is not busy. • During data transfer, the data line must remain stable whenever the clock line is high. Changes in the data line while the clock line is high will be interpreted as control signals. Accordingly, the following bus conditions have been defined: Bus not busy: Both data and clock lines remain high. Start data transfer: A change in the state of the data line from high to low while the clock is high defines a START condition. ____________________________________________________________________ Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors and Password Protection SDA MSB SLAVE ADDRESS R/W DIRECTION BIT ACKNOWLEDGEMENT SIGNAL FROM RECEIVER ACKNOWLEDGEMENT SIGNAL FROM RECEIVER SCL 1 2 6 7 8 9 1 2 3–7 8 ACK START CONDITION 9 ACK STOP CONDITION OR REPEATED START CONDITION REPEATED IF MORE BYTES ARE TRANSFERRED Figure 5. 2-Wire Data Transfer Protocol SDA tBUF tHD:STA tLOW tR tSP tF SCL tHD:STA STOP tSU:STA tHIGH tSU:DAT START REPEATED START tSU:STO tHD:DAT Figure 6. 2-Wire AC Characteristics ____________________________________________________________________ 29 DS1856 plished on the 2-wire bus. Depending on the state of the R/W bit, two types of data transfer are possible. Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of data bytes transferred between START and STOP conditions is not limited and is determined by the master device. The information is transferred byte-wise and each receiver acknowledges with a ninth bit. Stop data transfer: A change in the state of the data line from low to high while the clock line is high defines the STOP condition. Data valid: The state of the data line represents valid data when, after a START condition, the data line is stable for the duration of the high period of the clock signal. The data on the line can be changed during the low period of the clock signal. There is one clock pulse per bit of data. Figures 5 and 6 detail how data transfer is accom- DS1856 Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors and Password Protection Within the bus specifications, a standard mode (100kHz clock rate) and a fast mode (400kHz clock rate) are defined. The DS1856 works in both modes. Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge after the byte has been received. The master device must generate an extra clock pulse, which is associated with this acknowledge bit. A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is a stable low during the high period of the acknowledge-related clock pulse. Setup and hold times must be taken into account. A master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data line high to enable the master to generate the STOP condition. 1) Data transfer from a master transmitter to a slave receiver. The first byte transmitted by the master is the command/control byte. Next follows a number of data bytes. The slave returns an acknowledge bit after each received byte. 2) Data transfer from a slave transmitter to a master receiver. The master transmits the first byte (the command/control byte) to the slave. The slave then returns an acknowledge bit. Next follows a number of data bytes transmitted by the slave to the master. The master returns an acknowledge bit after all received bytes other than the last byte. At the end of the last received byte, a not acknowledge can be returned. 30 The master device generates all serial clock pulses and the START and STOP conditions. A transfer is ended with a STOP condition or with a repeated START condition. Since a repeated START condition is also the beginning of the next serial transfer, the bus is not released. The DS1856 can operate in the following two modes: 1) Slave Receiver Mode: Serial data and clock are received through SDA and SCL, respectively. After each byte is received, an acknowledge bit is transmitted. START and STOP conditions are recognized as the beginning and end of a serial transfer. Address recognition is performed by hardware after the slave (device) address and direction bit have been received. 2) Slave Transmitter Mode: The first byte is received and handled as in the slave receiver mode. However, in this mode the direction bit indicates that the transfer direction is reversed. Serial data is transmitted on SDA by the DS1856, while the serial clock is input on SCL. START and STOP conditions are recognized as the beginning and end of a serial transfer. ____________________________________________________________________ Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors and Password Protection PART RES0/RES1 RESISTANCE (kΩ) PIN-PACKAGE PART RES0/RES1 RESISTANCE (kΩ) PIN-PACKAGE DS1856B-050/T&R 50/50 16-Ball CSBGA DS1856E-030+T&R* 30/10 16 TSSOP DS1856E-050+ 50/50 16 TSSOP DS1856B-030+* 30/10 16-Ball CSBGA DS1856E-050+T&R 50/50 16 TSSOP DS1856B-030+T&R* 30/10 16-Ball CSBGA DS1856B-050+ 50/50 16-Ball CSBGA DS1856E-002 10/2.5 16 TSSOP DS1856B-050+T&R 50/50 16-Ball CSBGA DS1856E-002/T&R 10/2.5 16 TSSOP 10/2.5 16-Ball CSBGA DS1856E-020* 20/20 16 TSSOP DS1856B-002 DS1856E-020/T&R* 20/20 16 TSSOP DS1856B-002/T&R 10/2.5 16-Ball CSBGA DS1856B-020* 20/20 16-Ball CSBGA DS1856E-002+ 10/2.5 16 TSSOP 16-Ball CSBGA DS1856E-002+T&R 10/2.5 16 TSSOP 16-Ball CSBGA DS1856B-020/T&R* 20/20 DS1856E-020+* 20/20 16 TSSOP DS1856B-002+ 10/2.5 DS1856E-020+T&R* 20/20 16 TSSOP DS1856B-002+T&R 10/2.5 16-Ball CSBGA 2.5/2.5 16 TSSOP 16 TSSOP DS1856B-020+* 20/20 16-Ball CSBGA DS1856E-025 DS1856B-020+T&R* 20/20 16-Ball CSBGA DS1856E-025/T&R 2.5/2.5 DS1856E-030* 30/10 16 TSSOP DS1856B-025 2.5/2.5 16-Ball CSBGA 2.5/2.5 16-Ball CSBGA DS1856E-030/T&R* 30/10 16 TSSOP DS1856B-025/T&R DS1856B-030* 30/10 16-Ball CSBGA DS1856E-025+ 2.5/2.5 16 TSSOP DS1856B-030/T&R* 30/10 16-Ball CSBGA DS1856E-025+T&R 2.5/2.5 16 TSSOP 16 TSSOP DS1856B-025+ 2.5/2.5 16-Ball CSBGA DS1856B-025+T&R 2.5/2.5 16-Ball CSBGA DS1856E-030+* 30/10 Chip Information TRANSISTOR COUNT: 51,061 SUBSTRATE CONNECTED TO GROUND +Denotes lead free. *Future product—contact factory for availability. T&R denotes tape-and-reel. All parts operate at the -40°C to +95°C temperature range. Package Information For the latest package outline information, go to www.maxim-ic.com/DallasPackInfo. Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 31 © 2005 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc. DALLAS is a registered trademark of Dallas Semiconductor Corporation. DS1856 Ordering Information (continued)