350 MHz FET Buffer Features General Description # # # # # # # The EL2004 is a very high-speed, FET input buffer/line driver designed for unity gain applications at both high current (up to 100 mA) and at frequencies up to 350 MHz. The 2500 V/ms slew rate and wide bandwidth ensures the stability of the circuit when the EL2004 is used inside op amp feedback loops. Slew rateÐ2500 V/ms Rise timeÐ1 ns BandwidthÐ350 MHz ELH0033Ðpin compatible g 5 to g 15V operation 100 mA output current MIL-STD-883B Rev. C devices manufactured in U.S.A. Applications # # # # # # # Coaxial cable driver Fast op amp booster Flash converter driver Video line driver High-speed sample and hold Pulse transformer driver A.T.E. pin driver Temp. Range Applications for the EL2004 include line drivers, video buffers, wideband instrumentation, and high-speed drivers for inductive and capacitive loads. The performance of the EL2004 makes it an ideal buffer for video applications including input buffers for flash A/D converters, and output buffers for video DACs. Its excellent phase linearity is particularly advantageous in digital signal processing applications. Elantec facilities comply with MIL-I-45208A and are MILSTD-1772 certified. Elantec’s Military devices comply with MIL-STD-883B Revision C and are manufactured in our rigidly controlled, ultra-clean facilities in Milpitas, California. For additional information on Elantec’s Quality and Reliability Assurance Policy and procedures request brochure QRA-1. Ordering Information Part No. EL2004/EL2004C EL2004/EL2004C Package OutlineÝ EL2004CG b 25§ C to a 85§ C TO-8 MDP0002 EL2004G b 55§ C to a 125§ C TO-8 MDP0002 EL2004L b 55§ C to a 125§ C 52-Pad LCC MDP0013 Simplified Schematic EL2004L/MIL b 55§ C to a 125§ C 52-Pad LCC MDP0013 5962-89659 is the SMD version of this device. Connection Diagram Case is Electrically Isolated 2004 – 3 Note: All information contained in this data sheet has been carefully checked and is believed to be accurate as of the date of publication; however, this data sheet cannot be a ‘‘controlled document’’. Current revisions, if any, to these specifications are maintained at the factory and are available upon your request. We recommend checking the revision level before finalization of your design documentation. Patent pending. © 1989 Elantec, Inc. November 1993 Rev G 2004 – 1 Top View EL2004/EL2004C 350 MHz FET Buffer Absolute Maximum Ratings (TA e 25§ C) Supply Voltage (V a b Vb) Input Voltage Power Dissipation (See curves) Continuous Output Current Peak Output Current VS VIN PD IOC IOP TA 40V 40V 1.5W g 100 mA g 250 mA Operating Temperature Range EL2004 EL2004C Operating Junction Temperature Storage Temperature Lead Temperature (Soldering, 10 seconds) TJ TST b 55§ C to a 125§ C b 25§ C to a 85§ C 175§ C b 65§ C to a 150§ C 300§ C Important Note: All parameters having Min/Max specifications are guaranteed. The Test Level column indicates the specific device testing actually performed during production and Quality inspection. Elantec performs most electrical tests using modern high-speed automatic test equipment, specifically the LTX77 Series system. Unless otherwise noted, all tests are pulsed tests, therefore TJ e TC e TA. Test Level I II III IV V Test Procedure 100% production tested and QA sample tested per QA test plan QCX0002. 100% production tested at TA e 25§ C and QA sample tested at TA e 25§ C , TMAX and TMIN per QA test plan QCX0002. QA sample tested per QA test plan QCX0002. Parameter is guaranteed (but not tested) by Design and Characterization Data. Parameter is typical value at TA e 25§ C for information purposes only. g 15V DC Electrical Characteristics VS e g 15V, TMIN k TA k TMAX, VIN e 0V, RL e 1 kX unless otherwise specified (Note 1) Description Test Conditions Min Typ Max EL2004C Test Level Min Test Level Units 20 I mV 25 III mV 0.98 1.0 II V/V 0.98 II V/V I X II X Typ Max 12 Output Offset Voltage RS s 100 kX, TJ e 25§ C AV Voltage Gain VIN e g 10V 0.97 RL e 100X, VIN e g 10V RIN Input Impedance TJ e 25§ C, VIN e g 1V ROUT Output Impedance VIN e g 1 VDC, DRL e 100X to Infinity VO Output Voltage Swing VIN e g 14V g 12 g 13 I g 12 g 13 II V VIN e g 10.5V, RL e 100X TA e 25§ C g9 g 9.8 I g9 g 9.8 I V I nA VOS IIN Input Current 5 10 I 15 I 0.98 1.0 I 0.96 0.92 0.95 0.98 I 0.90 0.95 108 1011 I 108 1011 RS s 100 kX 4 I 4 10 TJ e 25§ C (Note 2) 0.25 I TA e 25§ C (Note 3) 2.5 IV 20 IV nA TJ e TA e TMAX 10 I 50 III nA V nA II mA VIN e b10V IS 8 20 Supply Current 20 2 24 2.0 V 20 I 20 24 TD is 3.2in EL2004 Parameter EL2004/EL2004C 350 MHz FET Buffer g 5V DC Electrical Characteristics VS e g 5V, TMIN k TA k TMAX, VIN e 0V, RL e 50X unless otherwise specified Description Test Conditions Min EL2004C Typ Max Test Level 10 30 I 35 I Min Test Level Units 30 I mV 35 III mV Typ Max 10 Output Offset Voltage RS s 100 kX, TJ e 25§ C Voltage Gain VIN e g 1V, RL e 1 kX 0.90 0.95 1.0 I 0.90 0.95 1.0 II V/V VIN e g 1V 0.80 0.88 0.95 I 0.80 0.88 0.95 II V/V Input Impedance TJ e 25§ C, VIN e g 1V 108 1011 I 1010 1011 I X ROUT Output Impedance VIN e g 1 VDC, DRL e 50X to Infinity II X VO Output Voltage Swing VIN e g 4V III V IIN Input Current VOS AV RIN RS s 100 kX 4 g 2.0 8 g 2.9 I I 4 g 2.0 10 g 2.9 TJ e 25§ C (Note 2) 250 I 500 I pA TA e 25§ C (Note 3) 2.5 IV 5 IV nA TJ e TA e TMAX 10 I 20 III nA V dB II mA PSRR Power Supply Rejection Ratio VS e g 5V to g 15V RL e 1 kX IS Supply Current RL e 1 kX 60 17.5 20 V 60 I 17.5 20 TD is 3.2in EL2004 Parameter Note 1: When operating at elevated temperatures the power dissipation of the EL2004 must be limited to the values shown in the typical performance curve ‘‘Maximum Power Dissipation vs Temperature’’. Junction to case thermal resistance is 31§ C/W when dissipation is spread among the transistors in a normal AC steady-state condition. In special conditions where heat is concentrated in one output device, junction temperature should be calculated using a thermal resistance of 70§ C/W. Note 2: Specification is at 25§ C junction temperature due to requirements of high-speed automatic testing. Actual values at operating temperatures will exceed the value at TJ e 25§ C. When supply voltages are g 15V, no-load operating junction temperatures may rise 40§ C to 60§ C above ambient and more under load conditions. Accordingly, VOS may change one to several mV, and IIN will change significantly during warm-up. Refer to IIN vs Temperature graph for expected values. Note 3: Measured in still air seven minutes after application of power. See graph of Input Current During Warm-up for further information. Note 4: Bandwidth is calculated from the rise time. The EL2004 has a single pole gain and phase response up to the b3 dB frequency. Note 5: Slew rate is measured between VOUT e a 2.5V and b2.5V for this test. Note 6: Slew rate is measured between VOUT e a 1V and b1V for this test. Pulse repetition rate is k50 MHz. g 15V AC Electrical Characteristics VS e g 15V, RL e 1 kX, RS e 50X, TJ e 25§ C unless otherwise specified BW Description Bandwidth ts Settling Time to 1% Cin Input Capacitance Test Conditions Units I MHz 200 I MHz 6 V ns 3 V pF Typ I 200 350 140 Typ (Note 4) 200 350 RL e 50X 140 200 I 6 V 3 V 3 Test Level Min Min DVIN e 1V, tr e 3 ns Max EL2004C Test Level Max TD is 1.3in EL2004 Parameter EL2004/EL2004C 350 MHz FET Buffer g 15V AC Electrical Characteristics VS e g 15V, RL e 1 kX, RS e 50X, TJ e 25§ C unless otherwise specified Ð Contd. EL2004 SR Description Slew Rate Test Conditions VIN e g 5V (Note 5) 2000 2500 I 2000 2500 I V/ms 1200 V 1200 V V/ms CL e 100 pF, VIN e g 5V (Note 5) tr EL2004C Test Test Units Min Typ Max Min Typ Max Level Level Rise Time DVIN P 0.6V Note: See Test Figure DVIN P 0.6V, RL e 50X 1.0 1.7 I 1.0 1.7 I ns 1.7 2.5 I 1.7 2.5 I ns 1.0 2.0 I 1.0 2.0 I ns tp Propagation Delay DVIN P 0.6V Note: See Test Figure ROUT Output Impedance f e 1 MHz, VIN e 1 VRMS DRL e 100X to Infinity 4 V 4 V X a PSRR Power Supply Rejection Ratio DVS a e g 1.5 Vpeak f e 1 kHz 40 V 40 V dB b PSRR Power Supply Rejection Ratio DVSb e g 1.5 Vpeak f e 1 kHz 40 V 40 V dB TD is 2.7in Parameter g 5V AC Electrical Characteristics VS e g 5V, RL e 50X, RS e 50X, TJ e 25§ C unless otherwise specified EL2004 BW Description Bandwidth ts Settling Time to 1% Cin Input Capacitance SR Slew Rate Test Conditions RL e 1 kX 175 220 I 175 220 I MHz (Note 4) 125 150 IV 125 150 IV MHz 8 V 8 V ns 3 V 3 V pF 1200 I 1200 I V/ms 500 V 500 V V/ms DVIN e 1V, tr e 3 ns VIN e g 2V (Note 6) 900 CL e 100 pF, VIN e g 2V RL e 1 kX (Note 6) tr EL2004C Test Test Units Min Typ Max Min Typ Max Level Level Rise Time RL e 1 kX, DVIN P 0.6V Note: See Test Figure RL e 50X, DVIN P 0.6V 900 1.6 2.0 I 1.6 2.0 I ns 2.3 2.8 IV 2.3 2.8 IV ns 1.2 2.4 I 1.2 2.4 I ns tp Propagation Delay RL e 1 kX, DVIN P 0.6V Note: See Test Figure ROUT Output Impedance f e 1 MHz, VIN e 1 VRMS DRL e 100X to Infinity 4 V 4 V X a PSRR Power Supply Rejection Ratio DVSb e g 0.5 Vpeak f e 1 kHz 30 V 30 V dB b PSRR Power Supply Rejection Ratio DVS a e g 0.5 Vpeak f e 1 kHz 30 V 30 V dB 4 TD is 3.4in Parameter EL2004/EL2004C 350 MHz FET Buffer AC Test Circuit 2004 – 4 Typical Performance Curves TO-8 Maximum Power Dissipation 2004 – 5 Output Resistance vs Output Current Gain vs Input Voltage 2004 – 7 5 EL2004/EL2004C 350 MHz FET Buffer Typical Performance Curves Ð Contd. Rise Time vs Temperature Frequency Response Small Signal Pulse Response Large Signal Pulse Response Offset Voltage vs Supply Voltage Normalized Input Bias Current During Warm-up Supply Current vs Supply Voltage Output Voltage vs Supply Voltage 2004 – 8 6 EL2004/EL2004C 350 MHz FET Buffer Input Bias Current vs Temperature Applications Information The EL2004 is one member of a family of high performance buffers manufactured by Elantec. The 2004 is optimized for speed while others offer choices of input DC parameters or output drive or cost. The following table illustrates those members available at the time of this printing. Consult the factory for the latest capabilities in this developing line. Elantec’s Buffer Family Part Ý ELH0002 ELH0033 EL2004 EL2005 Slew Rate V/ms Bandwidth MHz Input Current (Warm) Peak IOUT mA Rise Time ns 200 1500 2500 1500 50 100 350 140 6 mA 2.5 nA 2.5 nA 0.1 nA 400 250 250 250 7 2.9 1.0 2.5 Input Bias Current vs Input Voltage Recommended Layout Precautions The very high-speed performance of the EL2004 can only be realized by taking certain precautions in circuit layout and power supply decoupling. Low inductance ceramic chip or disc power supply decoupling capacitors of 0.1 mF or more should be connected with the shortest practical lead lengths between the device supply leads and a ground plane. In addition, it can be helpful to parallel these with 4.7 mF electrolytics (Tantalum preferred). Failure to follow these precautions can result in oscillation. 2004 – 9 In applications such as sample and hold circuits where it is important to maintain low input bias current over input voltage range, the EL2005 High Accuracy Fast Buffer is recommended. The input capacitance of EL2004 comprises the FET device gate-to-source capacitance (which is a function of input voltage) and stray capacitance to the case. Effective input capacitance can be minimized by connecting the case to the output since it is electrically isolated. Or, for reduced radiation, the case may be grounded. The AC characteristics specified in this data sheet were obtained with the case floating. Circuit Operation The EL2004 is effectively an ideal unity gain amplifier with almost infinite input impedance and about 6X output impedance. Input Characteristics The input impedance of a junction FET is a strong function of temperature and input voltage. Nominal input resistance of EL2004 is 1012 at 25§ C junction, but as IB doubles every 11§ C in the JFET, the input resistance falls. During warm-up, self-heating raises the junction temperature up to 60§ C or more (without heatsink) so operating IB will be much higher than the data sheet 25§ C specification. Offset Voltage Adjustment The EL2004’s offset voltages have been actively laser trimmed at g 15V supplies to meet specified limits when the offset adjust pin is shorted to the offset preset pin. If external offset null is required, the offset adjust pin should be connected to a 200X trim pot connected to the negative supply. Another factor which can increase bias current is input voltage. If the input voltage is more than 20V below the positive supply, the input current rises exponentially. (See Curve.) 7 EL2004/EL2004C 350 MHz FET Buffer Current Limiting Using Current Sources Circuit Operation Ð Contd. Offset Zero Adjust 2004 – 10 Capacitive Loading The EL2004 is designed to drive capacitive loads up to several thousand picofarads without oscillation. However, peak current resulting from charging currents on fast edges should be limited below the absolute maximum peak current rating of 250 mA. In some cases it may be necessary to employ one of the current limit schemes shown below. 2004 – 12 The inclusion of limiting resistors in the collectors of the output devices will reduce the output voltage swing and speed. Decoupling VC a and VC b pins with capacitors to ground will retain full output swing for transient pulses. Short Circuit Protection Dynamic response of the EL2004 was preserved by excluding current limit circuits which are not needed in most applications. However, in situations where operating conditions are not controlled, short circuit protection can be added by inserting resistors between the output device collectors and supplies as illustrated. An alternate active current limit technique that retains full DC output swing is shown above. Here the current sources are saturated during normal operation thus applying full supply voltage to the VC pins. Under fault conditions, the voltage decreases as the current source reaches its limit. Using Resistor Current Limiting RLIM e VBE 0.6V e e 6X ISC 100 mA Power Supplies The EL2004 has been characterized for both g 15 and g 5V dual supply operation, but other combinations can also be useful. For example, in many video applications it is only necessary for the output to swing g 2V or less, but speed and distortion are important. In this situation, the input stage can be operated at the full g 15V supply while the output collectors are returned to g 5V. The speed and distortion will be almost as good as if the whole circuit was operating at g 15V, but the dissipation is substantially reduced and higher load currents can be safely accommodated. 2004 – 11 Suitable resistor values can be calculated as follows: RSC e Va Vb e ISC ISC where ISC s 100 mA for EL2004. 8 EL2004/EL2004C 350 MHz FET Buffer Circuit Operation Ð Contd. General Application Suggestions Increasing Operating Voltage and Reducing Thermal Tail Video DAC Buffer Many of the available video D to A converters are unable to directly drive 50X or 75X cables. The EL2004’s excellent phase linearity at video frequencies make it an ideal solution. In critical applications or where line termination is not controlled, a matching pad should be used as shown. The capacitor should be adjusted for optimum pulse response. If properly layed out this circuit will not overshoot. When driving heavy loads, the changing dissipation in the output transistors can sometimes cause temperature gradients in the circuit which cause a shift in offset voltage and the phenomenon known as ‘‘thermal tail’’. Bootstrapping the output as illustrated substantially reduces the power in the output transistors and mitigates the effect. Video DAC Buffer High Voltage Inputs can be Accommodated with Bootstrapped Supplies 2004 – 14 Impedance Matching The EL2004 provides power gain and isolation between source and load when used as an active tap or impedance matching device as illustrated here. In this example, there is no output matching pad between the 2004 and the 75X line. Such matching is not needed when the distant end of the cable is properly terminated as there is no reflected signal to worry about and the 2004 isolates the source. This technique allows the full output voltage of the EL2004 to be applied to the load. 2004 – 13 Hardware In order to utilize the full drive capabilities of the EL2004, it should be mounted with a heatsink, particularly for extended temperature operation. Suitable heatsinks include Thermalloy 2240A (33§ C/W), Wakefield 215CB (30§ C/W) and IERC-UP-TO-848CB (15§ C/W). Impedance Converter The case is isolated from the circuit and may be connected to system chassis. Sockets are not recommended as they add substantial inductance and capacitance which impair the performance of the device. However, for test purposes they are unavoidable and precautions such as shielding input from output are suggested. 2004 – 15 9 EL2004/EL2004C 350 MHz FET Buffer General Application Suggestions Ð Contd. Inverting Amplifier for 20 MHz Flash Converter 2004 – 16 EL2004. For example, a 50X cable driver with g 10V capability can be made by using two EL2004’s. A short-circuit protected version is shown below. Boosting the Output Unlike most integrated cicuits, two or more EL2004’s can be paralleled for increased output drive. This capability results from the finite output resistance and low output mismatch of the 50X Cable Driver with Short Circuit Protection NPN e 2N6551 PNP e 2N6554 ( 2W devices or equivalent 2004 – 17 10 EL2004/EL2004C 350 MHz FET Buffer Burn-In Circuit 2004 – 18 Pin numbers are for TO-8 package. LCC uses the same schematic. 11 EL2004/EL2004C TAB WIDE 350 MHz FET Buffer EL2004 Macromodel input l l l l l l Va l l l l l Vc a l l l l Vb l Vcb * output l l * l l l .subckt M2004 5 12 1 10 9 11 * Models .model qn npn (is e 5eb14 bf e 150 vaf e 100 rc e 1 rb e 5 re e 1 ikf e 200mA a cje e 5pF cjc e 5pF mje e .42 mjc e .23 tf e .3nS tr e 200nS br e 5 vtf e 0) .model qp pnp (is e 5eb14 bf e 150 vaf e 100 rc e 2 rb e 3 re e 1 ikf e 100mA a cje e 5.7pF cjc e 4pF tf e .3nS mje e .32 mjc e .43 tr e 170nS br e 5 vtf e 0) .model qf njf (vto eb3V beta e 4.0eb3 cgd e 4pF cgs e 10pF lambda e 671.0eb6) * Resistors r1 20 21 58.33 r2 27 10 58.33 r3 22 11 2 r4 11 23 2 * Transistors j1 12 5 20 qf j4 24 10 26 qf q2 21 21 25 qn q3 24 24 25 qp q5 1 21 22 qn q6 9 24 23 qp q7 26 26 27 qn .ends 12 TD is 3.8in * Connections: * * * * EL2004/EL2004C 350 MHz FET Buffer EL2004 Macromodel Ð Contd. 2004 – 19 13 14 BLANK 15 BLANK EL2004/EL2004C EL2004/EL2004C 350 MHz FET Buffer General Disclaimer Specifications contained in this data sheet are in effect as of the publication date shown. Elantec, Inc. reserves the right to make changes in the circuitry or specifications contained herein at any time without notice. Elantec, Inc. assumes no responsibility for the use of any circuits described herein and makes no representations that they are free from patent infringement. November 1993 Rev G WARNING Ð Life Support Policy Elantec, Inc. products are not authorized for and should not be used within Life Support Systems without the specific written consent of Elantec, Inc. Life Support systems are equipment intended to support or sustain life and whose failure to perform when properly used in accordance with instructions provided can be reasonably expected to result in significant personal injury or death. Users contemplating application of Elantec, Inc. products in Life Support Systems are requested to contact Elantec, Inc. factory headquarters to establish suitable terms & conditions for these applications. Elantec, Inc.’s warranty is limited to replacement of defective components and does not cover injury to persons or property or other consequential damages. Elantec, Inc. 1996 Tarob Court Milpitas, CA 95035 Telephone: (408) 945-1323 (800) 333-6314 Fax: (408) 945-9305 European Office: 44-71-482-4596 16 Printed in U.S.A.