EMIF04-10006F2 ® 4 LINES EMI FILTER AND ESD PROTECTION IPAD™ MAIN PRODUCT CHARACTERISTICS Where EMI filtering in ESD sensitive equipment is required: ■ Mobile phones and communication systems ■ Computers, printers and MCU Boards ® DESCRIPTION The EMIF04-10006F2 is a highly integrated devices designed to suppress EMI/RFI noise in all systems subjected to electromagnetic interferences. The EMIF04 flip-chip packaging means the package size is equal to the die size. This filter includes an ESD protection circuitry which prevents the device from destruction when subjected to ESD surges up 15kV. This device includes four EMIF filters and 4 separated ESD diodes. BENEFITS ■ EMI symmetrical (I/O) low-pass filter ■ High efficiency in EMI filtering ■ Lead free package ■ Very low PCB space consuming: 2.92mm x 1.29mm ■ Very thin package: 0.65 mm ■ High efficiency in ESD suppression (IEC61000-4-2 level 4) ■ High reliability offered by monolithic integration ■ High reducing of parasitic elements through integration and wafer level packaging. Flip-Chip (15 Bumps) Table 1: Order Code Part Number EMIF04-10006F2 Marking FS Figure 1: Pin Configuration (ball side) 9 8 D3 COMPLIES WITH THE FOLLOWING STANDARDS: IEC 61000-4-2 level 4: 15kV (air discharge) 8kV (contact discharge) MIL STD 883E - Method 3015-6 Class 3: 30kV 7 6 I4 I3 Gnd D4 O4 5 4 3 I2 I1 Gnd O3 2 1 D1 Gnd O2 O1 A B D2 C TM: IPAD is a trademark of STMicroelectronics. September 2004 REV. 1 1/7 EMIF04-10006F2 Figure 2: Basic Cell Configuration 100Ω 100Ω Input 1 Output 1 30pF Input 4 Output 4 30pF 30pF 30pF 100Ω Input 2 Output 2 30pF D1 30pF D2 30pF 30pF 30pF 30pF 100Ω Input 3 Output 3 30pF 30pF D3 D4 Table 2: Absolute Ratings (limiting values) Symbol Parameter and test conditions PR DC power per resistance Unit 0.1 W PT Total DC power per package 0.6 W Tj Maximum junction temperature 125 °C - 40 to + 85 °C 125 °C Top Operating temperature range Tstg Storage temperature range Table 3: Electrical Characteristics (Tamb = 25 °C) Symbol Parameter VBR Breakdown voltage IRM Leakage current @ VRM VRM Stand-off voltage VCL Clamping voltage Rd Dynamic impedance IPP Peak pulse current RI/O Series resistance between Input and output Cline Capacitance per line Symbol VBR 2/7 Value I IF VF VCL VBR VRM Test conditions IR = 1 mA V IRM IR IPP Min. 5.5 Typ. 7 Max. 9 Unit V 500 nA IRM VRM = 3.3 V per line RI/O I = 10 mA 80 100 120 Ω Cline VR = 2.5 V, F = 1 MHz, 30 mV (on filter cells) 50 60 70 pF EMIF04-10006F2 Figure 3: S21 (dB) attenuation measurements and Aplac simulation Figure 4: Analog crosstalk measurements Aplac 7.62 User: ST Microelectronics 0.00 00 dB dB -12.50 -25 i3_o2.s2p -25.00 -50 -37.50 -75 Measurement Simulation f/Hz -50.00 100.0k f/Hz -100 1.0M 10.0M 100.0M 1.0G 100k 10M 1M 100M 1G Figure 5: Digital crosstalk measurements Figure 6: ESD response to IEC61000-4-2 (+15kV air discharge) on one imput V(in) and one output V(out) Figure 7: ESD response to IEC61000-4-2 (–15kV air discharge) on one imput V(in) and one output V(out) Figure 8: Line capacitance versus applied voltage for filter C(pF) 100 90 F=1MHz Vosc=30mVRMS Tj=25°C 80 70 60 50 40 30 20 10 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VR(V) 3/7 EMIF04-10006F2 Figure 9: Aplac model Rbump Lbump Rs=100 Lbump Rbump Ii* Oi* sub Cz=41pF@0V Cbump Rsub Cz=41pF@0V Rsub Rbump sub Oi * = Output of each filter cell Ii* = Input of each filter cell Rbump Lbump Lbump Lbump Cgnd Rbump Lgnd Di* Dj * Rgnd Cz=41pF@0V Cbump Rsub Cbump Cz=41pF@0V With Dj* = D1 & D3 And Di* = D2 & D4 Rsub sub EMIF04-10006F2 model Ground return for each GND bump Figure 10: Aplac parameters 4/7 Rsub Cbump aplacvar RS 100Ω aplacvar Cz 41 pF aplacvar Lbump 50 pH aplacvar Rbump 20 m aplacvar Cbump 1.2 pF aplacvar Rsub 100 m aplacvar Rgnd 100 m aplacvar Lgnd 100 pH aplacvar Cgnd 0.15 pF EMIF04-10006F2 Figure 11: Order code EMIF yy - xxx zz Fx EMI Filter Number of lines Information x = resistance value (Ohms) z = capacitance value / 10(pF) or 3 letters = application 2 digits = version Package F = Flip-Chip x = 1: 500µm, Bump = 315µm = 2: Leadfree Pitch = 500µm, Bump = 315µm Figure 12: FLIP-CHIP Package Mechanical Data 435µm ± 50 315µm ± 50 500µm ± 50 650µm ± 65 50 1µ m ±5 0 1.29mm ± 50µm 250µm ± 50 2.92mm ± 50µm Figure 13: Foot print recommendations Dot, ST logo xx = marking z = packaging location yww = datecode (y = year ww = week) 545 400 545 Copper pad Diameter : 250µm recommended , 300µm max Figure 14: Marking E Solder stencil opening : 330µm 230 x x z y w w 100 Solder mask opening recommendation : 340µm min for 300µm copper pad diameter All dimensions in µm 5/7 EMIF04-10006F2 Figure 15: FLIP-CHIP Tape and Reel Specification Dot identifying Pin A1 location Ø 1.5 +/- 0.1 1.75 +/- 0.1 4 +/- 0.1 3.5 +/- 0.1 STE xxz yww STE xxz yww STE xxz yww 8 +/- 0.3 0.73 +/- 0.05 4 +/- 0.1 User direction of unreeling All dimensions in mm Table 4: Ordering Information Ordering code Marking Package Weight Base qty Delivery mode EMIF04-10006F2 FS Flip-Chip 5.4 mg 5000 Tape & reel 7” Note: More packing informations are available in the application note AN1235: “Flip-Chip: Package description and recommendations for use” AN1751: "EMI Filters: Recommendations and measurements" Table 5: Revision History Date 08-Sep-2004 6/7 Revision 1 Description of Changes First issue EMIF04-10006F2 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. 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