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FSDM101
Green Mode Fairchild Power Switch (FPSTM)
Features
•
•
•
•
•
•
•
•
•
•
Internal Avalanche Rugged Sense FET
Precision Fixed Operating Frequency (67kHz)
Internal Start-up Switch and Soft Start
Under Voltage Lock Out (UVLO) with Hysteresis
Pulse by Pulse Current Limit
Over Load Protection (OLP)
Over Voltage Protection (OVP)
Internal Thermal Shutdown Function (TSD)
Secondary Side Regulation
Auto-Restart Mode
Applications
•
•
•
•
Charger & Adaptor for Mobile Phone, PDA & MP3
Auxiliary Power for White Goods, PC, C-TV & Monitor
SMPS for VCR, SVR, STB, DVD, and DVCD
Adaptor for Camcorder
Description
The FSDM101 is an integrated Pulse Width Modulator
(PWM) and Sense FET specially designed for high performance off-line Switch Mode Power Supplies (SMPS) with
minimal external components. This device is a monolithic
high voltage power switching regulator which combines a
VDMOS Sense FET with a voltage mode PWM control
block. The integrated PWM controller features include: a
fixed oscillator, Under Voltage Lock Out (UVLO) protection, Leading Edge Blanking (LEB), optimized gate turn-on/
turn-off driver, thermal shut down protection (TSD), temperature compensated precision current sources for loop compensation and fault protection circuitry. When compared to a
discrete MOSFET and controller or RCC switching converter solution, the FSDM101 reduces total component
count, design size, weight and at the same time increases
efficiency, productivity, and system reliability. This device is
a basic platform well suited for cost effective designs of flyback converters.
FPSTM is a trademark of Fairchild Semiconductor Corporation.
©2005 Fairchild Semiconductor Corporation
TYPICAL OUTPUT POWER CAPABILITY
PRODUCT
Open Frame(1)
230VAC ±15%(2)
85-265VAC
13W
8W
FSDM101
PEAK OUTPUT POWER CAPABILITY(3)
PRODUCT
Open Frame(1)
230VAC ±15%(2)
85-265VAC
17W
12W
FSDM101
Table 1. Notes: 1. Maximum practical continuous power
in an open frame design with a sufficient drain pattern as
a heat sinker at 50°C ambient temperature. 2. 230 VAC or
100/115 VAC with doubler. 3. Peak output power means
the maximum power can be handled instantaneously.
Typical Circuit
AC
IN
DC
OUT
Vstr
Drain
PWM
Vfb
Vcc
Source
Figure 1. Typical Flyback Application Using FSDM101
Rev.1.0.1
FSDM101
Internal Block Diagram
Vstr
5
6,7,8
L
Vcc 2
Internal
Bias
Voltage
Ref
UVLO
Drain
H
9.0/7.0V
Vck
OSC
2.5uA
400uA
PWM
Vfb 3
SFET
DRIVER
S
Q
R
S/S
15mS
LEB
NC 4
OLP
Iover
Reset
S
V SD
Min.20V
Q
Rsense
Vth
R
OVP
TSD
A/R
1
Figure 2. Functional Block Diagram of FSDM101
2
GND
FSDM101
Pin Definitions
Pin Number
Pin Name
1
GND
Sense FET source terminal on primary side and internal control ground.
Vcc
Positive supply voltage input. Although connected to an auxiliary
transformer winding, current is supplied from pin 5 (Vstr) via an internal
switch during startup (see Internal Block Diagram section). It is not until Vcc
reaches the UVLO upper threshold (9V) that the internal start-up switch
opens and device power is supplied via the auxiliary transformer winding.
Vfb
The feedback voltage pin is the inverting input to the PWM comparator with
nominal input levels between 0.5Vand 2.5V. It has a 0.40mA current source
connected internally while a capacitor and optocoupler are typically
connected externally. A feedback voltage of 4.5V triggers overload
protection (OLP). There is a time delay while charging between 3V and 4.5V
using an internal 2.5uA current source, which prevents false triggering under
transient conditions, but still allows the protection mechanism to operate
under true overload conditions.
Vstr
The startup pin connects directly to the rectified AC line voltage source for
FSDM101. For the FSDM101, at start up the internal switch supplies internal
bias and charges an external storage capacitor placed between the Vcc pin
and ground. Once this reaches 9V, the internal current source is disabled.
Drain
The Drain pin is designed to connect directly to the primary lead of the
transformer and is capable of switching a maximum of 650V. Minimizing the
length of the trace connecting this pin to the transformer will decrease
leakage inductance.
2
3
5
6, 7, 8
Pin Function Description
Pin Configuration
8DIP
GND 1
8 Drain
Vcc 2
7 Drain
Vfb 3
6 Drain
NC 4
5 Vstr
Figure 3. Pin Configuration (Top View)
3
FSDM101
Absolute Maximum Ratings
(Ta=25°C unless otherwise specified)
Parameter
Maximum Vstr Pin Voltage
Maximum Drain Pin Voltage
Drain Current Pulsed
Symbol
Value
Unit
VSTR,MAX
650
V
VDRAIN,MAX
650
V
IDM
1.5
ADC
(1)
Continuous Drain Current (Tc=25°C)
ID
0.5
ADC
Continuous Drain Current (Tc=100°C)
ID
0.32
ADC
EAS
10
mJ
VCC,MAX
20
V
Input Voltage Range
VFB
−0.3 to VSTOP
V
Single Pulsed Avalanche Energy
Maximum Supply Voltage
(2)
Total Power Dissipation
PD
-
W
Operating Junction Temperature.
TJ
Internally limited
°C
Operating Ambient Temperature.
TA
-25 to +85
°C
TSTG
-55 to +150
°C
Symbol
Value
Unit
θJA(1)
θJA(1)
θJC(2)
-(3)
°C/W
-(4)
°C/W
Storage Temperature Range.
1. Repetitive rating: Pulse width limited by maximum junction temperature
2. L=24mH, starting Tj=25°C
Thermal Impedance
Parameter
8DIP
Junction-to-Ambient Thermal
Junction-to-Case Thermal
Note:
1. Free standing without heatsink.
2. Measured on the GND pin close to plastic interface.
3. Soldered to 100mm2 copper clad.
4. Soldered to 300mm2 copper clad.
* - all items are tested with the standard JESD 51-10(DIP)
4
°C/W
FSDM101
Electrical Characteristics (Sense FET Part)
(Ta = 25°C unless otherwise specified)
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
VDS=Max. Rating,
VGS=0V
-
-
25
µA
VDS=0.8Max. Rating,
VGS=0V, TC=125°C
-
-
200
µA
RDS(ON)
VGS=10V, ID=0.5A
-
14
19
Ω
gfs
VDS=50V, ID=0.5A
1.0
1.3
-
S
-
162
-
-
18
-
-
3.8
-
-
9.5
-
-
19
-
-
33
-
-
42
-
-
7.0
-
-
3.1
-
-
0.4
-
SENSE FET SECTION
Zero Gate Voltage Drain Current
Static Drain-Source on Resistance
(Note)
Forward Trans conductance (Note)
IDSS
Input Capacitance
CISS
Output Capacitance
COSS
Reverse Transfer Capacitance
CRSS
Turn on Delay Time
td(on)
Rise Time
Turn Off Delay Time
Fall Time
tr
td(off)
tf
Total Gate Charge
(Gate-Source + Gate-Drain)
Qg
Gate-Source Charge
Qgs
Gate-Drain (Miller) Charge
Qgd
VGS=0V, VDS=25V,
f=1MHz
VDD=0.5B VDSS,
ID=1.0A
(MOSFET switching time
is essentially
independent of
operating temperature)
VGS=10V, ID=1.0A,
VDS=0.5B VDSS
(MOSFET switching time
is essentially
independent of operating
temperature)
pF
ns
nC
Note:
1. Pulse test: Pulse width ≤ 300µS, duty ≤ 2%
2.
1S = --R
5
FSDM101
Electrical Characteristics (Control Part) (Continued)
(Ta=25°C unless otherwise specified)
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
UVLO SECTION
Start Threshold Voltage
VSTART
VFB=GND
8
9
10
V
Stop Threshold Voltage
VSTOP
VFB=GND
6
7
8
V
61
67
73
kHz
OSCILLATOR SECTION
Initial Accuracy
FOSC
(2)
-
±5
±10
%
Maximum Duty Cycle
Dmax
59
65
71
%
Minimum Duty Cycle
Dmin
-
-
0
%
0.35
0.40
0.45
mA
Frequency Change With Temperature
∆F/∆T
-25°C ≤ Ta ≤ +85°C
FEEDBACK SECTION
Feedback Source Current
Shutdown Feedback Voltage
Shutdown Delay Current
IFB
Ta=25°C, 0V ≤ Vfb ≤ 3V
4.0
4.5
5.0
V
Ta=25°C, 3V ≤ Vfb ≤ VSD
1.9
2.5
3.1
µA
Ta=25°C
4.20
4.50
4.80
V
-
0.3
0.6
mV/°C
IOVER
0.65
0.75
0.85
A
TSOFT
10
15
20
ms
125
145
-
°C
20
-
-
V
450
550
650
µA
-
1.5
3.0
mA
VSD
IDELAY
REFERENCE SECTION
Output Voltage (1)
Temperature Stability
Vref
(1)(2)
Vref/∆T
-25°C ≤ Ta ≤ +85°C
CURRENT LIMIT(SELF-PROTECTION)SECTION
Peak Current Limit (3)
SOFT START SECTION
Soft Start Time
PROTECTION SECTION
Thermal Shutdown Temperature (1)
Over Voltage Protection
TSD
-
VOVP
TOTAL STANDBY CURRENT SECTION
Start-up Charging Current
ISTR
VCC = 0V, VSTR = 40V
Operating Supply Current
(Control Part Only)
IOP
VCC ≤ 16
Note:
1. These parameters, although guaranteed, are not 100% tested in production
2. These parameters, although guaranteed, are tested in EDS (wafer test) process
3. Test current slope : di/dt = 150 mA/us
6
FSDM101
Comparison Between FSDH0165 and FSDM101
Function
FSDH0165
FSDM101
FSDM101 Advantages
Soft-Start
not applicable
15mS
• Gradually increasing current limit
during soft-start further reduces peak
current and voltage component
stresses
• Eliminates external components used
for soft-start in most applications
• Reduces or eliminates output
overshoot
Drain Creepage at
Package
1.02mm
3.56mm DIP
• Greater immunity to arcing as a result
of build-up of dust, debris and other
contaminants
7
FSDM101
Typical Performance Characteristics
1.15
1.15
1.10
1.10
1.05
1.05
1.00
1.00
Iop
Vref
(These characteristic graphs are normalized at Ta=25°C)
0.95
0.95
0.90
0.90
0.85
-50
0
50
100
0.85
150
-50
0
Temperature('C)
1.15
1.15
1.10
1.10
1.05
1.05
1.00
0.95
0.90
0.90
0
50
100
0.85
150
-50
0
1.15
1.15
1.10
1.10
1.05
1.05
1.00
0.95
0.90
0.90
50
100
Temperature('C)
Frequency vs. Temp
8
150
1.00
0.95
0
100
Stop Threshold Voltage vs. Temp
Dmax
Fosc
Start Threshold Voltage vs. Temp
-50
50
Temperature('C)
Temperature('C)
0.85
150
1.00
0.95
-50
100
Operating Current vs. Temp
Vstop
Vstart
Reference Voltage vs. Temp
0.85
50
Temperature('C)
150
0.85
-50
0
50
100
Temperature('C)
Maximum Duty vs. Temp
150
FSDM101
Typical Performance Characteristics (Continued)
1.15
1.10
1.10
1.05
1.05
1.00
1.00
0.95
0.95
0.90
0.90
0.85
Idelay
Ifb
1.15
-50
0
50
100
0.85
150
50
100
Peak Current Limit vs. Temp
Feedback Source Current vs. Temp
1.15
1.10
1.10
1.05
1.05
1.00
1.00
0.95
0.95
0.90
0.90
-50
0
Temperature('C)
1.15
0.85
-50
Temperature('C)
Vsd
Iover
(These characteristic graphs are normalized at Ta=25°C)
0
50
100
150
0.85
-50
0
50
100
Temperature('C)
Temperature('C)
ShutDown Delay Current vs. Temp
ShutDown Feedback Voltage vs. Temp
150
150
1.15
1.10
Vovp
1.05
1.00
0.95
0.90
0.85
-50
0
50
100
150
Temperature('C)
Over Voltage Protection vs. Temp
9
FSDM101
Functional Description
1. Startup : At startup, the internal high voltage current
source supplies the internal bias and charges the external
Vcc capacitor as shown in Figure 4. In the case of the
FSDM101, when Vcc reaches 9V the device starts switching
and the internal high voltage current source is disabled. The
device continues to switch provided that Vcc does not drop
below 7V. After startup, the bias is supplied from the auxiliary transformer winding.
2. Feedback Control : The FSDM101 products are the voltage mode devices shown in Figure 6. Usually, an opto-coupler and KA431 type voltage reference are used to
implement the feedback network. The feedback voltage is
compared with an internally generated sawtooth waveform.
This directly controls the duty cycle. When the KA431 reference pin voltage exceeds the internal reference voltage of
2.5V, the optocoupler LED current increases, pulling down
the feedback voltage and reducing the duty cycle. This will
happen when the input voltage increases or the output load
decreases.
Vin,dc
Istr
Vstr
Vcc
L
H
9V/
7V
FSDM101
Figure 4. Internal Startup Circuit
Calculating the Vcc capacitor is an important step to designing in the FSDM101. At initial start-up in the FSDM101, the
stand-by maximum current is 100uA, supplying current to
UVLO and Vref Block. The charging current (i) of the Vcc
capacitor is equal to Istr - 100uA. After Vcc reaches the
UVLO start voltage only the bias winding supplies Vcc current to device. When the bias winding voltage is not sufficient, the Vcc level decreases to the UVLO stop voltage. At
this time Vcc oscillates. In order to prevent this ripple, it is
recommended that the Vcc capacitor be sized between 10uF
and 47uF.
3. Leading Edge Blanking (LEB) : When the MOSFET is
turned on, there usually exists a high current spike through
the MOSFET. This is caused by primary side capacitance
and secondary side rectifier reverse recovery. This could
cause premature termination of the switching pulse if it
exceeded the over-current threshold. Therefore, the FPS
employs the leading edge blanking (LEB) circuit. This circuit inhibits the over current comparator for a short time
after the MOSFET is turned on.
Vcc
2.5uA
Vfb
Vo
OSC
Vref
0.40mA
Gate
driver
FB
4
Cfb
R
Vin,dc
Istr
KA431
VSD
Vstr
i = Istr-max current
i = Istr-max current
Vcc
J-FET
Figure 6. PWM and Feedback Circuit
max
current
UVLO
Vref
FSDM101
Vcc
UVLO
start
Vcc must not drop
to UVLO stop
UVLO
stop
Auxiliary winding
voltage
t
Figure 5. Charging the Vcc Capacitor through Vstr
10
OLP
4. Protection Circuit : The FSDM101 has three self protection functions: over-load protection (OLP), thermal shutdown (TSD) and over-voltage protection (OVP). Because
these protection circuits are fully integrated into the IC with
no external components, system reliability is improved without any cost increase. If either of these functions are triggered, the FPS starts an auto-restart cycle. Once the fault
condition occurs, switching is terminated and the MOSFET
remains off. This causes Vcc to fall. When Vcc reaches the
UVLO stop voltage (7V), the protection is reset and the
internal high voltage current source charges the Vcc capacitor. When Vcc reaches the UVLO start voltage (9V), the
device attempts to resume normal operation. If the fault condition is no longer present start up will be successful. If it is,
however, still present, the cycle is repeated. This is shown in
Figure 7.
FSDM101
Vfb
OSC
2.5uA
Vfb
400uA
S
+
-
4
Q
R
GATE
DRIVER
3.8V
R
Cfb
OLP
4.5V
FPS Switching Area
OLP
S
RESET
Vth 4.5V
TSD
R
A/R
Q
FSDM101
OLP, TSD
Protection Block
Idelay (5uA) charges Cfb
IC Reset
Figure 7. Protection Block
4.1 Over Load Protection (OLP) : Overload is a load current that exceeds a pre-set level due to an abnormal situation.
If this occurs, the protection circuit should be triggered to
protect the SMPS. It is possible that a short term load transient can occur under normal operation. If this occurs, the
system should not shut down. In order to avoid false shutdowns, the over load protection circuit is designed to trigger
after a delay. Therefore the device can discriminate between
transient overloads and true fault conditions. The device is
pulse-by-pulse current limited and therefore, for a given
input voltage, the maximum input power is limited. If the
load tries to draw more than this, the output voltage will drop
below its set value. This reduces the opto-coupler LED current, which in turn, will reduce the photo-transistor current.
Therefore, the 400uA current source will charge the feedback pin capacitor, Cfb, and the feedback voltage, Vfb, will
increase. The input to the feedback comparator is clamped at
around 3.8V. Therefore, once Vfb reaches 3.8V, the device is
switching at maximum power. At this point the 400uA current source is blocked and the 2.5uA source continues to
charge Cfb. Once Vfb reaches 4.5V, switching stops. Therefore the shutdown delay time is set by the time required to
charge Cfb from 3.8V to 4.5V with 2.5uA, as shown in Figure 8.
4.2 Thermal Shutdown (TSD) : The Sense FET and the
control IC are assembled in one package. This makes it easy
for the control IC to detect the temperature of the Sense FET.
When the temperature exceeds approximately 145°C, thermal shutdown is activated.
t
t1
t2
t1<<t2, t3
t1 = -1/RC Χ ln( 1-v(t1)/R )
t2 = C Χ [v(t1+t2)-v(t1)] Χ Idelay
t3
v(t1)=3.8V
Figure 8. Over Load Protection Delay
5. Soft Start : The FPS has an internal soft start circuit that
increases the drain current limit together with the MOSFET
current slowly after it starts up. The soft start time is typically 15msec as shown in Figure 9. It progressively
increases during the start-up phase. The pulse width to the
power switching devices is progressively increased to establish the correct working conditions for transformers, inductors, and capacitors. The voltage on the output capacitors is
progressively increased with the intention of smoothly establishing the required output voltage. Consequently it prevents
transformer saturation and stress on the secondary diodes.
Drain current [A]
0.75A
0.49A
0.46A
0.43A
0.40A
0.37A
0.34A
0.31A
2mS
7steps
t
Figure 9. Internal Soft Start
11
FSDM101
Package Dimensions
8DIP
12
FSDM101
Ordering Information
Product Number
Package
Marking Code
Topr (°C)
FSDM101
8DIP
DM101
650V
13
FSDM101
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY
PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY
LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER
DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES
OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR
CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, and (c) whose failure to
perform when properly used in accordance with
instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
6/8/05 0.0m 001
2005 Fairchild Semiconductor Corporation