HCF4089B BINARY RATE MULTIPLIER ■ ■ ■ ■ ■ ■ ■ ■ CASCADABLE IN MULTIPLES OF 4-BITS SET TO "15" INPUT AND "15" DETECT OUTPUT QUIESCENT CURRENT SPECIFIED UP TO 20V STANDARDIZED SYMMETRICAL OUTPUT CHARACTERISTICS 5V, 10V AND 15V PARAMETRIC RATINGS INPUT LEAKAGE CURRENT II = 100nA (MAX) AT VDD = 18V TA = 25°C 100% TESTED FOR QUIESCENT CURRENT MEETS ALL REQUIREMENTS OF JEDEC JESD13B "STANDARD SPECIFICATIONS FOR DESCRIPTION OF B SERIES CMOS DEVICES" DESCRIPTION HCF4089B is a monolithic integrated circuit fabricated in Metal Oxide Semiconductor technology available in DIP and SOP packages. HCF4089B is a low power 4-bit digital rate multiplier that provides an output pulse rate that is the clock input pulse rate multiplied by 1/16 times the binary input. For example, when the binary input number is 13, ther will be 13 output pulses for every 16 input pulses. HCF4089B has an internal synchronous 4-bit counter, which, together with one of the four DIP SOP ORDER CODES PACKAGE TUBE T&R DIP SOP HCF4089BEY HCF4089BM1 HCF4089M013TR binary inputs bits, produces pulse trains as shown in the timing diagram. If more than one binary input bit is high, the resulting pulse train is a combination of the above separate pulse trains. This device may be used to perform arithmetic operations (add, subtract, divide, raise to a power), solve algebrical and differential equations, generate natural logarithms and trigonometric functions, A/D and D/A conversions, and frequency division. PIN CONNECTION September 2002 1/11 HCF4089B IINPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No SYMBOL NAME AND FUNCTION 14, 15, 2, 3 5 6 4 1 Binary Rate Select Inputs Rate Output Rate Output Set Input Output 8 A, B, C, D OUT OUT SET TO "15" "15" OUT INHIBIT OUT (CARRY) CLEAR CASCADE INHIBIT IN (CARRY) STROBE CLOCK VSS 16 VDD 7 13 12 11 10 9 FUNCTIONAL DIAGRAM 2/11 Inhibit Out (Carry) Clear Input Cascade Inhibit Input (Carry) Strobe Clock Input Negative Supply Voltage Positive Supply Voltage HCF4089B TRUTH TABLE INPUTS OUTPUTS Number of Pulses or Input Logic Level Number of Pulses or Output Logic Level D C B A CLOCK INH IN STR. CAS. CLEAR SET OUT OUT INH OUT "15" OUT L L L L L L L L H H H H H H H H X X X H L X L L L L H H H H L L L L H H H H X X X X X X L L H H L L H H L L H H L L H H X X X X X X L H L H L H L H L H L H L H L H X X X X X X 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 L L L L L L L L L L L L L L L L H L L L L L L L L L L L L L L L L L L L L L L H L L L L L L L L L L L L L L L L L L L L L L H L L L L L L L L L L L L L L L L L L L L L L H H L L L L L L L L L L L L L L L L L L L L L L H L 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 • L H 16 L L H 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 • H * 16 H H 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 H 1 1 H H L 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 • 1 1 L L H X : Don’t Care • : Depends on internal state of counter *: Output same as the first 16 lines of this truth table (depending on values of A, B, C, D) LOGIC DIAGRAM 3/11 HCF4089B TIMING CHART ABSOLUTE MAXIMUM RATINGS Symbol VDD Parameter Supply Voltage Value Unit -0.5 to +22 V VI DC Input Voltage -0.5 to VDD + 0.5 V II DC Input Current ± 10 mA 200 100 mW mW Top Power Dissipation per Package Power Dissipation per Output Transistor Operating Temperature -55 to +125 °C Tstg Storage Temperature -65 to +150 °C PD Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. All voltage values are referred to VSS pin voltage. RECOMMENDED OPERATING CONDITIONS Symbol VDD 4/11 Parameter Supply Voltage VI Input Voltage Top Operating Temperature Value Unit 3 to 20 V 0 to VDD V -55 to 125 °C HCF4089B DC SPECIFICATIONS Test Condition Symbol IL VOH VOL VIH VIL IOH IOL II CI Parameter Quiescent Current High Level Output Voltage Low Level Output Voltage VI (V) Low Level Input Voltage Output Sink Current Input Leakage Current Input Capacitance |IO| VDD (µA) (V) 0/5 0/10 0/15 0/20 0/5 0/10 0/15 5/0 10/0 15/0 High Level Input Voltage Output Drive Current VO (V) 0/5 0/5 0/10 0/15 0/5 0/10 0/15 0/18 Value 0.5/4.5 1/9 1.5/13.5 4.5/0.5 9/1 13.5/1.5 2.5 4.6 9.5 13.5 0.4 0.5 1.5 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 Any Input Any Input 5 10 15 20 5 10 15 5 10 15 5 10 15 5 10 15 5 5 10 15 5 10 15 18 TA = 25°C Min. Typ. Max. 0.04 0.04 0.04 0.08 5 10 20 100 4.95 9.95 14.95 -40 to 85°C -55 to 125°C Min. Min. 150 300 600 3000 4.95 9.95 14.95 0.05 0.05 0.05 4.95 9.95 14.95 3.5 7 11 1.5 3 4 -3.2 -1 -2.6 -6.8 1 2.6 6.8 ±0.1 5 7.5 0.05 0.05 0.05 1.5 3 4 V V 1.5 3 4 -1.1 -0.36 -0.9 -2.4 0.36 0.9 2.4 ±1 µA V 3.5 7 11 -1.1 -0.36 -0.9 -2.4 0.36 0.9 2.4 ±10-5 Max. 150 300 600 3000 0.05 0.05 0.05 3.5 7 11 -1.36 -0.44 -1.1 -3.0 0.44 1.1 3.0 Max. Unit V mA mA ±1 µA pF The Noise Margin for both "1" and "0" level is: 1V min. with VDD =5V, 2V min. with VDD=10V, 2.5V min. with VDD=15V DYNAMIC ELECTRICAL CHARACTERISTICS (Tamb = 25°C, CL = 50pF, RL = 200KΩ, tr = tf = 20 ns) Test Condition Symbol Parameter tPHL tPLH Propagation Delay Time CLOCK to OUT tPHL tPLH Propagation Delay Time CLOCK or STROBE to OUT tPHL tPLH Propagation Delay Time CLOCK to INHIBIT High Level to Low Level tPHL tPLH Propagation Delay Time LOW Level to HIGH Level VDD (V) 5 10 15 5 10 15 5 10 15 5 10 15 Value (*) Min. Unit Typ. Max. 110 55 45 150 75 60 360 160 110 250 100 75 220 110 90 300 150 120 720 320 220 500 200 150 ns ns ns ns 5/11 HCF4089B Test Condition Symbol Parameter tPHL tPLH Propagation Delay Time CLEAR to OUT tPHL tPLH Propagation Delay Time CLOCK to "9" or "15" OUT tPHL tPLH Propagation Delay Time CASCADE to OUT tPHL tPLH Propagation Delay Time INHIBIT IN to INHIBIT OUT tPHL tPLH Propagation Delay Time SET to OUT tTHL tTLH Transition Time fCL tW tr, tf tW tsetup tR tR tR Maximum Clock Frequency Clock Pulse Width Clock Rise or Fall Time SET or CLEAR pulse Width INHIBIT Input Set-Up Time, High Level to Low Level INHIBIT Input Removal Time Minimum SET Removal Time CLEAR Removal Time VDD (V) 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 (*) Typical temperature coefficient for all VDD value is 0.3 %/°C. 6/11 Value (*) Unit Min. Typ. Max. 760 350 260 600 250 180 180 90 70 320 150 110 660 300 220 200 100 80 1.2 2.5 3.5 330 170 100 380 175 130 300 125 90 90 45 35 160 75 55 330 150 110 100 50 40 2.4 5 7 165 85 50 80 45 30 50 20 10 120 65 55 75 40 25 30 20 15 ns ns ns ns ns MHz ns 15 15 15 160 90 60 100 40 20 240 130 110 150 80 50 60 40 30 ns µs ns ns ns ns ns HCF4089B APPLICATION NOTES For words of more than 4 bits, HCF4089B device may be cascaded in two different modes : an ADD mode and a MULTIPLY mode. TWO HCF4089B’S CASCADED IN THE "ADD" MODE WITH A PRESET NUMBER OF 189 In the ADD mode some of the gaps left by the more significant unit at the count of 15 are filled in by the less significant units. For example, when two units are cascaded in the ADD mode and programmed to 11 and 13, respectively, the more significant unit will have 11 output pulses and the other unit will have 13 output pulses for every 256 input pulses for a total of : 11 13 189 + = 16 256 256 TWO HCF4089B’S CASCADED IN THE "MULTIPLY" MODE FOR MULTIPLICATION OF TWO VARIABLES A AND B WITH LOOP CIRCUIT CONTROL A B 1 N When the loop stabilities rate R2 = rate R3, thus fclock( • ) = fclock ( • ) therefore N = AB 16 16 16 16 7/11 HCF4089B TEST CIRCUIT CL = 50pF or equivalent (includes jig and probe capacitance) RL = 200KΩ RT = ZOUT of pulse generator (typically 50Ω) 8/11 HCF4089B Plastic DIP-16 (0.25) MECHANICAL DATA mm. inch DIM. MIN. a1 0.51 B 0.77 TYP MAX. MIN. TYP. MAX. 0.020 1.65 0.030 0.065 b 0.5 0.020 b1 0.25 0.010 D 20 0.787 E 8.5 0.335 e 2.54 0.100 e3 17.78 0.700 F 7.1 0.280 I 5.1 0.201 L Z 3.3 0.130 1.27 0.050 P001C 9/11 HCF4089B SO-16 MECHANICAL DATA DIM. mm. MIN. TYP A a1 inch MAX. MIN. TYP. 1.75 0.1 0.068 0.2 a2 MAX. 0.003 0.007 1.65 0.064 b 0.35 0.46 0.013 0.018 b1 0.19 0.25 0.007 0.010 C 0.5 0.019 c1 45˚ (typ.) D 9.8 E 5.8 10 0.385 6.2 0.228 0.393 0.244 e 1.27 0.050 e3 8.89 0.350 F 3.8 4.0 0.149 0.157 G 4.6 5.3 0.181 0.208 L 0.5 1.27 0.019 0.050 M S 0.62 0.024 8 ˚ (max.) PO13H 10/11 HCF4089B Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. © The ST logo is a registered trademark of STMicroelectronics © 2002 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. © http://www.st.com 11/11