AGILENT HDMP

Gigabit Ethernet and
Fibre Channel SerDes ICs
Technical Data
HDMP-1636A Transceiver
HDMP-1646A Transceiver
HDMP-T1636A Transceiver
Features
Description
• IEEE 802.3z Gigabit Ethernet
Compatible
• ANSI x3.230-1994 Fibre
Channel Compatible (FC-O)
• Supports Serial Data Rates of
1062.5 MBd (Fibre Channel)
& 1250 MBd (Gigabit
Ethernet)
• Low Power Consumption,
630 mW Typical
• Transmitter and Receiver
Functions Incorporated onto
a Single IC
• Three Package Sizes
Available:
– 10 mm TQFP (HDMP-T1636A)
– 10 mm PQFP (HDMP-1636A)
– 14 mm PQFP (HDMP-1646A)
• 10-Bit Wide Parallel TTL
Compatible I/Os
• Single +3.3 V Power Supply
• 5-Volt Tolerant I/Os
• 2 kV ESD Protection on All
Pins
The HDMP-1636A/46A/T1636A
transceiver is a single integrated
circuit packaged in a plastic QFP
package. It provides a low-cost,
low-power physical layer solution
for 1250 MBd Gigabit Ethernet,
1062.5 MBd Fibre Channel, and
proprietary link interfaces. It
provides complete Serialize/
Deserialize (SerDes) for copper
transmission, incorporating the
Gigabit Ethernet/Fibre Channel
transmit and receive functions
into a single device.
Applications
• 1250 MBd Gigabit Ethernet
Interface
• 1062.5 MBd Fibre Channel
Interface
• Mass Storage System I/O
Channel
• Work Station/Server I/O
Channel
• Backplane Serialization
• FC Interface for Disk Drives
and Arrays
This chip is used to build a high
speed interface (as shown in
Figure 1) while minimizing board
space, power and cost. It is
compatible with the IEEE 802.3z
specification.
The transmitter section accepts
10-bit wide parallel TTL data and
serializes this data into a high
speed serial data stream. The
parallel data is expected to be
“8B/10B” encoded data, or equivalent. This parallel data is latched
into the input register of the
transmitter section on the rising
edge of the reference clock (used
as the transmit byte clock). A
1062.5 MHz reference clock is
used in Fibre Channel operation,
whereas a 125 MHz reference
clock is used in Gigabit Ethernet
operation.
The transmitter section’s PLL
locks to the user supplied
reference byte clock. This clock
is then multiplied by 10 to generate the high speed serial clock
used to generate the high speed
output. The high speed outputs
are capable of interfacing directly
to copper cables for electrical
transmission or to a separate
fiber optic module for optical
transmission.
The receiver section accepts a
serial electrical data stream at
1062.5 MBd or 1250 MBd and
recovers the original 10-bit wide
parallel data. The receiver PLL
locks onto the incoming serial
signal and recovers the high
speed serial clock and data. The
serial data is converted back into
10-bit parallel data, recognizing
the 8B/10B comma character to
establish byte alignment.
CAUTION: As with all semiconductor ICs, it is advised that normal static precautions be taken in handling and assembly
of this component to prevent damage and/or degradation which may be induced by electrostatic discharge (ESD).
2
HDMP-16x6A
TRANSMITTER SECTION
SERIAL DATA OUT
PLL
PROTOCOL DEVICE
RBC0
RBC1
PLL
SERIAL DATA IN
RECEIVER SECTION
BYTSYNC
REFCLK
ENBYTSYNC
DATA BYTE
TX[0-9]
INPUT
LATCH
Figure 1. Typical Application Using the HDMP-1636A/1646A/T1636A.
FRAME
MUX
OUTPUT
SELECT
INTERNAL
LOOPBACK
TXCAP0
TXCAP1
TX
PLL/CLOCK
GENERATOR
INTERNAL
TX CLOCKS
± DOUT
LOOPEN
INPUT
SELECT
± DIN
SIGNAL
DETECT
SIG_DET
REFCLK
RX
PLL/CLOCK
RECOVERY
DATA BYTE
RX[0-9]
OUTPUT
DRIVER
RXCAP0
RXCAP1
RBC0
RBC1
FRAME
DEMUX
AND
BYTE SYNC
BYTSYNC
INTERNAL
RX CLOCKS
INPUT
SAMPLER
ENBYTSYNC
Figure 2. HDMP-1636A/1646A/T1636A Transceiver Block Diagram.
3
The recovered parallel data is
presented to the user at TTL
compatible outputs. The receiver
section also recovers two receiver
byte clocks which are 180
degrees out of phase with each
other. For Gigabit Ethernet,
these clocks are 62.5 MHz,
whereas for Fibre Channel, they
are 53.125 MHz. The parallel
data is properly aligned with the
rising edge of alternating clocks.
For test purposes, the transceiver
provides for on-chip local loopback functionality, controlled
through an external input pin.
Additionally, the byte
synchronization feature may be
disabled. This may be useful in
proprietary applications which
use alternative methods to align
the parallel data.
HDMP-1636A/1646A/
T1636A Block Diagram
The HDMP-1636A/1646A/
T1636A was designed to transmit
and receive 10-bit wide parallel
data over a single high-speed
line. The parallel data applied to
the transmitter is expected to be
8B/10B encoded. In order to
accomplish this task, the HDMP1636A/1646A/T1636A
incorporates the following:
• TTL Parallel I/Os
• High Speed Phase Locked
Loops
• Parallel to Serial Converter
• High Speed Serial Clock and
Data Recovery Circuitry
• Comma Character Recognition
Circuitry as per 8B/10B
Specifications
• Byte Alignment Circuitry
• Serial to Parallel Converter
INPUT LATCH
The transmitter accepts 10-bit
wide TTL parallel data at inputs
TX[0..9]. The user-provided
reference clock signal, REFCLK,
is also used as the transmit byte
clock. The TX[0..9] and REFCLK
signals must be properly aligned,
as shown in Figure 3.
TX PLL/CLOCK GENERATOR
The transmitter Phase Locked
Loop and Clock Generator (TX
PLL/CLOCK GENERATOR) block
is responsible for generating all
internal clocks needed by the
transmitter section to perform its
functions. These clocks are based
on the supplied reference byte
clock (REFCLK). REFCLK is
used as both the frequency
reference clock for the PLL and
the transmit byte clock for the
incoming data latches. It is
expected to be properly aligned
to the incoming parallel data (see
Figure 3). This clock is then
multiplied by 10 to generate the
high speed clock necessary for
clocking the high speed serial
outputs.
FRAME MUX
The FRAME MUX accepts the 10bit wide parallel data from the
INPUT LATCH. Using internally
generated high speed clocks, this
parallel data is multiplexed into
the high speed serial data stream.
The data bits are transmitted
sequentially, from the least
significant bit (TX[0]) to the
most significant bit (TX[9]).
OUTPUT SELECT
The OUTPUT SELECT block
provides for an optional internal
loopback of the high speed serial
signal for testing purposes.
In normal operation, LOOPEN is
set low and the serial data stream
is placed at +/- DOUT. When
wrap-mode is activated by setting
LOOPEN high, the +/- DOUT
pins are held static at logic 1 and
the serial output signal is
internally wrapped to the INPUT
SELECT box of the receiver
section.
INPUT SELECT
The INPUT SELECT block
determines whether the signal at
+/- DIN or the internal loop-back
serial signal is used. In normal
operation, LOOPEN is set low
and the serial data is accepted at
+/- DIN. When LOOPEN is set
high, the high speed serial signal
is internally looped-back from the
transmitter section to the
receiver section. This feature
allows for loop back testing
exclusive of the transmission
medium.
RX PLL/CLOCK RECOVERY
The RX PLL/CLOCK RECOVERY
block is responsible for frequency
and phase locking onto the
incoming serial data stream and
recovering the bit and byte
clocks. An automatic locking
feature allows the Rx PLL to lock
onto the input data stream
without external PLL training
controls. It does this by
continually frequency locking
onto the reference clock, and
then phase locking onto the input
data stream. An internal signal
detection circuit monitors the
presence of the input, and
invokes the phase detection as
the data stream appears. Once bit
locked, the receiver generates the
high speed sampling clock for the
input sampler, and recovers the
4
two receiver byte clocks
(RBC1/RBC0). These clocks are
180 degrees out of phase with
each other, and are alternately
used to clock out the 10-bit
parallel output data.
INPUT SAMPLER
The INPUT SAMPLER is responsible for converting the serial
input signal into a retimed serial
bit stream. In order to accomplish this, it uses the high speed
serial clock recovered from the
RX PLL/CLOCK RECOVERY
block. This serial bit stream is
sent to the FRAME DEMUX and
BYTE SYNC block.
FRAME DEMUX AND BYTE
SYNC
The FRAME DEMUX AND BYTE
SYNC block is responsible for
restoring the 10-bit parallel data
from the high speed serial bit
stream. This block is also
responsible for recognizing the
comma character (or a K28.5
character) of positive disparity
(0011111xxx). When recognized,
the FRAME DEMUX AND BYTE
SYNC block works with the RX
PLL/CLOCK RECOVERY block to
properly align the receive byte
clocks to the parallel data. When
a comma character is detected
and realignment of the receiver
byte clocks (RBC1/RBC0) is
necessary, these clocks are
stretched, not slivered, to the
next possible correct alignment
position. These clocks will be
fully aligned by the start of the
second 2-byte ordered set. The
second comma character
received shall be aligned with the
rising edge of RBC1. As per the
8B/10B encoding scheme,
comma characters must not be
transmitted in consecutive bytes
to allow the receiver byte clocks
to maintain their proper
recovered frequencies.
OUTPUT DRIVERS
The OUTPUT DRIVERS present
the 10-bit parallel recovered data
byte properly aligned to the
receive byte clocks (RBC1/RBC0),
as shown in Figure 5. These
output data buffers provide TTL
compatible signals.
SIGNAL DETECT
The SIGNAL DETECT block
examines the differential
amplitude of the inputs ± DIN.
When this input signal is too
small, it outputs a logic 0 at
SIG_DET (refer to SIG_DET pin
definition for detection
thresholds), and at the same
time, forces the parallel output
RX[0]..RX[9] to all logic one
(1111111111). The main
purpose of this circuit is to
prevent the generation of random
data when the serial input lines
are disconnected. When the
signal at ± DIN is of a valid
amplitude, SIG_DET is set to
logic 1, and the output of the
INPUT SELECT block is passed
through.
HDMP-1636A/1646A/T1636A (Transmitter Section) – Gigabit Ethernet
Timing Characteristics
TA = 0°C to +70°C, VCC = 3.15 V to 3.45 V
Symbol
Parameter
tsetup
Setup Time
thold
Hold Time
t_txlat[1]
Transmitter Latency
Units
nsec
nsec
nsec
bits
Min.
1.5
1.0
Typ.
Max.
3.5
4.4
Note:
1. The transmitter latency, as shown in Figure 4, is defined as the time between the latching in of the parallel data word (as triggered
by the rising edge of the transmit byte clock, REFCLK) and the transmission of the first serial bit of that parallel word (defined by
the rising edge of the first bit transmitted).
5
HDMP-1636/1646A/T1636A (Transmitter Section) – Fibre Channel
Timing Characteristics
TA[1] = 0°C to +70°C, VCC = 3.15 V to 3.45 V
Symbol
Parameter
tsetup
Setup Time
thold
Hold Time
t_txlat[2]
Transmitter Latency
Units
nsec
nsec
nsec
bits
Min.
2
1.5
Typ.
Max.
4.2
4.4
Notes:
1. Device tested and characterized under TA conditions specified, with TC monitored at approximately 20° higher than TA.
2. The transmitter latency, as shown in Figure 4, is defined as the time between the latching in of the parallel data word (as triggered
by the rising edge of the transmit byte clock, REFCLK) and the transmission of the first serial bit of that parallel word (defined by
the rising edge of the first bit transmitted).
1.4 V
REFCLK
2.0 V
TX[0]-TX[9]
DATA
DATA
DATA
DATA
DATA
0.8 V
tSETUP
tHOLD
Figure 3. Transmitter Section Timing.
DATA BYTE A
± DOUT
T5
T6
T7
T8
T9
T0
T1
T2
T3
T4
T5
DATA BYTE B
T6
T7
T8
T9
T0
T1
T2
T3
T4
T5
t_TXLAT
TX[0]-TX[9]
REFCLK
Figure 4. Transmitter Latency.
DATA BYTE B
DATA BYTE C
1.4 V
6
HDMP-1636A/1646A/T1636A (Receiver Section) – Gigabit Ethernet
Timing Characteristics
TA = 0°C to +70°C, VCC = 3.15 V to 3.45 V
Symbol
Parameter
b_sync[1,2]
Bit Sync Time
f_lock
Frequency Lock at Powerup
tvalid_before
Time Data Valid Before Rising Edge of RBC
tvalid_after
Time Data Valid After Rising Edge of RBC
tduty
RBC Duty Cycle
[3]
tA-B
Rising Edge Time Difference between
RBC0 and RBC1
[4]
t_rxlat
Receiver Latency
Units
bits
µs
nsec
nsec
%
nsec
Min.
Typ.
2.5
1.5
40
7.5
nsec
bits
Max.
2500
500
60
8.5
22.4
28.0
Notes:
1. This is the recovery time for input phase jumps, per the Fibre Channel Specification X3.230-1994 FC-PH Standard, Sec 5.3.
2. Tested using C PLL = 0.1 µF.
3. Garranteed at room temperature.
4. The receiver latency, as shown in Figure 6, is defined as the time between receiving the first serial bit of a parallel data word
(defined as the first edge of the first serial bit) and the clocking out of that parallel word (defined by the rising edge of the receive
byte clock, either RBC1 or RBC0).
HDMP-1636/1646A/T1636A (Receiver Section) – Fibre Channel
Timing Characteristics
TA[1] = 0°C to +70°C, VCC = 3.15 V to 3.45 V
Symbol
Parameter
[2,3]
b_sync
Bit Sync Time
tvalid_before
Time Data Valid Before Rising Edge of RBC
tvalid_after
Time Data Valid After Rising Edge of RBC
tduty
RBC Duty Cycle
[4]
tA-B
Rising Edge Time Difference between
RBC0 and RBC1.
t_rxlat[5]
Receiver Latency
Units
bits
nsec
nsec
%
nsec
nsec
bits
Min.
3
1.5
40
8.9
Typ.
9.4
Max.
2500
60
9.9
24.5
26
Notes:
1. Device tested and characterized under TA conditions specified, with TC monitored at approximately 20° higher than TA.
2. This is the recovery time for input phase jumps, per the FC-PH specification Ref 4.1, Sec 5.3.
3. Tested using C PLL = 0.1 µF.
4. The RBC clock skew is calculated as t A-B(max) - tA-B(min).
5. The receiver latency, as shown in Figure 6, is defined as the time between receiving the first serial bit of a parallel data word
(defined as the first edge of the first serial bit) and the clocking out of that parallel word (defined by the rising edge of the receive
byte clock, either RBC1 or RBC0).
7
tvalid_before
tvalid_after
RBC1
1.4 V
2.0 V
RX[0]-RX[9]
K28.5
DATA
DATA
DATA
DATA
0.8 V
2.0 V
BYTSYNC
0.8 V
1.4 V
RBC0
tA-B
Figure 5. Receiver Section Timing.
DATA BYTE C
± DIN
R5
R6
R7
R8
DATA BYTE D
R9
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R2
R3
R4
R5
t_rxlat
RX[0]-RX[9]
RBC1/0
Figure 6. Receiver Latency.
DATA BYTE A
DATA BYTE D
1.4 V
8
HDMP-1636A/1646A/T1636A (TRx)
Absolute Maximum Ratings
TA = 25°C, except as specified. Operation in excess of any one of these conditions may result in permanent
damage to this device.
Symbol
VCC
VIN,TTL
VIN,HS_IN
IO,TTL
Tstg
Tj
Parameter
Supply Voltage
TTL Input Voltage
HS_IN Input Voltage
TTL Output Source Current
Storage Temperature
Junction Operating Temperature
Units
V
V
V
mA
°C
°C
Min.
-0.5
-0.7
2.0
-65
0
Max.
5.0
VCC + 2.8
VCC
13
+150
+150
HDMP-1636A/1646A/T1636A (TRx)
Guaranteed Operating Rates – Gigabit Ethernet
TA = 0°C to +70°C, VCC = 3.15 V to 3.45 V
Parallel Clock Rate (MHz)
Serial Baud Rate (MBaud)
Min.
Max.
Min.
Max.
124.0
126.0
1240
1260
Guaranteed Operating Rates – Fibre Channel
TA = 0°C to +70°C, VCC = 3.15 V to 3.45 V
Parallel Clock Rate (MHz)
Serial Baud Rate (MBaud)
Min.
Max.
Min.
Max.
106.20
106.30
1062.0
1063.0
HDMP-1636A/1646A/T1636A (TRx)
Transceiver Reference Clock Requirements
TA = 0°C to +70°C, VCC = 3.15 V to 3.45 V
Symbol
Parameter
f
Nominal Frequency (for Gigabit Ethernet Compliance)
f
Nominal Frequency (for Fibre Channel Compliance)
Ftol
Frequency Tolerance
Symm
Symmetry (Duty Cycle)
Unit
MHz
MHz
ppm
%
Min.
-100
40
Typ.
125
106.25
Max.
+100
60
9
HDMP-1636A/1646A/T1636A (TRx)
DC Electrical Specifications
TA= 0°C to +70°C, VCC = 3.15 V to 3.45 V
Symbol
Parameter
VIH,TTL
TTL Input High Voltage Level, Guaranteed High Signal
for All Inputs
VIL,TTL
TTL Input Low Voltage Level, Guaranteed Low Signal for
All Inputs
VOH,TTL
TTL Output High Voltage Level, IOH = -400 µA
VOL,TTL
TTL Output Low Voltage Level, IOL = 1 mA
IIH,TTL
Input High Current, VIN = 2.4 V, VCC = 3.45 V
IIL,TTL
Input Low Current, VIN = 0.4 V, VCC = 3.45 V
[1,2]
ICC,TRx
Transceiver VCC Supply Current, TA = 25°C
Unit
V
Min.
2
Typ.
Max.
VCC
V
0
0.8
V
V
µA
µA
mA
2.2
0
VCC
0.6
40
-600
220
Notes:
1. Measurement Conditions: Tested sending 1250 MBd PRBS 27-1 sequence from a serial BERT with ± DOUT outputs biased with
150 Ω resistors.
2. Typical specified with VCC = 3.3 volts.
10
HDMP-1636A/1646A/T1636A (TRx)
AC Electrical Specifications
TA = 0°C to +70°C,
Symbol
tr,REFCLK
tf,REFCLK
t,TTLin
tf,TTLin
tr,TTLout
tf,TTLout
trs,HS_OUT
tfs,HS_OUT
trd,HS_OUT
tfd,HS_OUT
VIP,HS_IN
VOP,HS_OUT[1]
VCC = 3.15 V to 3.45 V
Parameter
REFCLK Rise Time, 0.8 to 2.0 Volts
REFCLK Fall Time, 2.0 to 0.8 Volts
Input TTL Rise Time, 0.8 to 2.0 Volts
Input TTL Fall Time, 2.0 to 0.8 Volts
Output TTL Rise Time, 0.8 to 2.0 Volts, 10 pF Load
Output TTL Fall Time, 2.0 to 0.8 Volts, 10 pF Load
HS_OUT Single-Ended (+DOUT) Rise Time
HS_OUT Single-Ended (+DOUT) Fall Time
HS_OUT Differential Rise Time
HS_OUT Differential Fall Time
HS_IN Input Peak-to-Peak Differential Voltage
HS_OUT Output Peak-to-Peak Differential Voltage
Units
nsec
nsec
nsec
nsec
nsec
nsec
psec
psec
psec
psec
mV
mV
Note:
1. Output Peak-to-Peak Differential Voltage specified as DOUT+ minus DOUT-.
22.0680 ns
Yaxis = 400 mV/DIV
a. Differential HS_OUT Output (Dout+ Minus Dout-).
22.0680 ns
Yaxis = 200 mV/DIV
b. Single-Ended HS_OUT Output (Dout+).
Eye Diagrams of the High-Speed Serial Outputs from the HDMP-1636A/1646A/T1636A
as Captured on the 83480A Digital Communications Analyzer. Tested with PRBS = 27 -1.
Figure 7. Transmitter DOUT Eye Diagrams.
Min.
85
85
85
85
200
1200
Typ.
2
2
1.5
1.1
225
200
1200
1600
Max.
2.4
2.4
2.4
2.4
327
327
327
327
2000
2200
11
HDMP-1636A/1646A/T1636A (Transmitter Section)
Output Jitter Characteristics
TA = 0°C to +70°C, VCC = 3.15 V to 3.45 V
Symbol
Parameter
[1]
RJ
Random Jitter at DOUT, the High Speed Electrical Data Port, specified as
one sigma deviation of the 50% crossing point (RMS)
DJ[1]
Deterministic Jitter at DOUT, the High Speed Electrical Data Port (pk-pk)
Units
ps
Typ.
8
ps
15
Note: 1. Defined by Fibre Channel Specification X3.230-1994 FC-PH Standard, Annex A, Section A.4 and tested using measurement
method shown in Figure 8.
70841B
PATTERN
GENERATOR
70311A
CLOCK SOURCE
+K28.5, -K28.5
70841B
PATTERN
GENERATOR*
83480A
OSCILLOSCOPE
0000011111
+ DATA
- DATA
125 MHz
1.25 GHz
83480A
OSCILLOSCOPE
TRIGGER
CH1
CH2
+DOUT
-DOUT
70311A
CLOCK SOURCE
BIAS
TEE
+ DATA
- DATA
1.25 GHz
DIVIDE
BY 10
CIRCUIT
(DUAL
OUTPUT)
DIVIDE
BY 2
CIRCUIT
CH1
HDMP-1636A
REFCLK LOOPEN
TRIGGER
+DOUT
VARIABLE
DELAY
TTL
125 MHz
REFCLK
Tx[0..9]
1.4 V
-DOUT
-DIN
+DIN
HDMP-1636A
Tx[0..9]
* PATTERN
GENERATOR
PROVIDES A
DIVIDE BY
10 FUNCTION.
CH2
ENBYTSYNC
LOOPEN
Rx[0..9]
0011111000
(STATIC K28.7)
a. Block Diagram of RJ Measurement Method.
b. Block Diagram of DJ Measurement Method.
Figure 8. Transmitter Jitter Measurement Method.
HDMP-1636A/1646A/T1636A
Package Thermal Characteristics
TA = 0°C to +70°C, VCC = 3.15 V to 3.45 V
Symbol
Parameter
PDmax
Power Dissipationa
θJA[1]
Thermal Resistance: Junction to Ambient in still air
HDMP-1646A
HDMP-1636A
HDMP-T1636A
[2]
ψJT
Thermal Characterization parameter: Junction to package top
HDMP-1646A
HDMP-1636A
HDMP-T1636A
Units
mW
°C/W
Typ.
675
Max.
900
36.3
45.0
40.0
°C/W
9.6
7.8
6.2
Notes:
Based on independent testing done by Agilent.
1. θJA is based on thermal measurement in a still air environment at 23°C on a standard 3 x 3” FR4 PCB as specified in EIA/JESD 51-7.
2. ψJT is used to determine the actual junction temperature in a given application, using the following equation:
TJ = ψJT x PD + T T where TT is the measured temperature on top center of the package and P D is the power being dissipated.
12
I/O Type Definitions
I/O Type
I-TTL
O-TTL
HS_OUT
HS_IN
C
S
Definition
Input TTL, Floats High When Left Open
Output TTL
High Speed Output, ECL Compatible
High Speed Input
External Circuit Node
Power Supply or Ground
HDMP-1636A/46A/T1636A (TRx)
Pin Input Capacitance
Symbol
C INPUT
Parameter
Input Capacitance on TTL Input Pins
Units
pF
O_TTL
Typ.
1.6
Max.
I_TTL
VCC_RXTTL
R
VCC
R
VCC
R
R
R
VBB 1.4 V
GND
GND_RXTTL
ESD
PROTECTION
ESD
PROTECTION
GND
Figure 9. O-TTL and I-TTL Simplified Circuit Schematic.
HS_OUT
HS_IN
VCC
VCC_TXHS
VCC_TXECL
+
–
VCC
VCC
+
–
R
R
0.01 µF
+DOUT
Zo
+DIN
RPAD
150
-DOUT
2 Zo
RPAD
Zo
0.01 µF
GND
ESD
PROTECTION
-DIN
GND
ESD
150
PROTECTION
GND_TXHS
GND
Figure 10. HS_OUT and HS_IN Simplified Circuit Schematic.
Notes:
1. HS_IN inputs should never be connected to ground as permanent damage to the device may result.
2. The optional series padding resistors (R PAD) help dampen load reflections. Typical RPAD values for mismatched loads range
between 25-Zo Ω.
VCC_RXA
RXCAP1
-DIN
GND_RXA
*VCC
*VCC
+DIN
*GND
GND
VCC
GND_TXHS
VCC_TXHS
+DOUT
-DOUT
VCC_TXECL
VCC
13
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
*GND
1
48
TX[0]
TX[1]
2
47
RXCAP0
BYTSYNC
46
GND_RXTTL
TX[2]
45
44
43
RX[0]
*VCC
TX[3]
4
5
6
TX[4]
TX[5]
TX[6]
7
8
9
42
41
40
*VCC
TX[8]
10
11
12
VCC_RXTTL
RX[3]
RX[4]
RX[5]
RX[6]
TX[9]
*GND
GND_TXA
TXCAP1
13
14
15
16
TX[7]
3
Agilent
HDMP-16x6A/T1636A
xxxx-x Rz.zz
S
YYWW
39
38
37
36
35
34
33
RX[1]
RX[2]
VCC_RXTTL
RX[7]
RX[8]
RX[9]
GND_RXTTL
RBC0
GND_RXTTL
VCC
VCC_RXTTL
RBC1
SIG_DET
*N/C
VCC
ENBYTSYNC
GND
TXCAP0
VCC_TXA
LOOPEN
VCC
GND
REFCLK
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
xxxx-x = WAFER CODE
Rzz.zz = DIE REVISION
S = SUPPLIER CODE
YYWW = DATE CODE (YY = YEAR, WW = WORK WEEK)
COUNTRY = COUNTRY OF MANUFACTURE
(MARKED ON BACK OF DEVICE)
*N/C: THIS PIN IS CONNECTED TO AN ISOLATED PAD AND HAS NO FUNCTIONALITY.
IT CAN BE LEFT OPEN, HOWEVER, TTL LEVELS CAN ALSO BE APPLIED TO THIS PIN.
*VCC: THIS PIN IS BONDED TO AN ISOLATED PAD AND HAS NO FUNCTIONALITY.
HOWEVER, IT IS RECOMMENDED THAT THIS PIN BE CONNECTED TO VCC IN ORDER
TO CONFORM WITH THE X3T11 "10-BIT SPECIFICATION," AND TO HELP DISSIPATE HEAT.
*GND: THIS PIN IS BONDED TO AN ISOLATED PAD AND HAS NO FUNCTIONALITY.
HOWEVER, IT IS RECOMMENDED THAT THIS PIN BE CONNECTED TO GND IN ORDER TO
CONFORM WITH THE X3T11 "10-BIT SPECIFICATION," AND TO HELP DISSIPATE HEAT.
Figure 11. HDMP-1636A/1646A/T1636A (TRx) Package Layout and Marking, Top View.
14
TRx I/O Definition
Name
BYTSYNC
Pin
47
-DIN
+DIN
-DOUT
+DOUT
52
54
61
62
ENBYTSYNC
24
GND
21
25
58
1
14
56
51
*GND
GND_RXA
GND_RXTTL
Type
O-TTL
Signal
Byte Sync Output: An active high output. Used to indicate detection of
a comma character (0011111XXX). It is only active when
ENBYTSYNC is enabled.
HS_IN Serial Data Inputs: High-speed inputs. Serial data is accepted from the
± DIN inputs when LOOPEN is low.
HS_OUT Serial Data Outputs: High-speed outputs. These lines are active when
LOOPEN is set low. When LOOPEN is set high, these outputs are held
static at logic 1.
I-TTL Enable Byte Sync Input: When high, turns on the internal byte sync
function to allow clock synchronization to a comma character,
(0011111XXX). When the line is low, the function is disabled and will
not reset registers and clocks, or strobe the BYTSYNC line.
S
Logic Ground: Normally 0 volts. This ground is used for internal PECL
logic. It should be isolated from the noisy TTL ground as well as possible.
S
S
GND_TXA
32
33
46
15
GND_TXHS
LOOPEN
64
19
S
I-TTL
N/C
27
RBC1
RBC0
30
31
O-TTL
REFCLK
22
I-TTL
S
This pin is bonded to an isolated pad and has no functionality. However,
it is recommended that this pin be connected to GND in order to conform
with the X3T11 “10-bit specification,” and to help dissipate heat.
Analog Ground: Normally 0 volts. Used to provide a clean ground
plane for the receiver PLL and high-speed analog cells.
TTL Receiver Ground: Normally 0 volts. Used for the TTL output cells
of the receiver section.
Analog Ground: Normally 0 volts. Used to provide a clean ground plane
for the PLL and high-speed analog cells.
Ground: Normally 0 volts.
Loopback Enable Input: When set high, the high-speed serial signal is
internally wrapped from the transmitter’s serial loopback outputs back
to the receiver’s loopback inputs. Also, when in loopback mode, the
± DOUT outputs are held static at logic 1. When set low, ± DOUT outputs
and ± DIN inputs are active.
This pin is connected to an isolated pad and has no functionality. It can
be left open, however, TTL levels can also be applied to this pin.
Receiver Byte Clocks: The receiver section recovers two 53.125 MHz
(Fibre Channel)/62.5 MHz (Gigabit Ethernet) receive byte clocks. These
two clocks are 180 degrees out of phase. The receiver parallel data
outputs are alternately clocked on the rising edge of these clocks.
The rising edge of RBC1 aligns with the output of the comma character
(for byte alignment) when detected.
Reference Clock and Transmit Byte Clock: A 106.25 MHz (Fibre
Channel)/125 MHz (Gigabit Ethernet) clock supplied by the host system.
The transmitter section accepts this signal as the frequency reference
clock. It is multiplied by 10 to generate the serial bit clock and other
internal clocks. The transmit side also uses this clock as the transmit byte
clock for the incoming parallel data TX[0]..TX[9]. It also serves as the
reference clock for the receive portion of the transceiver.
15
TRx I/O Definition (cont’d.)
Name
RX[0]
RX[1]
RX[2]
RX[3]
RX[4]
RX[5]
RX[6]
RX[7]
RX[8]
RX[9]
RXCAP0
RXCAP1
SIG_DET
Pin
45
44
43
41
40
39
38
36
35
34
48
49
26
TX[0]
TX[1]
TX[2]
TX[3]
TX[4]
TX[5]
TX[6]
TX[7]
TX[8]
TX[9]
TXCAP1
TXCAP0
VCC
2
3
4
6
7
8
9
11
12
13
16
17
20,
23,28
57,59
5,
10,53
55
50
I-TTL
S
VCC_TXA
29
37
42
18
VCC_TXECL
60
S
VCC_TXHS
63
S
*VCC
VCC_RXA
VCC _RXTTL
Type
O-TTL
Signal
Data Outputs: One 10 bit data byte. RX[0] is the first bit received.
RX[0] is the least significant bit. When there is a loss of input signal at
± DIN, these outputs are held static at logic 1. Refer to SIG_DET (pin 26)
pin definition for more details.
C
Loop Filter Capacitor: A loop filter capacitor for the internal PLL must
be connected across the RXCAP0 and RXCAP1 pins. (typical value = 0.1 µF).
Signal Detect: Indicates a loss of signal on the high-speed differential inputs,
± DIN, as in the case where the transmission cable becomes disconnected.
If ± DIN >= 200 mV peak-to-peak, SIG_DET = logic 1.
If ± DIN < 200 mV and ± DIN > 50 mV, SIG_DET = undefined.
If ± DIN <= 50 mV, SIG_DET = logic 0.
RX[0:9] = 1111111111.
Data Inputs: One 10 bit, 8B/10B-encoded data byte. TX[0] is the first
bit transmitted. TX[0] is the least significant bit.
O-TTL
C
S
S
S
Loop Filter Capacitor: A loop filter capacitor must be connected across
the TXCAP1 and TXCAP0 pins (typical value = 0.1 µF).
Logic Power Supply: Normally 3.3 volts. Used for internal TX and RX
PECL logic. It should be isolated from the noisy TTL supply as well as
possible.
This pin is bonded to an isolated pad and has no functionality. However,
it is recommended that this pin be connected to VCC in order to conform
with the X3T11 “10-bit specification,” and to help dissipate heat.
Analog Power Supply: Normally 3.3 volts. Used to provide a clean
supply line for the PLL and high-speed analog cells.
TTL Power Supply: Normally 3.3 volts. Used for all TTL receiver output
buffer cells.
Analog Power Supply: Normally 3.3 volts. Used to provide a clean
supply line for the PLL and high-speed analog cells.
High-Speed ECL Supply: Normally 3.3 volts. Used only for the last stage
of the high-speed transmitter output cell (HS_OUT) as shown in
Figure 10. Due to high current transitions, this VCC should be well
bypassed to a ground plane.
High-Speed Supply: Normally 3.3 volts. Used by the transmitter side for the
high-speed circuitry. Noise on this line should be minimized for best operation.
16
**VCC
VCC
RXCAP1
VCC_RXA
GND_RXA
*VCC
*VCC
*GND
VCC
GND
VCC
VCC_TXECL
VCC_TXHS
*GND
GND_TXHS
CPLLR
RXCAP0
GND_RXTTL
*VCC
VCC_RXTTL
VCC
HDMP-16x6A/T1636A
*VCC
TOP VIEW
GND_RXTTL
GND
VCC
VCC
GND
TXCAP0
VCC_TXA
TXCAP1
VCC
VCC_RXTTL
VCC_RXTTL
*GND
GND_TXA
GND_RXTTL
CPLLT
VCC
**VCC
*IT IS RECOMMENDED THAT THESE PINS BE CONNECTED TO THE APPROPRIATE
SUPPLY LINE, EITHER VCC OR GND, EVEN THOUGH THE PIN IS BONDED TO AN
ISOLATED PAD. REFER TO THE I/O DEFINITIONS SECTION FOR THESE PINS FOR
MORE DETAILS.
** SUPPLY VOLTAGE INTO VCC_RXA AND VCC_TXA SHOULD BE FROM A LOW NOISE
SOURCE. ALL BYPASS CAPACITORS AND PLL FILTER CAPACITORS ARE 0.1 µF.
Figure 12. Power Supply Bypass.
Start-up Procedure:
The transceiver start-up
procedure(s) use the following
conditions: VCC = +3.3 V ± 5%
and REFCLK = 106.25 MHz
(Fibre Channel)/125 MHz
(Gigabit Ethernet) ± 100 ppm.
After the above conditions have
been met, apply valid data using a
balanced code such as 8B/10B.
Frequency lock occurs within
500 µs. After frequency lock,
phase lock occurs within 2500 bit
times.
Transceiver Power
Supply Bypass and Loop
Filter Capacitors
Bypass capacitors should be
liberally used and placed as close
as possible to the appropriate
power supply pins of the
HDMP-1636A/1646A/T1636A as
shown on the schematic of Figure
12. All bypass chip capacitors are
0.1 µF. The VCC _RXA and
VCC_TXA pins are the analog
power supply pins for the PLL
sections. The voltage into these
pins should be clean with
minimum noise. The PLL loop
filter capacitors and their pin
locations are also shown on
Figure 12. Notice that only two
capacitors are required: CPLLT for
the transmitter and CPLLR for the
receiver. Nominal capacitance is
0.1 µF. The maximum voltage
across the capacitors is on the
order of 1 volt, so the capacitor
can be a low voltage type and
physically small. The PLL
capacitors are placed physically
close to the appropriate pins on
the HDMP-1636A/1646A/
T1636A. Keeping the lines short
will prevent them from picking
up stray noise from surrounding
lines or components.
17
Package Information
Item
Package Material
Lead Finish Material
Lead Finish Thickness
Lead Coplanarity
Details
Plastic
85% Tin, 15% Lead
300-800 µm
HDMP-1636A 0.08 mm max
HDMP-T1636A 0.08 mm max
HDMP-1646A 0.10 mm max
Mechanical Dimensions
PIN #1 ID
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
1
2
3
4
5
6
7
8
9
HDMP-16x6A/T1636A
48
47
46
45
44
43
42
41
40
E1
E
10
39
TOP VIEW
11
38
12
37
13
36
14
35
15
34
16
33
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
c
b
D1
0.25
GAGE PLANE
e
L
D
A2
A
A1
ALL DIMENSIONS ARE IN MILLIMETERS.
PART NUMBER D1/E1
D/E
b
e
L
c
A2
A1
A
HDMP-1636A
10.00
13.20
0.22
0.50
0.88
0.17
2.00
2.45
HDMP-1646A
14.00
17.20
0.35
0.80
0.88
0.17
2.00
0.25
MIN.
0.25
MAX.
TOLERANCE
± 0.10 ± 0.25 ± 0.05 BASIC + 0.15/ MAX.
– 0.10
+ 0.10/
– 0.05
2.35
MAX.
ALL DIMENSIONS ARE IN MILLIMETERS.
PART NUMBER D1/E1
HDMP-T1636A
TOLERANCE
D/E
b
e
L
c
A2
A1
A
0.15
1.20
MAX.
± 0.20 ± 0.20 ± 0.05 BASIC ± 0.15 MAX.
± 0.05 0.05 MAX.
MIN.
Meets JEDEC Pub 95 Outline: MS-026, Van. ACD
10
12
0.22
0.50
0.60
Figure 13. Mechanical Dimensions of HDMP-1636A/1646A/T1636A.
0.20
1.00
www.agilent.com/semiconductors
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Data subject to change.
Copyright © 2002 Agilent Technologies, Inc.
Obsoletes 5968-3339E
April 24, 2002
5988-6605EN