INTERSIL HI2300

HI2300
8-Bit, 18 MSPS, Video A/D Converter
with 3.3V Power Supply Operation
August 1997
Features
Description
• Resolution . . . . . . . . . . . . . . . . . . . . 8-Bit ±1/2 LSB (DL)
• Maximum Sampling Frequency . . . . . . . . . . . 18 MSPS
• Low Power Consumption at 18 MSPS (Typ)
(Reference Current Excluded) . . . . . . . . . . . . . . .18mW
• Synchronizing Clamp Function
The HI2300 is an 8-bit, CMOS A/D converter for video with
synchronizing clamp function and can operate on 3.3V
power supply. The adoption of 2 step-parallel method
achieves ultra-low power consumption and a maximum
conversion speed of 18 MSPS.
Ordering Information
• Clamp ON/OFF Function
PART
NUMBER
• Reference Voltage Self-Bias Circuit
TEMP.
RANGE (oC)
PACKAGE
PKG. NO.
• Input CMOS Compatible
HI2300JCQ
• Three-State TTL Compatible Output
-40 to 85
32 Ld MQFP
Q32.7x7-S
• Power Supply . . . . . . . . . . . . . . . . . . . . . . . . 3.3V Single
• Low Input Capacitance . . . . . . . . . . . . . . . . . . . . . . . 8pF
• Reference Impedance . . . . . . . . . . . . . . . . . . 330Ω (Typ)
• Direct Replacement for Sony CXD2300
Applications
• Portable Equipment
• Hand-Held Instruments
Pinout
NC
DVSS
OE
CLE
DVSS
CCP
VREF
VRBS
HI2300
(MQFP)
TOP VIEW
3231 30 29 28 27 26 25
1
24
2
23
3
22
4
21
5
20
6
19
18
7
17
8
9 10 11 12 13 14 15 16
VRB
AVSS
AVSS
VIN
AVDD
AVDD
VRT
VRTS
TEST
DVDD
TEST
CLK
TEST
TEST
CLP
AVDD
D0
D1
D2
D3
D4
D5
D6
D7
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
4-1230
File Number
4103.1
HI2300
Functional Block Diagram
DVSS
28
OE
30
REFERENCE
SUPPLY
DVSS
25 VRBS
31
24 VRB
D0 (LSB)
1
D1
2
D2
3
D3
4
D4
5
D5
6
D6
7
D7 (MSB)
8
DVDD
10
TEST
(DVDD)
11
CLK
12
TEST
(OPEN)
9
15 CLP
NC
32
TEST
14 (V
DD OR VSS)
LOWER
DATA
LATCH
LOWER ENCODER
(4-BIT)
23 AVSS
LOWER SAMPLING
COMPARATOR (4-BIT)
22 AVSS
21 VIN
LOWER ENCODER
(4-BIT)
LOWER SAMPLING
20 AVDD
COMPARATOR (4-BIT)
19 AVDD
UPPER
DATA
LATCH
UPPER ENCODER
(4-BIT)
18 VRT
UPPER SAMPLING
COMPARATOR (4-BIT)
17 VRTS
16 AVDD
CLOCK
GENERATOR
-
+
M-M
29
27
26
CLE
CCP
VREF
4-1231
TEST
13 (V
DD OR VSS)
HI2300
Pin Descriptions
PIN NUMBER
SYMBOL
1 to 8
D0 to D7
EQUIVALENT CIRCUIT
DESCRIPTION
D0 (LSB) to D7 (MSB) Output.
Di
9
TEST
Leave open during normal usage.
DVDD
9
DVSS
10
DVDD
Digital +3.3V.
12
CLK
Clock Input.
DVDD
12
DVSS
11, 13, 14
TEST
Fix Pin 11 to VDD , Pins 13 and 14 to VDD or
VSS during normal usage.
DVDD
11
13
14
DVSS
15
Inputs Clamp Pulse to Pin 15 (CLP). Clamps
the signal voltage during Low interval.
CLP
DVDD
15
DVSS
16, 19, 20
AVDD
17
VRTS
Analog +3.3V
Generates approximately +1.8V when shorted
with VRT .
AVDD
17
18
VRT
24
VRB
Reference Voltage (Top).
AVDD
Reference Voltage (Bottom).
18
24
AVSS
4-1232
HI2300
Pin Descriptions
(Continued)
PIN NUMBER
SYMBOL
21
VIN
EQUIVALENT CIRCUIT
DESCRIPTION
Analog Input.
AVDD
21
AVSS
25
VBRS
Generates approximately +0.4V when shorted
with VRB .
AVSS
25
26
VREF
Clamp Reference Voltage Input. Clamps so
that the reference voltage and the input signal
during clamp interval are equal.
AVDD
26
AVSS
27
CCP
Integrates the clamp control voltage. The
relationship between the changes in CCP
voltage and in VIN voltage is positive phase.
AVDD
27
AVSS
28, 31
DVSS
29
CLE
Digital Ground.
The clamp function is enabled when
CLE = Low.
The clamp function is set to off and the
converter functions as a normal A/D converter
when CLE = High.
The clamp pulse can be measured by
connecting CLE to DVDD through a
several-hundred-ohm resistor.
DVDD
29
CLAMP
PULSE
DVSS
30
OE
DVDD
Data is output when OE = Low. Pins D0 to D7
are at high impedance when OE = High.
30
DVSS
32
NC
No Connect pin.
4-1233
HI2300
Absolute Maximum Ratings
TA = 25oC
Thermal Information
Thermal Resistance (Typical, Note 1)
θJA (oC/W)
MQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .
122
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
(MQFP - Lead Tips Only)
Supply Voltage (VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V
Reference Voltage (VRT , VRB) . . . . . . . . . .VDD +0.5V to VSS - 0.5V
Input Voltage, Analog (VIN) . . . . . . . . . . . .VDD +0.5V to VSS - 0.5V
Input Voltage, Digital (VIH , VIL) . . . . . . . . .VDD +0.5V to VSS - 0.5V
Output Voltage, Digital (VOH , VOL) . . . . . .VDD +0.5V to VSS - 0.5V
Recommended Operating Conditions
Temperature Range (tOPR) . . . . . . . . . . . . . . . . . . . -40oC to 85oC
Supply Voltage (IDVSS - AVSSI). . . . . . . . . . . . . . . . . . . 0 to 100mV
Power Supply (DVDD , DVSS)(AVDD , AVSS). . . . . . . . .3.14V to 4.0V
Reference Input Voltage (VRB). . . . . . . . . . . . . . . . . . . . . . . . . 0.4V
(VRT) . . . . . . . . . . . . . . . . . . . . . . . . . . 1.8V
Analog Input (ADIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . VRT to VRB
Clock Pulse width (tPW1) . . . . . . . . . . . . . . . . . . . . . . . . 27ns (Min)
(tPW0). . . . . . . . . . . . . . . . . . . . . . . . . 27ns (Min)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
When using a single power supply; fC = 18 MSPS, VDD = 3.3V, VRB = 0V, VRT = 1.5V,
TA = 25oC
PARAMETER
SYMBOL
TEST CONDITIONS
Maximum Conversion Rate
fC Max
VIN = 0 to 1.5V
Minimum Conversion Rate
fC Min
fIN = 1kHz Ramp
fC = 18 MSPS, NTSC Ramp Wave Input
Supply Current
IDD
Reference Pin Current
IREF
MIN
TYP
MAX
UNITS
18
32
-
MSPS
-
32
0.5
MSPS
-
5.5
10
mA
3.3
4.6
6.6
mA
Analog Input Band Width
BW
VIN = 1.4VP-P , 17.9MHz
-
-.9
-
dB
Analog Input Capacitance
CIN
VIN = 0.75V + 0.07 VRMS
-
8
-
pF
230
330
440
Ω
Reference Resistance (VRT to VRB)
Self Bias I
Offset Voltage
Digital Input Voltage
RREF
VRB1
Shorts VRB and VRBS
0.33
0.36
0.39
V
VRT1 - VRB1
Shorts VRT and VRTS
1.30
1.39
1.48
V
EOT
-45
-25
-5
mV
EOB
40
60
80
mV
VIH
2.5
-
-
V
VIL
Digital Input Current
IIH
VDD = Max
IIL
Digital Output Current
IOH
IOL
Digital Output Current
IOZH
IOZL
Output Data Delay
Three-State Output Enable Time
tDL
tPZH
-
-
0.5
V
VIH = VDD
-
-
5
µA
VIL = 0V
-
-
-
µA
OE = VSS
VDD = Min
VOH = VDD - 0.5V
-1.0
-
-
mA
VOL = 0.4V
3.3
-
-
mA
OE = VDD
VDD = Max
VOH = VDD
-
-
16
µA
VOL = 0V
-
-
16
µA
8
18
30
ns
With TTL 1 Gate and 10pF Load
RL = 1kΩ, CL = 20pF, OE = 3V→0V
tPZL
Three-State Output Disable Time
tPHZ
RL = 1kΩ, CL = 20pF, OE = 0V→3V
tPLZ
Integral Nonlinearity Error
EL
fC = 18 MSPS
VIN = 0 to 1.5V
-
+0.5
±1.3
LSB
Differential Nonlinearity Error
ED
fC = 18 MSPS
VIN = 0 to 1.5V
-
±0.3
±0.5
LSB
Aperture Jitter
tAJ
-
30
-
ps
Sampling Delay
tSD
-
4
-
ns
Clamp Offset Voltage
EOC
Clamp Pulse Delay
VIN = DC
VREF = 0.5V
-20
0
+20
mV
PWS = 3µs
VREF = 1.5V
-30
-10
+10
mV
-
25
-
ns
tCPD
4-1234
HI2300
Digital Output
The following table shows the relationship between analog
input voltage and digital output code.
DIGITAL OUTPUT CODE
INPUT SIGNAL
VOLTAGE
STEP
VRT
0
•
•
•
•
•
•
MSB
1
1
LSG
1
1
•
•
•
127
1
0
0
0
•
128
0
1
1
1
•
•
•
•
•
•
•
•
•
VRB
255
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
•
0
0
0
0
Timing Chart
tPW1
tPW0
CLOCK
ANALOG INPUT
DATA OUTPUT
N
N+1
N+2
N-2
N-3
N-1
N +3
N+4
N
N-1
tD
tD = 18ns
: Analog Sampling Point
4-1235
HI2300
Typical Application Circuits
+3.3V (DIGITAL)
HC04
CLOCK IN
0.1µ
LATCH CK
(NOTE 2) Q
CLAMP PULSE IN
OPEN
16
0.01µ
+3.3V (ANALOG)
VIDEO IN
10µ 75Ω
+
0.1µ
10p
0.01µ
+3.3V
(ANALOG)
15
14
13
12
11
10
9
17
8
D7
18
7
D6
19
6
D5
20
5
D4
21
4
D3
22
3
D2
23
2
D1
24
1
D0
25
26
27
28
29
30
31
32
VREF
0.01µ
20K
GND (DIGITAL)
GND (ANALOG)
NOTE:
1. The clamp pulse is latched by the sampling clock of ADC, but that is not necessary for basic clamp operaiotn. However, slight small beat
may be generated as Vertical sag according to the relationship between the sampling frequency and the clamp pulse frequency. At such
time, the latch circuit is efective in this case.
FIGURE 1. WHEN CLAMP IS USED (SELF BIAS)
+3.3V (DIGITAL)
HC04
0.1µ
CLOCK IN
OPEN
16
0.01µ
+3.3V (ANALOG)
15
14
13
12
11
10
9
8
17
7
18
VIDEO IN
10µ 75Ω
+
10p
0.1µ
0.01µ
CLAMP LEVEL
SETTING DATA
6
19
20
5
21
4
22
3
23
2
24
SUBTRACTER,
COMPARATOR,
ETC.
1
25
26
27
28
29
30
31
32
DAC,
PWM,
ETC.
0.01µ
GND (DIGITAL)
GND (ANALOG)
NOTES:
2. The relationship between the changes in CCP voltage (Pin 27) and in VIN voltage is positive phase.
3. ∆VIN/∆VCCP = 3.0 (fS = 20 MSPS).
FIGURE 2. DIGITAL CLAMP (SELF BIAS)
4-1236
INFORMATION OTHER THAN
CLAMP INTERVAL IS AT
HIGH IMPEDANCE.
HI2300
Typical Application Circuits
(Continued)
+3.3V (DIGITAL)
HCO4
0.1µ
CLOCK IN
OPEN
16
+3.3V
(ANALOG)
15
14
13
12
11
10
9
17
8
D7
18
7
D6
19
6
D5
20
5
D4
21
4
D3
22
3
D2
23
2
D1
24
1
D0
0.01µ
VIDEO IN
75
0.1µ
10p
0.01µ
25
26
27
28
29
30
31
32
+3.3V (DIGITAL)
GND (ANALOG)
GND (DIGITAL)
FIGURE 3. WHEN CLAMP IS NOT USED (SELF BIAS)
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
4-1237