HSP061-4NY8 4-line ESD protection for high speed lines Features ■ flow-through routing to keep signal integrity ■ ultra-large bandwidth: 6 GHz ■ ultra low capacitance: 0.6 pF ■ low time domain reflection ■ low leakage current: 100 nA at 25 °C ■ extended operating junction temperature range: -40 °C to 150 °C ■ package size in mm: 2 x 1 x 0.5 ■ RoHS compliant µQFN-8L package Figure 1. Functional schematic (top view) Benefits ■ high ESD robustness of the equipment ■ suitable for high density boards I/O 1 1 Internally 8 not connected I/O 2 2 Complies with following standards ■ MIL-STD 883G Method 3015-7 Class 3B: – 8 kV GND 3 ■ IEC 61000-4-2 level 4: – 8 kV (contact discharge) I/O 3 4 I/O 4 5 Applications 7 GND 6 Internally not connected The HSP061-4NY8 is designed to protect against electrostatic discharge on sub micron technology circuits driving: ■ HDMI 1.3 and 1.4 ■ Digital Video Interface ■ Display Port ■ USB 3.0 ■ Serial ATA Description The HSP061-4NY8 is a 4-channel ESD array with a rail to rail architecture designed specifically for the protection of high speed differential lines. The ultra-low variation of the capacitance ensures very low influence on signal-skew. The large bandwidth and the low reflection make it compatible with 5 Gbps. The device is packaged in µQFN-8L with a 400 µm pitch, which minimizes the PCB area. October 2010 Doc ID 17414 Rev 2 1/10 www.st.com 10 Characteristics HSP061-4NY8 1 Characteristics Table 1. Absolute maximum ratings Tamb = 25 °C Symbol Parameter Value Unit 8 kV VPP Peak pulse voltage Ipp Repetitive peak pulse current (8/20 µs) 3 A Tj Operating junction temperature range -40 to +150 °C Storage temperature range -65 to +150 °C 260 °C Tstg IEC 61000-4-2 contact discharge TL Maximum lead temperature for soldering during 10 s Table 2. Electrical characteristics Tamb = 25 °C Symbol Parameter Test conditions Min. Typ. Max. Unit VBR Breakdown voltage IR = 1 mA IRM Leakage current VRM = 3 V VCL Clamping voltage IEC 61000-4-2, +8 kV contact (IPP = 30 A), measured at 30 ns 18 Capacitance (input/output to ground) VI/O = 0 V F = 1 MHz, VOSC = 30 mV 0.6 0.8 pF Capacitance variation (input/output to ground) VI/O = 0 V F = 1 MHz, VOSC = 30 mV 0.03 0.05 pF Cut-off frequency -3dB CI/O - GND ΔCI/O - GND fC ZDiff Differential impedance tr = 200 ps (10 Z0 Diff = 100 Ω 6 V 100 V 6 90%)(1) 85 100 nA GHz 115 Ω 1. HDMI specification conditions. This information can be provided for other applications. Please contact your local ST office. 2/10 Doc ID 17414 Rev 2 HSP061-4NY8 Figure 2. Characteristics Leakage current versus junction temperature (typical values) 10.00 0 VR = V RM = 3 V IR (nA) Figure 3. S21 attenuation measurement db -3 1.00 -6 0.10 -9 Tj (°C) 0.01 25 Figure 4. 50 75 100 125 f (Hz) 150 Differential impedance (Zdiff)(1) -12 10 MHz 30 MHz Figure 5. tr = 200 ps (10% - 90%) 12.5 Ω /div 100 MHz 300 MHz 1 GHz 3 GHz Eye diagram - HDMI mask at 3.4 Gbps per channel(1) Vertical : 200 mV / div Horizontal : 50 ps / div Z0Diff = 100 Ω 1. HDMI specification conditions. This information can be provided for other applications. Please contact your local ST office. Figure 6. ESD response to IEC 61000-4-2 (+8 kV contact discharge) Figure 7. ESD response to IEC 61000-4-2 (-8 kV contact discharge) 50 V / div 20 ns / div 20 GS / s 50 V / div 20 ns / div 20 GS / s Doc ID 17414 Rev 2 3/10 Ordering information scheme 2 HSP061-4NY8 Ordering information scheme Figure 8. Ordering information scheme HSP 06 1 - 4 NY8 High speed line protection Breakdown Voltage Version Number of lines Package µQFN-8L 4/10 Doc ID 17414 Rev 2 HSP061-4NY8 Package information ● Epoxy meets UL94, V0 ● Lead-free package In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Table 3. µQFN-8L dimensions Dimensions Ref Millimeters e b Pin 1 ID E r L p m n A Figure 9. A1 Inches Min Typ Max Min Typ Max A 0.45 0.50 0.55 0.018 0.020 0.022 A1 0.00 0.02 0.05 0.00 0.001 0.002 b 0.15 0.20 0.25 0.006 0.008 0.010 D 1.95 2.00 2.05 0.077 0.079 0.081 E 0.95 1.00 1.05 0.037 0.039 0.041 e 0.35 0.40 0.45 0.014 0.016 0.018 L 0.25 0.35 0.45 0.010 0.014 0.018 D m 0.40 0.016 n 0.15 0.006 p 0.11 0.004 r 0.05 0.002 Footprint recommendations (dimensions in mm) Figure 10. Marking 1.4 . 0.2 . . 1.8 0.4 0.4 . 3 Package information H4N 0.55 According to IPC7351 Doc ID 17414 Rev 2 5/10 Package information HSP061-4NY8 Figure 11. µQFN-8L tape and reel specification Dot identifying Pin A1 location 2.0 Ø 1.55 4.0 3.5 1.17 H4N H4N H4N 8.0 2.17 1.75 0.22 4.0 0.63 All dimensions are typical values in mm 6/10 User direction of unreeling Doc ID 17414 Rev 2 HSP061-4NY8 4 Recommendation on PCB assembly Recommendation on PCB assembly Figure 12. Recommended stencil window position 7 µm Copper Thickness: 100 µm 674 µm Footprint Stencil window Footprint 13 µm 200 µm 13 µm 7 µm 374 µm 13 µm 400 µm 4.1 10 µm 186 µm 200 µm Solder paste 1. 4.2 530 µm 550 µm 674 µm 700 µm 13 µm 7 µm 10 µm 186 µm 13 µm 700 µm 13 µm 7 µm Use halide-free flux, qualification ROL0 according to ANSI/J-STD-004. 2. “No clean” solder paste recommended. 3. Offers a high tack force to resist component displacement during PCB movement. 4. Use solder paste with fine particles: powder particle size 20-45 µm. Placement 1. Manual positioning is not recommended. 2. It is recommended to use the lead recognition capabilities of the placement system, not the outline centering. 3. Standard tolerance of ± 0.05 mm is recommended. 4. 3.5 N placement force is recommended. Too much placement force can lead to squeezed out solder paste and cause solder joints to short. Too low placement force can lead to insufficient contact between package and solder paste that could cause open solder joints or badly centered packages. 5. To improve the package placement accuracy, a bottom side optical control should be performed with a high resolution tool. 6. For assembly, a perfect supporting of the PCB (all the more on flexible PCB) is recommended during solder paste printing, pick and place and reflow soldering by using optimized tools. Doc ID 17414 Rev 2 7/10 Recommendation on PCB assembly 4.3 HSP061-4NY8 PCB design 1. To control the solder paste amount, the closed via is recommended instead of open vias. 2. The position of tracks and open vias in the solder area should be well balanced. The symmetrical layout is recommended, in case any tilt phenomena caused by asymmetrical solder paste amount due to the solder flow away. Figure 13. Printed circuit board layout recommendations 1 8 400 µm 2 Via to Via to 3 GND 7 GND 4 6 5 Footprint pad 4.4 PCB tracks Reflow profile Figure 14. ST ECOPACK® recommended soldering reflow profile for PCB mounting Temperature (°C) 260°C max 255°C 220°C 180°C 125 °C 2°C/s recommended 2°C/s recommended 6°C/s max 6°C/s max 3°C/s max 3°C/s max 0 0 1 2 3 4 5 10-30 sec 90 to 150 sec Note: 8/10 6 7 Time (min) 90 sec max Minimize air convection currents in the reflow oven to avoid component movement. Doc ID 17414 Rev 2 HSP061-4NY8 5 Ordering information Ordering information Table 4. 6 Ordering information Order code Marking Package Weight Base qty Delivery mode HSP061-4YN8 H4N µQFN 9.55 mg 6000 Tape and reel (7”) Revision history Table 5. Document revision history Date Revision Changes 20-Apr-2010 1 Initial release. 15-Oct-2010 2 Updated values for ΔCI/O - GND in Table 2. Updated Figure 13. Updated package name. Doc ID 17414 Rev 2 9/10 HSP061-4NY8 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. 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