INTERSIL HSP43481GM

HSP43481/883
TM
August 1999
NO
IG
DES
EW
N
FO R
E D 388 1
D
N
ME
SP4
C O M S ee H
E
R
T
NS
Digital Filter
Features
Description
• This Circuit is Processed in Accordance to MIL-STD883 and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.
The HSP43481/883 is a video-speed Digital Filter (DF)
designed to efficiently implement vector operations such as
FIR digital filters. It is comprised of four filter cells cascaded
internally and a shift-and- add output stage, all in a single
integrated circuit. Each filter cell contains an 8 x 8 multiplier,
three decimation registers and a 26-bit accumulator which
can add the contents of any filter cell accumulator to the output stage accumulator shifted right by eight-bits. The
HSP43481/883 has a maximum sample rate of 25.6MHz.
The effective multiply-accumulate (MAC) rate is 102MHz.
• 0MHz to 25.6MHz Sample Rate
• Four Filter Cells
• 8-Bit Coefficients and Signal Data
• Low Power CMOS Operation
- ICCSB = 500µA Maximum
- ICCOP = 110µA Maximum at 20MHz
• 26-Bit Accumulator Per Stage
The HSP43481/883 can be configured to process expanded
coefficient and word sizes. Multiple devices can be cascaded for larger filter lengths without degrading the sample
rate or a single device can process larger filter lengths at
less than 25.6MHz with multiple passes. The architecture
permits processing filter lengths of over 1000 taps with the
guarantee of no overflows. In practice, most filter coefficients
are less than 1.0, making even larger filter lengths possible.
The HSP43481/883 provides for unsigned or two’s complement arithmetic, independently selectable for coefficients
and signal data.
• Filter Lengths Up To 1032 Taps
• Expandable Coefficient Size, Data Size and Filter Length
• Decimation by 2, 3 or 4
Applications
• 1-D and 2-D FIR Filters
• Radar/Sonar
• Adaptive Filters
• Echo Cancellation
Each DF filter cell contains three resampling or decimation
registers which permit output sample rate reduction at rates of
1
/2, 1/3 or 1/4 the input sample rate. These registers also provide the capability to perform 2-D operations such as N x N
spatial correlations/convolutions for image processing applications.
• Complex Multiply-Add
• Sample Rate Converters
Ordering Information
PART NUMBER
TEMPERATURE RANGE
o
PACKAGE
o
HSP43481GM-20/883
-55 C to +125 C
68 Lead PGA
HSP43481GM-25/883
-55oC to +125oC
68 Lead PGA
Block Diagram
VCC
DIENB
CIENB
DCM0 - DCM1
ERASE
VSS
8
5
8
TCCI
CIN0 - CIN7
RESET
CLK
ADR0 - 1
DIN0 - DIN7 TCS
FILTER
CELL 0
8
4
8
8
26
4
FILTER
CELL 1
8
8
8
FILTER
CELL 2
26
26
8
FILTER
CELL 3
26
TCCO
8
COUT0 - COUT 7
COENB
2
MUX
ADR0, ADR1
2
OUTPUT
STAGE
SHADD
SENBL
SENBH
26
2
DB302
RESET
CLK
26
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2001, All Rights Reserved
3-193
File Number
2450.4
HSP43481/883
All Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice.
Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable.
However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from
its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
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