fax id: 3508 1I CD20 93 ICD2093 “Super Buffer” Clock Generator Features • Selectable CPU clock provides eight 2X or 1X outputs which handle all 486 processor clocking requirements • Less than 250 ps total skew between Hi-Drive (48 mA), Hi-Load (50 pF) CPU clock outputs • Four fixed outputs: 14.31818 MHz (2), 16 MHz, and 24 or 32 MHz handle all other system clocking requirements • CPU clock frequency range: 10 MHz to 100 MHz with 50% duty cycle • Optional power-down mode • Three-state oscillator control disables outputs for test purposes • Phase-locked loop oscillator input derived from single 14.31818 MHz crystal • Sophisticated internal loop-filter requires no external components • 5V operation • Low-power, high-speed CMOS technology • Available in 24-pin SOIC package configuration Functional Description Today’s high-end personal computers require a CPU system clock which exhibits a large drive capability (high fanout) without degradation in rise and fall times. The classical solution has been to distribute and buffer this clock. The ICD2093 alleviates this problem by providing eight 1X or 2X Clock outputs with extremely low skew between outputs. The ICD2093 also supplies other clocks required in a high-performance system: the system I/O and bus clocks. The ICD2093 consists of one crystal controlled oscillator, two phase-locked loops, and twelve different outputs in a single package. Block Diagram CPUA CPUB CPUC SKEW ADJUST ÷4 CPUCLK PLL CPUD Configuration option: ÷1 or ÷2 outputs) CPUE CPUF S2 S1 CPUG S0 CPUH ÷6 XTALIN OSCILLATOR XTALOUT (INPUT FROM 14.31818 MHz CRYSTAL) SYSCLK PLL ÷4 96 MHz ÷3 16 MHz 2:1 MUX SYSCLK (24 or 32 MHz) (Configuration option) SYSBUS_A SYSBUS_B ICD2093-1 GND (3) VDD (2) AVDD SHUTDOWN Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 June 1994 ICD2093 Pin Configuration SOIC Top View XTALOUT S0 SHUTDOWN GND SYSBUS_A SYSBUS_B GND CPUA CPUB CPUC CPUD V DD 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 XTALIN S2 19 18 SYSCLK CPUH VDD CPUG CPUF CPUE GND 17 16 15 14 13 S1 AV DD 16MHz ICD2093-2 Pin Summary Name Number Description XTALOUT[1] 1 Oscillator output to a 14.318 MHz parallel-resonant crystal S0 2 CPU Clock ROM Select Line—Bit 0 (LSB) SHUTDOWN (OE) 3 When pulled LOW, shuts down oscillator, PLL, and all dynamic logic. Can be made three-state Output Enable via configuration option. Internal pull-up allows for no-connect if shutdown operation is not needed. GND 4 Ground SYSBUS_A 5 14.31818 MHz Output SYSBUS_B 6 14.31818 MHz Output GND 7 Ground CPUA 8 CPU Clock Output A (1X or 2X)[2] CPUB 9 CPU Clock Output B (1X or 2X)[2] CPUC 10 CPU Clock Output C (1X or 2X) [2] CPUD 11 CPU Clock Output D (1X or 2X) [2] VDD 12 +5V to I/O Ring GND 13 Ground CPUE 14 CPU Clock Output E (1X or 2X)[2] CPUF 15 CPU Clock Output F (1X or 2X)[2] CPUG 16 CPU Clock Output G (1X or 2X)[2] VDD 17 +5V to I/O Ring CPUH 18 CPU Clock Output H (1X or 2X) [2] SYSCLK 19 24 MHz or 32 MHz Output (factory configurable) 16 MHz 20 16 MHz Output AVDD 21 +5V to Analog Core S1 22 CPU Clock ROM Select Line—Bit 1 S2 23 CPU Clock ROM Select Line—Bit 2 (MSB) XTALIN[1] 24 Oscillator input from a 14.31818 MHz crystal Notes: 1. For best accuracy, use a parallel-resonant crystal, assume CLOAD = 17 pF. 2. All the CPU outputs can be 1X, 2X, or any mix of the two (the outputs of each type are contiguous). 2 ICD2093 Clock Operation Fixed Frequency Oscillator Operation Table 2 lists the available fixed frequency outputs. CPUCLK PLL Table 2. CPUCLK ROM Selection Outputs The output frequency of the CPU clock PLL (CPUCLK) is selected by the Clock Selection Inputs S0−S2. This lets the ICD2093 support different microprocessor speed configurations. Desired Frequency (MHz) The selection lines can be changed at any time to select a new frequency. When this occurs, the internal phase-locked loop immediately seeks the new frequency in the 33.333-MHz to 80-MHz range. Actual Frequency (MHz) Error (PPM) Option −1 Option −2 Option −1 Option −2 24.000 23.993 23.967 1359 307 32.000 31.990 31.957 1359 307 Design Considerations Table 1. CPUCLK ROM Selection Outputs Skew Issues Desired Actual Actual VCO Freq. CPUCLK CPU/2 Freq. (MHz) (MHz) (MHz) S2 S1 S0 (MHz) Error (PPM) 0 0 0 20.000 20.003 10.002 80.013 167 0 0 1 33.333 33.322 16.661 66.645 331 0 1 0 60.000 60.000 30.000 120.000 0 0 1 1 40.000 40.006 20.003 80.013 1 0 0 50.000 50.114 25.057 100.227 2267 1 0 1 66.667 66.818 33.409 133.636 2270 1 1 0 80.000 80.013 40.006 160.026 167 1 1 1 100.000 100.227 The ICD2093 offers eight CPUCLK ÷1 or ÷2 outputs, CPUA−CPUH. These outputs have been optimized to minimize skew between any two CPUA−CPUH outputs. The standard drive on all CPU outputs is 48 mA, with a 3-ns rise and fall time when driving 50 pF. To minimize skew, output loads should be balanced and the printed circuit board trace lengths should be equal. The high-performance output driver of the ICD2093 requires the engineer to observe proper transmission line techniques, including termination, when designing for the ICD2093. (See the Termination section for suggestions on proper termination.) 167 50.114 100.227 2267 Table 3 estimates the incremental skew (in addition to worst-case specification) caused by unbalanced loading. The table includes data for driving both TTL loads and CMOS threshold loads. There are two normalized measurements given: all loads normalized to 0 pF, and all loads at 30 pF (the latter being a more realistic operating assumption). Table 3. CPUCLK ROM Selection Outputs Rising Edge (ns) Falling Edge (ns) Load Threshold Volts Normalized at 0 pF Normalized at 30 pF Normalized at 0 pF Normalized at 30 pF 50 pF 2.5 1.10 0.38 1.03 0.33 50 pF 1.4 0.72 0.22 1.31 0.44 40 pF 2.5 0.92 0.20 0.88 0.18 40 pF 1.4 0.62 0.12 1.09 0.22 30 pF 2.5 0.72 0.00 0.70 0.00 30 pF 1.4 0.50 0.00 0.87 0.00 20 pF 2.5 0.52 −0.20 0.50 −0.20 20 pF 1.4 0.35 −0.15 0.62 −0.25 10 pF 2.5 0.30 −0.42 0.28 −0.42 10 pF 1.4 0.20 −0.30 0.32 −0.55 0 pF 2.5 0.00 −0.72 0.00 −0.70 0 pF 1.4 0.00 −0.50 0.00 −0.87 3 ICD2093 Termination The ICD2093 provides fast rise and fall times on its outputs to drive large loads, which require the PCB designer to observe proper transmission line techniques. There are three principal techniques for proper termination. The optimum choice depends on individual requirements. Device 8Ω Z0 pin Series Termination PCB Trace The main drawback of this technique is that CL adversely affects rise and fall times (see Figure 1). RT RT =Z 0 CT ICD2093 Driver Parallel Termination CL The main drawback of this technique is that it consumes power. C L−Receiver Capacitance Figure 3. AC Termination VT = VDD ÷ 2 for minimum power. (Note that VT should not equal receiver threshold. TTL systems often set VT at 3V using Thévenin equivalent circuit.) See example divider in Figure 2. Power Calculation Actual current drain is a function of frequency and circuit loading. The operating current of a given output is given by the equation I = C • V • f, where I=current, C=load capacitance, V=output voltage in Volts (usually 5V for rail-to-rail CMOS pads) and f=output frequency in MHz. AC Termination The main drawback of this technique is that it is not as good at high frequencies (see Figure 3). To calculate total operating current, sum the following: ISYSBUS_A ISYSBUS_B ICPUA ICPUB ICPUC ICPUD ICPUE ICPUF ICPUG ICPUH I(Internal) RT =Z 0 −8Ω 8Ω Device RT Z0 pin PCB Trace CL C L−Receiver Capacitance ICD2093 Driver Figure 1. Series Termination ⇒ ⇒ ⇒ ⇒ ⇒ ⇒ ⇒ ⇒ ⇒ ⇒ ⇒ C14 • V • 14.318 C24 • V • 14.318 CCLKA • V • fCLKA CCLKB • V • fCLKB CCLKC • V • fCLKC CCLKD • V • fCLKD CCLKE • V • fCLKE CCLKF • V • fCLKF CCLKG • V • fCLKG CCLKH • V • fCLKH .06 A (60 mA) This yields an approximation of the actual operating current. For unconnected output pins, one can assume 5−10 pF loading, depending on the package type. . Some typical values are displayed in Table 4. Device 8Ω Table 4. Operating Current Typical Values Z0 pin PCB Trace RT =Z 0 ICD2093 Driver RT CL VT C L−Receiver Capacitance 5V 83Ω Example: 50Ω @ 3V = 125Ω Figure 2. Parallel Termination 4 Frequency Capacitive Load Current (in mA) 66.6 MHz 30 pF 115 ICD2093 General Considerations Maximum Ratings Power-Down Operation (Above which the useful life may be impaired. For user guidelines, not tested.) In the power-down state, the oscillator, PLL, and all dynamic logic is shut down. Supply Voltage to Ground Potential ................. −0.5V to +7.0V DC Input Voltage ..........................................−0.5V to VDD +0.5V Storage Temperature ....................................... −65°C to +150°C Note that, during shutdown, the internal PLLs are turned off. Upon restarting, there will be a 5-msec interval during which the VCOs stabilize. See Power-Down Timing in the Switching Waveforms section for further timing information. Max soldering temperature (10 sec)............................. 260°C Junction temperature.................................................... 140°C Three-State Output Operation Package power dissipation..................................... 1000 mW If the OE configuration is chosen, then the SHUTDOWN pin becomes an OE pin, which, when pulled LOW, will three-state all the clock output lines. This supports Wired-OR connections between external clock lines, and allows for procedures such as automated testing where the clock must be disabled. The OE signal contains an internal pull-up; it can be left unconnected if three-state operation is not required. The output pads contain weak pull-down resistors. Operating Range Ambient Temperature VDD & AVDD 0°C ≤ TAMBIENT ≤ 70°C 5V ± 5% Electrical Characteristics Over the Operating Range Parameter VOH Description Output HIGH Voltage Test Conditions IOH = −48 mA[3] Min. Max. VDD−0.5 = 48 mA[3] Unit V VOL Output LOW Voltage IOL VIH Input HIGH Voltage Except crystal inputs 0.5 VIL Input LOW Voltage Except crystal inputs 0.8 V IIH Input HIGH Current VIN = VDD−0.5V 150 µA IIL Input LOW Current VIN = +0.5V −250 µA IOZ Output Leakage Current (Three-state) 150 µA IDDA Power Supply to Core IDD Power Supply Current 1 CPU @ 66 MHz 7 CPU @ 33 MHz Inputs @ VDD or GND CL Total Cap. Load/CPU Output 2.0 −10 Notes: 3. Option −2 has half the output drive capability: IOH=−24 mA, IOL=24 mA, CL=25 pF. 4. Maximum load on all CPU outputs can exceed the maximum specifications. 5 V V 18 mA 130 mA 50[3, 4] pF ICD2093 Switching Characteristics[5] Parameter Name Description f(REF) Reference Frequency Reference input normal value t(REF) Reference Clock Period 1 ÷ f(REF) t1 Input Duty Cycle Duty cycle for the input oscillator defined as t1 = t1A ÷ t1B t2 Output Period t3 Output Duty Cycle Duty cycle for the outputs, measured @ CMOS VTH of VDD ÷2 (special screening required for 100 MHz) t3 = t1A ÷ t1B t4 Rise Times Rise time of clock outputs (50-pF load @ 10 MHz) t5 Fall Times t6 Skew t8 Min. 25% Typ. Max. Unit 14.318 MHz 69.84 ns 50% 75% 10 100 MHz 100 10 MHz 40% 60% ns 3.5 ns Fall time of clock outputs (50-pF load @ 10 MHz) 4 ns Leading edge skew between 1X and 2X outputs and CL=50 pF 500 ps Skew Leading edge skew between 1X and 1X or 2X and 2X outputs and CL=50 pF 250 ps tVCO VCO Settle Time Time for VCO to transition smoothly and monotonically from the original to the new frequency 3 mse c t10 Three-state Time Time for the outputs to go into three-state mode after OE signal goes LOW 20 ns t11 Clock Enable Time Time for the outputs to recover from three-state mode after OE signal goes HIGH 20 ns t12 SYSBUS Skew Leading edge skew between SYSBUS outputs 500 ps t13 SYSBUS Skew Trailing edge skew between SYSBUS outputs 500 ps t14 Power-Down Time to invoke power-down option 20 ns t15 Power-Up Time to revoke power-down option 20 ns Note: 5. Input capacitance is typically 10 pF, except for the crystal pads. Switching Waveforms Duty Cycle Timing t1B t1A VDD/2 V DD/2 VDD/2 ICD2093-3 6 ICD2093 Switching Waveforms (continued) Rise and Fall Times t(REF) f (REF) t2 ALL OUTPUTS t3 t4 t5 90% 90% 10% 10% ICD2093-4 CPUCLK Skew CPUCLK t6 ANY CPU/2 t8 ANY OTHER CPU/2 ICD2093-5 Selection Timing S0−S2 f OUT New frequency CPUCLK VCO Settle Time Original frequency time tVCO ICD2093-6 (Valid for all transitions except CPUCLK = 10 MHz ⇒100MHz) 7 ICD2093 Switching Waveforms (continued) Three-StateTiming OE 1.4V 1.4V t10 t 11 THREE-STATEOUTPUT ALL THREE-STATE OUTPUTS ICD2093-7 SYSBUS Skew SYSBUS_A t13 t 12 SYSBUS_B ICD2093-8 Power-DownTiming POWER-DOWN OPTION (SELECTED BY OE) t 14 t 15 (forced LOW) ALL OUTPUTS f OUT f OUT ICD2093-9 Test Circuit DEVICE UNDER TEST VDD CLK out + CLOAD 22Ω AVDD + 2.2 µF Tantalum GND ICD2093-10 8 ICD2093 Typical AC and DC Characteristics 149 148 147 146 145 160 0.75 140 0.70 120 0.65 POWER (WATTS) IDD (mA) IDD (mA) 155 154 153 152 151 150 100 80 60 40 0.60 0.55 0.50 0.45 0.40 20 0.35 0 0.30 20 40 60 80 100 FREQUENCY OF 1 CPU OUTPUT WITH 7 @ ÷2, @ 0 °C 0 10 20 30 40 50 60 70 AMBIENT TEMPERATURE ( °C) WITH 1 CPU OUTPUT @ ÷1 (100MHz) & 7 @ ÷2 CALCULATED POWER DISSIPATION 10 20 30 40 50 CLOAD (pF) WITH 1 CPU OUTPUT @ 66 MHz & 7 @ ÷2 (OPTION−1) WORST-CASE POWER,VDD =5.25V,CLOAD =50 pF (SIMILAR TO −1 OPTION) 0.75 0.70 POWER (WATTS) 0.65 0.60 0.55 0.50 0.45 0.40 0.35 0.30 10 15 20 25 CLOAD (pF) WITH 6 CPU OUTPUT @ 66 MHz & 2 @ ÷2 (OPTION−2) 1.50 1.40 1.30 1.20 1.10 1.00 0.90 0.80 0.70 0.60 0.50 100MHz 66MHz 60MHz MAX. POWER 50MHz 33MHz 0 1 2 3 4 5 6 1.00 MAX. POWER 100MHz 0.90 0.80 66MHz 60MHz 50MHz 0.70 0.60 33MHz 0.50 0.40 0 7 8 NUMBER OF÷1 OUTPUTS WITH OTHER OUTPUTS @ ÷2 WORST-CASE POWER, VDD =5.25V, CLOAD=25 pF (SIMILAR TO −2 OPTION) POWER (WATTS) POWER (WATTS) CALCULATED POWER DISSIPATION I TOTAL I TOTAL 1 2 3 4 5 6 7 8 NUMBER OF÷1 OUTPUTS WITH OTHER OUTPUTS @ ÷2 9 ICD2093: 3/95 Revision: March 29, 1995 ICD2093 Configuration Options Option −1 Option −2 CPUA ÷2 ÷2 CPUB ÷2 ÷2 CPUC ÷2 ÷1 CPUD ÷2 ÷1 CPUE ÷2 ÷1 CPUF ÷2 ÷1 CPUG ÷2 ÷1 Signal/Pin CPUH ÷1 ÷1 Pin 3 OE SHUTDOWN 24 MHz 24 MHz SYSCLK Ordering Information Ordering Code ICD2093 Package Name S13 Operating Range Package Type 24-Pin SOIC C=0°C to +70°C @ VDD=5V Example: Order ICD2093SC−1 for the ICD2093, 24-pin plastic SOIC, commercial temperature range device which uses the standard configuration code −1 (SYSCLK=24 MHz, Power-Down not enabled, one ÷1 CPU clock and seven ÷2 CPU clocks). Clock Output Options Standard Configuration −1 Custom configurations are also available. To order a custom configuration, please contact your Cypress representative. Document #: 38−00401 Package Diagram 24-Lead (300-Mil) Molded SOIC S13 ICD2093-11 © Cypress Semiconductor Corporation, 1995. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.