FemtoClock™ Dual VCXO Video PLL ICS810001-22 DATA SHEET General Description Features The ICS810001-22 is a member of the HiperClockS™ family of high performance clock solutions from IDT. HiPerClockS™ The ICS810001-22 is a PLL based synchronous clock generator that is optimized for digital video clock jitter attenuation and frequency translation. The device contains two internal frequency multiplication stages that are cascaded in series. The first stage is a VCXO PLL that is optimized to provide reference clock jitter attenuation, and to support the complex PLL multiplication ratios needed for video rate conversion. • • Jitter attenuation and frequency translation of video clock signals • Support of High-Definition (HD) and Standard-Definition (SD) pixel rates • Dual VCXO-PLL supports both 60 and 59.94Hz base frame rates in one device • Dual PLL mode for high-frequency clock generation (32.967MHz to 162MHz) The second stage is a FemtoClock™ frequency multiplier that provides the low jitter, high frequency video output clock. • VCXO-PLL mode for low-frequency clock generation (27MHz and 26.973MHz) Preset multiplication ratios are selected from internal lookup tables using device input selection pins. The multiplication ratios are optimized to support common video rates used in professional video system applications. The VCXO requires the use of an external, inexpensive pullable crystal. Two crystal connections are provided (pin selectable) so that both 60 and 59.94Hz base frame rates can be supported. The VCXO requires external passive loop filter components which are used to set the PLL loop bandwidth and damping characteristics. • • • • One LVCMOS/LVTTL PLL clock output • • • 3.3V supply voltage Supported Input Frequencies Supported Output Frequencies ICS Supports SMTPE 292M, ITU-R Rec. 601/656 and MPEG-transport clocks Two selectable LVCMOS/LVTTL input clocks LVCMOS/LVTTL compatible control signals RMS phase jitter @148.5MHz, using a 27MHz crystal (12kHz – 20MHz): 1.01ps (typical) 0°C to 70°C ambient operating temperature Available in a lead-free (RoHS 6) 32-VFQFN package fVCXO = 27MHz fVCXO = 26.973MHz fVCXO = 27MHz fVCXO = 26.973MHz 67.5kHz 67.4326 148.5 148.3516 56.25kHz 56.1938 74.25 74.1758 45.0kHz 44.955 49.5 49.4505 37.5kHz 37.4625 33 32.967 33.75kHz 33.7163 162 161.8382 31.4685kHz 31.4371 81 80.9191 31.25kHz 31.2188 54 53.9461 28.125kHz 28.0969 36 35.9640 27.0kHz 26.973 27 26.973 22.5kHz 22.4775 18.75kHz 18.7313 18kHz 17.982 15.7343kHz 15.7185 15.625kHz 15.6094 ICS810001BK-22 REVISION A SEPTEMBER 8, 2009 1 ©2009 Integrated Device Technology, Inc. ICS810001-22 Data Sheet FEMTOCLOCK™ DUAL VCXO VIDEO PLL 0 CLK0 0 CLK1 1 XTAL_SEL XTAL_OUT1 XTAL_IN1 XTAL_IN0 LF1 LF0 ISET Loop Filter XTAL_OUT0 Block Diagram 1 Phase Detector VCXO Charge Pump VCXO Feedback Divider (M Value from Table) CLK_SEL V3:V0 VCXO Divider Table 4 MR VCXO Jitter Attenuation PLL 10 FemtoClock Frequency Multiplier 11 0= x22 1= x24 Master Reset 01 10 11 Output Divider 00 = 4 01 = 8 10 = 12 11 = 18 00 01 10 11 Q OE MF N1:N0 nBP1:nBP0 2 2 VDD XTAL_SEL XTAL_OUT1 XTAL_IN1 GND XTAL_OUT0 VDDX XTAL_IN0 Pin Assignment 32 31 30 29 28 27 26 25 24 N0 LF0 2 23 N1 ISET 3 22 nBP1 VDD 4 21 OE nBP0 5 20 GND GND 6 19 Q CLK_SEL 7 18 VDDO CLK1 8 17 VDDA ICS810001-22 32 Lead VFQFN 5mm x 5mm x 0.925mm package body K Package Top View V3 V2 V1 MF MR 10 11 12 13 14 15 16 VDD 9 V0 1 CLK0 LF1 ICS810001BK-22 REVISION A SEPTEMBER 8, 2009 2 ©2009 Integrated Device Technology, Inc. ICS810001-22 Data Sheet FEMTOCLOCK™ DUAL VCXO VIDEO PLL Table 1. Pin Descriptions Number Name Type Description 1, 2 LF1, LF0 Analog Input/Output Loop filter connection node pins. 3 ISET Analog Input/Output Charge pump current setting pin. 4, 11, 25 VDD Power 5, 22 nBP0, nBP1 Input 6, 20, 29 GND Power 7 CLK_SEL Input Pulldown Input clock select. When HIGH selects CLK1. When LOW, selects CLK0. LVCMOS / LVTTL interface levels. 8, 9 CLK1, CLK0 Input Pulldown Single-ended clock inputs. LVCMOS/LVTTL interface levels. 10, 14, 15, 16 V0, V1, V2, V3 Input Pulldown VCXO PLL divider selection pins. LVCMOS/LVTTL interface levels. 12 MR Input Pulldown Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the output to go low. When logic LOW, the internal dividers and the output is enabled. LVCMOS/LVTTL interface levels. Pulldown Core supply pins. Pullup PLL Bypass control pins. See block diagram. Power supply ground. 13 MF Input 17 VDDA Power Analog supply pin. FemtoClock multiplication factor select pin. LVCMOS/LVTTL interface levels. 18 VDDO Power Output supply pin. 19 Q Output Single-ended VCXO PLL clock output. LVCMOS/LVTTL interface levels. 21 OE Input Pullup 23, 24 N1, N0 Input Pulldown FemtoClock output divide select pins. LVCMOS/LVTTL interface levels. 26 XTAL_SEL Input Pulldown Crystal select. When HIGH, selects XTAL1. When LOW, selects XTAL0. LVCMOS/LVTTL interface levels. 27, 28 XTAL_OUT1, XTAL_IN1 Input Crystal oscillator interface. XTAL_IN1 is the input. XTAL_OUT1 is the output. 30, 31 XTAL_OUT0, XTAL_IN0 Input Crystal oscillator interface. XTAL_IN0 is the input. XTAL_OUT0 is the output. 32 VDDX Power Power supply pin for VCXO charge pump. Output enable. When logic LOW, the clock output is in high-impedance. When logic HIGH, the output is enabled. LVCMOS/LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter CIN Input Capacitance CPD Power Dissipation Capacitance RPULLUP Test Conditions Minimum Typical Maximum Units 4 pF 8.5 pF Input Pullup Resistor 51 kΩ RPULLDOWN Input Pulldown Resistor 51 kΩ ROUT Output Impedance 22.5 Ω ICS810001BK-22 REVISION A SEPTEMBER 8, 2009 VDD = VDDO = 3.465V 3 ©2009 Integrated Device Technology, Inc. ICS810001-22 Data Sheet FEMTOCLOCK™ DUAL VCXO VIDEO PLL Function Tables Table 3A. VCXO PLL Feedback Divider and Input Frequency Function Table Input V3 V2 V1 V0 VCXO PLL Configuration Feedback-Divider M 0 (default) 0 (default) 0 (default) 0 (default) 0 0 0 0 0 0 Input frequency for crystal frequency (fVCXO) in kHz fVCXO = 27MHz fVCXO = 26.973MHz 400 67.5 67.4326 1 480 56.25 56.1938 1 0 600 45.00 44.9550 0 1 1 720 37.50 37.4625 0 1 0 0 800 33.75 33.7163 0 1 0 1 858 31.4685 31.4371 0 1 1 0 864 31.25 31.2188 0 1 1 1 960 28.125 28.0969 1 0 0 0 1000 27.00 26.973 1 0 0 1 1200 22.50 22.4775 1 0 1 0 1440 18.75 18.7313 1 0 1 1 1500 18.00 17.9820 1 1 0 0 1716 15.7343 15.7185 1 1 0 1 1728 15.6250 15.6094 1 1 1 0 1716 15.7343 15.7185 1 1 1 1 960 28.125 28.0969 ICS810001BK-22 REVISION A SEPTEMBER 8, 2009 4 ©2009 Integrated Device Technology, Inc. ICS810001-22 Data Sheet FEMTOCLOCK™ DUAL VCXO VIDEO PLL Table 3B. Output Frequency Table (Dual PLL Mode) FemtoClock Look-up Table fVCXO MF N1 N0 Output Frequency fQ (MHz) 0 0 0 148.5000 0 0 1 74.2500 0 1 0 49.5000 0 1 1 33.0000 1 0 0 162.0000 1 0 1 81.0000 1 1 0 54.0000 1 1 1 36.0000 0 0 0 148.3515 0 0 1 74.1758 0 1 0 49.4505 0 1 1 32.9670 1 0 0 161.8382 1 0 1 80.9191 1 1 0 53.9461 1 1 1 35.9640 27MHz 26.973MHz NOTE: Use the VCXO-PLL mode to achieve output frequencies of 27MHz or 26.973MHz. See Table 3G. Table 3C. CLK_SEL Function Table Input CLK_SEL Operation 0 (default) Selects CLK0 as PLL reference input. 1 Selects CLK1 as PLL reference input. Table 3D. MR Master Reset Function Table Input MR 0 (default) 1 Operation Normal operation, internal dividers and the output Q are enabled. Internal dividers are reset. Q output is in logic low state (with OE = 1). Table 3E. FemtoCLock PLL Feedback Divider Function Table Input MF Operation 0 (default) Selects MF = 22. The 2nd stage PLL (FemtoClock. multiplies the output frequency of the VCXO-PLL by 22. 1 Selects MF = 24. The 2nd stage PLL (FemtoClock. multiplies the output frequency of the VCXO-PLL by 24. ICS810001BK-22 REVISION A SEPTEMBER 8, 2009 5 ©2009 Integrated Device Technology, Inc. ICS810001-22 Data Sheet FEMTOCLOCK™ DUAL VCXO VIDEO PLL Table 3F. PLL Output Divider Function Table Input N1 N0 Operation 0 (default) 0 (default) Output divider N = 4. 0 1 Output divider N = 8. 1 0 Output divider N = 12. 1 1 Output divider N = 18. Table 3G. PLL BYPASS Logic Function Table Input nBP1 nBP0 Operation 0 0 VCXO-PLL mode: The input reference frequency is multiplied by the VCXO-PLL. fOUT = fREF * M. 0 1 Test mode: The input reference frequency is divided by the output divider N and bypasses both PLLs. fOUT = fREF ÷ N. 1 0 FemtoClock Mode: The input reference frequency is multiplied by the 2nd PLL (FemtoClock, MF). The 1st PLL (VCXO-PLL, M) is bypassed. This mode does not support jitter attenuatiion. fOUT = fREF * MF ÷ N. 1 (default) 1 (default) Dual PLL Mode: both PLLs are cascaded for jitter attenuation and frequency multiplication. fOUT = fREF * M * MF ÷ N. ICS810001BK-22 REVISION A SEPTEMBER 8, 2009 6 ©2009 Integrated Device Technology, Inc. ICS810001-22 Data Sheet FEMTOCLOCK™ DUAL VCXO VIDEO PLL Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Rating Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, VO -0.5V to VDDO + 0.5V Package Thermal Impedance, θJA 37°C/W (0 mps) Storage Temperature, TSTG -65°C to 150°C DC Electrical Characteristics Table 4A. Power Supply DC Characteristics, VDD = VDDO = VDDX = 3.3V ± 5%, TA = 0°C to 70°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VDD Core Supply Voltage 3.135 3.3 3.465 V VDDA Analog Supply Voltage VDD – 0.15 3.3 VDD V VDDO Output Supply Voltage 3.135 3.3 3.465 V VDDX Charge Pump Supply Voltage 3.135 3.3 3.465 V IDD Power Supply Current 187 mA IDDA Analog Supply Current 15 mA IDDO Output Supply Current 4 mA IDDX Charge Pump Supply Current 4 mA No Load Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = VDDO = VDDX = 3.3V ± 5%, TA = 0°C to 70°C Symbol Parameter VIH Input High Voltage VIL Input Low Voltage IIH IIL Input High Current Input Low Current Test Conditions Minimum Typical Maximum Units 2 VDD + 0.3 V -0.3 0.8 V CLK[0:1], CLK_SEL, P[1:0], V[3:0], N[1:0], MR, MF, XTAL_SEL VDD = VIN = 3.465V 150 µA OE, nBP0, nBP1 VDD = VIN = 3.465V 5 µA CLK[0:1], CLK_SEL, P[1:0], V[3:0], N[1:0], MR, MF, XTAL_SEL VDD = 3.465V, VIN = 0V -5 µA OE, nBP0, nBP1 VDD = 3.465, VIN = 0V -150 µA 2.6 V VOH Output High Voltage IOH = -24mA VOL Output Low Voltage IOL = 24mA ICS810001BK-22 REVISION A SEPTEMBER 8, 2009 7 0.5 V ©2009 Integrated Device Technology, Inc. ICS810001-22 Data Sheet FEMTOCLOCK™ DUAL VCXO VIDEO PLL AC Electrical Characteristics Table 5. AC Characteristics, VDD = VDDO = VDDX = 3.3V ± 5%, TA = 0°C to 70°C Symbol Parameter fOUT Output Frequency tjit(Ø) RMS Phase Jitter, (Random), NOTE 1 tR / tF Output Rise/Fall Time odc Output Duty Cycle tLOCK VCXO & FemtoClock PLL Lock Time; NOTE 2 Test Conditions Minimum nBP0, nBP1 = 00 Maximum Units 26 28 MHz nBP1 = 1 31 175 MHz 148.5MHz, Integration Range: 12kHz – 20MHz 20% to 80% Typical 1.01 ps 250 750 ps 48 52 % 5 ms NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. See Parameter Measurement Information Section. NOTE 1: Refer to the Phase Noise Plot. NOTE 2: Lock Time measured from power-up to stable output frequency. ICS810001BK-22 REVISION A SEPTEMBER 8, 2009 8 ©2009 Integrated Device Technology, Inc. ICS810001-22 Data Sheet FEMTOCLOCK™ DUAL VCXO VIDEO PLL Typical Phase Noise at 148.3516MHz Noise Power dBc Hz 148.5MHz RMS Phase Jitter (Random) 12kHz to 20MHz = 1.01ps (typical) Offset Frequency (Hz) ICS810001BK-22 REVISION A SEPTEMBER 8, 2009 9 ©2009 Integrated Device Technology, Inc. ICS810001-22 Data Sheet FEMTOCLOCK™ DUAL VCXO VIDEO PLL Parameter Measurement Information 1.65V±5% 1.65V±5% VDD, VDDO, “VDDX SCOPE VDDA Qx LVCMOS 80% 80% Q 20% 20% tR tF GND -1.65±5% Output Rise/Fall Time 3.3V Output Load AC Test Circuit Phase Noise Plot V Noise Power DDO 2 Q t PW t odc = PERIOD t PW x 100% f1 t PERIOD Offset Frequency f2 RMS Jitter = Area Under Offset Frequency Markers Phase Jitter Output Duty Cycle/Pulse Width/Period ICS810001BK-22 REVISION A SEPTEMBER 8, 2009 10 ©2009 Integrated Device Technology, Inc. ICS810001-22 Data Sheet FEMTOCLOCK™ DUAL VCXO VIDEO PLL Application Information Recommendations for Unused Input Pins Inputs: CLK Inputs For applications not requiring the use of a clock input, it can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from the CLK input to ground. LVCMOS Control Pins All control pins have internal pullups or pulldowns; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. Power Supply Filtering Technique As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The ICS810001-22 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA, VDDO and VDDX should be individually connected to the power supply plane through vias, and 0.01µF bypass capacitors should be used for each pin. Figure 1 illustrates this for a generic VDD pin and also shows that VDDA requires that an additional 10Ω resistor along with a 10µF bypass capacitor be connected to the VDDA pin. 3.3V VDD .01µF 10Ω VDDX 10Ω .01µF 10µF VDDA .01µF 10µF Figure 1. Power Supply Filtering ICS810001BK-22 REVISION A SEPTEMBER 8, 2009 11 ©2009 Integrated Device Technology, Inc. ICS810001-22 Data Sheet FEMTOCLOCK™ DUAL VCXO VIDEO PLL VFQFN EPAD Thermal Release Path In order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the Printed Circuit Board (PCB) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in Figure 2. The solderable area on the PCB, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. Sufficient clearance should be designed on the PCB between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. and dependent upon the package power dissipation as well as electrical conductivity requirements. Thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. Maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. It is recommended to use as many vias connected to ground as possible. It is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal land. Precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. Note: These recommendations are to be used as a guideline only. For further information, please refer to the Application Note on the Surface Mount Assembly of Amkor’s Thermally/Electrically Enhance Leadframe Base Package, Amkor Technology. While the land pattern on the PCB provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are necessary to effectively conduct from the surface of the PCB to the ground plane(s). The land pattern must be connected to ground through these vias. The vias act as “heat pipes”. The number of vias (i.e. “heat pipes”) are application specific PIN PIN PAD SOLDER EXPOSED HEAT SLUG GROUND PLANE THERMAL VIA SOLDER LAND PATTERN (GROUND PAD) PIN PIN PAD Figure 2. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale) ICS810001BK-22 REVISION A SEPTEMBER 8, 2009 12 ©2009 Integrated Device Technology, Inc. ICS810001-22 Data Sheet FEMTOCLOCK™ DUAL VCXO VIDEO PLL Schematic Example Figure 3 shows an example of the ICS810001-22 application schematic. In this example, the device is operated at VDD = VDDO = 3.3V. The decoupling capacitors should be located as close as possible to the power pin. The input is driven by a 3.3V LVPECL driver. An optional 3-pole filter can also be used for additional spur reduction. It is recommended that the loop filter components be laid out for the 3-pole option. This will also allow the 2-pole filter to be used. Logic Control Input Examples Set Logic Input to '1' Set Logic Input to '0' VDD RU1 1K RU2 Not Install To Logic Input pins To Logic Input pins RD1 Not Install XTAL_OUT0 RD2 1K C1 SPARE X1 820k R2 Cp 0.68nF C5 220pF 10 VDDX C7 10u C8 0.01u U1 2-pole loop filter with Mid LBW Setting LF LF Rs 150k VDD nPB0 GND CLK_SEL Cp 0.68nF Cs 0.18uF 1 2 3 4 5 6 7 8 C6 0.1u LF1 LF0 ISET VDD nPB0 GND CLK_SEL CLK1 VDD = VDDO = 3.3V N0 N1 nBP1 OE GND Q VDDO VDDA 24 23 22 21 20 19 18 17 N0 N1 nBP1 OE GND R3 VDDO R4 5.6K R5 V0 Ro ~ 7 Ohm R9 Zo = 50 Ohm MR MF V1 V2 V3 VDDA Q1 CLK0 Receiv er C10 0.1u 9 10 11 12 13 14 15 16 VDD C11 0.01u Zo = 50 33 VDDO C LK0 V0 VD D MR MF V1 V2 V3 C9 0.1u C4 SPARE VDD XT AL_SEL Cs 0.18uF VDD GN D Rs 150k LF XTAL_OUT1 C3 SPARE 32 31 30 29 28 27 26 25 LF C2 SPARE X2 XTAL_IN0 3-pole loop filter example - (optional) R1 XTAL_IN1 VD D X XT AL_IN 0 XT AL_OU T 0 GN D XT AL_IN 1 XT AL_OU T 1 XT AL_SEL VD D VDD VDD 10 C12 10u VDD 43 Driv er_LVCMOS C13 0.1u Figure 3. ICS810001-22 Schematic Example ICS810001BK-22 REVISION A SEPTEMBER 8, 2009 13 ©2009 Integrated Device Technology, Inc. ICS810001-22 Data Sheet FEMTOCLOCK™ DUAL VCXO VIDEO PLL VCXO-PLL EXTERNAL COMPONENTS Choosing the correct external components and having a proper printed circuit board (PCB) layout is a key task for quality operation of the VCXO-PLL. In choosing a crystal, special precaution must be taken with the package and load capacitance (CL). In addition, frequency, accuracy and temperature range must also be considered. Since the pulling range of a crystal also varies with the package, it is recommended that a metal-canned package like HC49 be used. Generally, a metal-canned package has a larger pulling range than a surface mounted device (SMD). For crystal selection information, refer to the VCXO Crystal Selection Application Note. The frequency of oscillation in the third overtone mode is not necessarily at exactly three times the fundamental frequency. The mechanical properties of the quartz element dictate the position of the overtones relative to the fundamental. The oscillator circuit may excite both the fundamental and overtone modes simultaneously. This will cause a nonlinearity in the tuning curve. This potential problem is why VCXO crystals are required to be tested for absence of any activity inside a +/-200 ppm window at three times the fundamental frequency. Refer to FL_3OVT and FL_3OVT_spurs in the crystal Characteristics table. The crystal’s load capacitance CL characteristic determines its resonating frequency and is closely related to the VCXO tuning range. The total external capacitance seen by the crystal when installed on a board is the sum of the stray board capacitance, IC package lead capacitance, internal varactor capacitance and any installed tuning capacitors (CTUNE). The crystal and external loop filter components should be kept as close as possible to the device. Loop filter and crystal traces should be kept short and separated from each other. Other signal traces should be kept separate and not run underneath the device, loop filter or crystal components. If the crystal’s CL is greater than the total external capacitance, the VCXO will oscillate at a higher frequency than the crystal specification. If the crystal’s CL is lower than the total external capacitance, the VCXO will oscillate at a lower frequency than the crystal specification. In either case, the absolute tuning range is reduced. The correct value of CL is dependent on the characteristics of the VCXO. The recommended CL in the Crystal Parameter Table balances the tuning range by centering the tuning curve. LF0 LF1 ISET RS CP RSET CS XTAL_IN CTUNE 19.44MHz XTAL_OUT CTUNE VCXO Characteristics Table Symbol Parameter Typical Units kVCXO VCXO Gain 13.65 kHz/V CV_LOW Low Varactor Capacitance 16 pF CV_HIGH High Varactor Capacitance 33 pF VCXO-PLL Loop Bandwidth Selection Table Bandwidth Crystal Frequency (MHz) MF RS (kΩ) CS (µF) CP (nF) RSET (kΩ) 11Hz (Low) 27, 26.973 1728 150 1 10 18 64Hz (Mid) 27, 26.973 1000 150 0.18 0.68 5.6 597Hz (High) 27, 26.973 400 220 0.022 0.12 2.2 Crystal Characteristics Symbol Parameter Test Conditions Minimum Mode of Oscillation Typical Maximum Units Fundamental 27 MHz 26.973 MHz fN Frequency fT Frequency Tolerance ±20 ppm fS Frequency Stability ±20 ppm 70 0C Operating Temperature Range 0 CL Load Capacitance 12 pF CO Shunt Capacitance 4 pF CO / C1 Pullability Ratio ESR Equivalent Series Resistance 20 Ω Drive Level 1 mW ±3 per year ppm Aging @ 25 220 0C ICS810001BK-22 REVISION A SEPTEMBER 8, 2009 14 240 ©2009 Integrated Device Technology, Inc. ICS810001-22 Data Sheet FEMTOCLOCK™ DUAL VCXO VIDEO PLL Reliability Information Table 6. θJA vs. Air Flow Table for a 32 Lead VFQFN θJA vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 37.0°C/W 32.4°C/W 29°C/W Transistor Count The transistor count for ICS810001-22 is: 7283 ICS810001BK-22 REVISION A SEPTEMBER 8, 2009 15 ©2009 Integrated Device Technology, Inc. ICS810001-22 Data Sheet FEMTOCLOCK™ DUAL VCXO VIDEO PLL Package Outline and Package Dimensions Package Outline - K Suffix for 32 Lead VFQFN (Ref.) S eating Plan e N &N Even (N -1)x e (R ef.) A1 Ind ex Area A3 N To p View Anvil Anvil Singulation Singula tion or OR Sawn Singulation L N e (Ty p.) 2 If N & N 1 are Even 2 E2 (N -1)x e (Re f.) E2 2 b A (Ref.) D e N &N Odd Chamfer 4x 0.6 x 0.6 max OPTIONAL 0. 08 Th er mal Ba se D2 2 C D2 C Bottom View w/Type A ID Bottom View w/Type B ID Bottom View w/Type C ID BB 4 CHAMFER 4 N N-1 There are 3 methods of indicating pin 1 corner at the back of the VFQFN package are: 1. Type A: Chamfer on the paddle (near pin 1) 2. Type B: Dummy pad between pin 1 and N. 3. Type C: Mouse bite on the paddle (near pin 1) 2 1 2 1 CC 2 1 4 N N-1 DD 4 RADIUS 4 N N-1 AA 4 Table 7. Package Dimensions NOTE: The following package mechanical drawing is a generic drawing that applies to any pin count VFQFN package. This drawing is not intended to convey the actual pin count or pin layout of this device. The pin count and pinout are shown on the front page. The package dimensions are in Table 7 below. JEDEC Variation: VHHD-2/-4 All Dimensions in Millimeters Symbol Minimum Nominal Maximum N 32 A 0.80 1.00 A1 0 0.05 A3 0.25 Ref. b 0.18 0.25 0.30 8 ND & NE D&E 5.00 Basic D2 & E2 3.0 3.3 e 0.50 Basic L 0.30 0.40 0.50 Reference Document: JEDEC Publication 95, MO-220 ICS810001BK-22 REVISION A SEPTEMBER 8, 2009 16 ©2009 Integrated Device Technology, Inc. ICS810001-22 Data Sheet FEMTOCLOCK™ DUAL VCXO VIDEO PLL Ordering Information Table 8. Ordering Information Part/Order Number 810001BK-22LF 810001BK-22LFT Marking ICS0001B22L ICS0001B22L Package “Lead-Free” 32 Lead VFQFN “Lead-Free” 32 Lead VFQFN Shipping Packaging Tray 2500 Tape & Reel Temperature 0°C to 70°C 0°C to 70°C NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications, such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. ICS810001BK-22 REVISION A SEPTEMBER 8, 2009 17 ©2009 Integrated Device Technology, Inc. ICS810001-22 Data Sheet 6024 Silver Creek Valley Road San Jose, California 95138 FEMTOCLOCK™ DUAL VCXO VIDEO PLL Sales 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT Technical Support [email protected] +480-763-2056 DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. 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Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright 2009. All rights reserved.